CN106409810B - 具有堆叠通孔的再分布线 - Google Patents
具有堆叠通孔的再分布线 Download PDFInfo
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- CN106409810B CN106409810B CN201510797011.1A CN201510797011A CN106409810B CN 106409810 B CN106409810 B CN 106409810B CN 201510797011 A CN201510797011 A CN 201510797011A CN 106409810 B CN106409810 B CN 106409810B
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- hole
- redistribution lines
- metal trace
- dielectric layer
- opening
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Abstract
一种方法,包括:在导电部件上方形成第一介电层;在第一介电层中形成开口;以及镀金属材料以形成电耦合至导电部件的第一再分布线。再分布线包括位于开口中的通孔和金属迹线。该金属迹线包括直接位于通孔上方的第一部分和与通孔不重合的第二部分。金属迹线的第一部分的第一顶面与第二部分的第二顶面基本共面。本发明还提供了一种具有堆叠通孔的再分布线。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地,涉及封装件的形成方法。
背景技术
随着半导体技术的进步,半导体芯片/管芯变得越来越小。同时,需要将更多的功能集成到半导体管芯中。因此,半导体管芯需要需要在更小的区域中封装越来越多的I/O焊盘,并且I/O焊盘的密度随时间快速增加。结果,半导体管芯的封装变得更加困难,对封装的产量产生不利的影响。
传统的封装技术可以划分为两类。在第一类中,晶圆上的管芯在被切割之前进行封装。这种封装技术具有一些有利的特征,诸如更大的产量和更低的成本。此外,需要较少的底部填充或模塑料。然而,这种封装技术还具有一些缺陷。管芯的尺寸变得越来越小,并且对应的封装件仅可以为多输入型封装件,其中每个管芯的I/O焊盘限于直接位于对应管芯的表面上方的区域。在管芯具有有限面积的情况下,I/O焊盘的数量由于I/O焊盘的间距的限制而受限。如果焊盘的间距减小,则会发生焊料桥接。此外,在固定焊球尺寸的要求下,焊球必须具有特定尺寸,从而又限制了可封装在管芯表面上的焊球的数量。
在另一类封装中,管芯在被封装之前从晶圆上切割下来。这种封装技术的有利特征在于可能形成多输出型封装件,这意味着管芯上的I/O焊盘可以再分布到比管芯更大的面积,因此可以增加管芯表面上封装的I/O焊盘的数量。这种封装技术的另一有利特征在于“已知良好管芯”被封装而有缺陷管芯被丢弃,因此不会将成本和精力浪费在有缺陷管芯上。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种方法,包括:在导电部件上方形成第一介电层;在所述第一介电层中形成第一开口;以及镀金属材料以形成电耦合至所述导电部件的第一再分布线,其中所述第一再分布线包括:第一通孔,位于所述第一开口中;和第一金属迹线,包括直接位于所述第一通孔上方的第一部分和与所述第一通孔不重合的第二部分,所述第一金属迹线的所述第一部分的第一顶面与所述第二部分的第二顶面基本共面。
根据本发明的另一方面,提供了一种方法,包括:在导电部件上方形成第一介电层;在所述第一介电层中形成第一开口,通过所述第一开口露出所述导电部件的一部分;镀第一再分布线,所述第一再分布线包括:第一通孔,位于所述第一开口中;和第一金属迹线,包括直接位于所述第一通孔上方的第一部分和与所述第一通孔不重合的第二部分;在所述第一金属迹线上方形成第二介电层;在所述第二介电层中形成第二开口,通过所述第二开口露出所述第一金属迹线的第一部分的第一顶面;以及镀第二再分布线,所述第二再分布线包括:第二通孔,位于所述第二开口中,所述第二通孔包括与所述第一再分布线的第一顶面接触的底面;和第二金属迹线,包括直接位于所述第二通孔上方的第三部分和与所述第二通孔不重合的第四部分。
根据本发明的又一方面,提供了一种方法,包括:在密封材料中密封器件管芯;执行平坦化以露出所述器件管芯内的金属柱;形成与所述器件管芯和所述密封材料均重叠的第一聚合物层;在所述第一聚合物层中形成第一开口以露出所述金属柱;形成第一再分布线,所述第一再分布线包括位于所述第一开口中的第一通孔和位于所述第一聚合物层上方的第一金属迹线;在所述第一再分布线上方形成第二聚合物层;在所述第二聚合物层中形成第一开口阵列以露出所述第一再分布线;镀第二再分布线,所述第二再分布线包括:第一通孔阵列,位于所述第一开口阵列中;和第二金属迹线,位于所述第一通孔阵列上方并接触所述第一通孔阵列;在所述第二再分布线上方形成第三聚合物层;在所述第三聚合物层中形成第二开口阵列以露出所述第二再分布线;以及镀第三再分布线,所述第三再分布线包括:第二通孔阵列,位于所述第二开口阵列中,所述第二通孔阵列中的每个通孔均以一一对应的关系与所述第一通孔阵列中的一个通孔重叠;和第三金属迹线,位于所述第二通孔阵列上方并接触所述第二通孔阵列。
附图说明
当阅读附图时,根据以下的详细描述来更好地理解本发明的各个方面。注意,根据工业的标准实践,各个部件没有按比例绘制。实际上,为了讨论的清楚,可以任意地增加或减小各个部件的尺寸。
图1至图21示出了根据一些实施例的形成封装件的中间阶段的截面图。
图22A、图22B、图22C和图22D示出了根据一些实施例的再分布线的多种轮廓。
图23示出了根据一些实施例的形成封装件的工艺流程。
具体实施方式
以下公开提供了许多不同的用于实施本发明主题的不同特征的实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然,这些仅仅是实例而不用于限制。例如,在以下的描述中,在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例,并且也可以包括可以在第一部件和第二部件形成附件部件使得第一部件和第二部分没有直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚,其本身并不表示所讨论的各个实施例和/或结构之间的关系。
此外,为了易于描述,可以使用空间相对术语(诸如“在…下方”、“之下”、“下部”、“在…上方”、“上部”等)以描述图中所示一个元件或部件与另一个元件或部件的关系。除图中所示的定向之外,空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向),本文所使用的空间相对描述可因此进行类似的解释。
根据各个示例性实施例提供了堆叠封装(PoP)结构/封装件和形成该封装件的方法。讨论了实施例的一些变形例。在各附图和所示实施例中,类似的参考标号用于表示类似的元件。应该理解,尽管封装件的形成被用作实例,但本发明内容的教导可容易地用于其他集成电路部件(诸如晶圆/ 管芯、中介片、封装衬底等)的形成。
图1至图21示出了根据一些实施例的封装件形成的中间阶段的截面图。在随后的讨论中,参照图23中的工艺步骤来讨论图1至图21所示的工艺步骤。
参照图1,设置载体30,并在载体30上方设置粘合层32。载体30可以是空白玻璃载体、空白陶瓷载体等,并且可以具有半导体晶圆的形状,其具有圆形顶视图形状。载体30有时被称为载体晶圆。粘合层32例如可由光热转换(LTHC)材料形成,但是还可以使用其他类型的粘合剂。根据本发明的一些实施例,粘合层32能够在光热的作用下分解,因此可以将载体30与其上形成的结构分离。
参照图2,在粘合层32上方形成介电层34。在图23所示的工艺流程中以步骤202示出对应步骤。根据本发明的一些实施例,介电层34是由聚合物形成的聚合物层,其可以是光敏聚合物,诸如聚苯并恶唑(PBO)、聚酰亚胺等。根据一些实施例,介电层34由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸玻璃(PSG)、硼硅酸玻璃(BSG)、掺硼磷硅酸玻璃(BPSG)等形成。
参照图3,例如通过物理气相沉积(PVD),在介电层34上方形成导电晶种层40。在图23所示的工艺流程中以步骤206示出对应步骤。导电晶种层40可以是金属晶种层,包括铜、铝、钛、它们的合金或者它们的多层。根据本发明的一些实施例,导电晶种层40包括诸如钛层的第一金属层 (未示出)和位于第一金属层上方的诸如铜层的第二金属层(未示出)。根据本发明的可选实施例,导电晶种层40包括诸如铜层的单个金属层,其可以由基本纯的铜或铜合金形成。
图4至图7示出了通孔的形成。如图4所示,掩模层42(诸如光刻胶) 应用于导电晶种层40上方,然后使用光刻掩模进行图案化。在图23所示的工艺流程中以步骤208示出对应的步骤。根据本发明的一些实施例,掩模层42由干膜形成,其层压在导电晶种层40上。根据一些实施例,通过旋涂来形成掩模层42。作为图案化(曝光和显影)的结果,在掩模层42 中形成开口44,通过该开口露出导电晶种层40的一些部分。掩模层42的厚度被选择为接近随后放置的器件管芯48(图8)的厚度。根据本发明的一些实施例,掩模层42的厚度大于器件管芯48的厚度。
如图5所示,通过镀(可以为电镀或无电镀)在开口44中形成通孔 46。在图23所示的工艺流程中以步骤210示出对应的步骤。在导电晶种层40的露出部分上镀通孔46。通孔46是导电的,并且可以是包括铜、铝、钨、镍或它们的合金的金属通孔。通孔46的顶视图形状包括但不限于矩形、正方形、圆形等。根据本发明的一些实施例,通过随后放置的器件管芯48(图8)的厚度来确定通孔46的高度,其中通孔46的高度稍大于或等于器件管芯48的厚度。
在镀通孔46之后,去除掩模层42,并且在图6中示出所得到的结构。在图23所示的工艺流程中以步骤212示出对应的步骤。结果,露出导电晶种层40中先前被光刻胶42覆盖的部分。
接下来,如图7所示,执行蚀刻步骤以去除导电晶种层40的暴露部分,其中蚀刻可以是各向异性或各向同性蚀刻。在图23所示的工艺流程中以步骤212示出对应的步骤。另一方面,导电晶种层40与通孔46重叠的部分保持不被蚀刻。在整个描述中,导电晶种层40的剩余下面部分被称为通孔 46的底部。尽管导电晶种层40被示为与通孔46的上覆部分的可辨识的界面,但当导电晶种层40由与对应的上覆通孔46相似或相同的材料形成时,导电晶种层40的一些或所有可以与通孔46合并而在其间没有可辨识的界面。例如,导电晶种层40中的铜层可以与通孔46合并而没有可辨识的界面。根据可选实施例,在导电晶种层40与通孔46的对应上覆镀部分之间存在可辨识的界面。例如,导电晶种层40中的钛层可以与含铜通孔46区别开来。作为导电晶种层40的蚀刻的结果,露出介电层34。
图8示出了在介电层34上方放置器件管芯48。在图23所示的工艺流程中以步骤214示出对应的步骤。器件管芯48可以通过器件附接膜50(粘合膜)粘附至介电层34。器件附接膜50的边缘与器件管芯48的对应边缘共终端(对齐)。应该理解,尽管示出了一个器件管芯48,但可以在介电层34上方放置多个器件管芯48。多个放置的器件管芯48可以配置为包括多行和多列的阵列。器件管芯48可以包括背面(面朝下的表面)与对应下方的管芯附接膜50物理接触的半导体衬底。器件管芯48还包括位于半导体衬底的前面(面朝上的表面)处的集成电路器件(诸如有源器件,例如包括晶体管,未示出)。器件管芯48可以是逻辑管芯,诸如中央处理单元 (CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯等。
器件管芯48可以包括接近其顶面的金属柱54。金属柱54可以电耦合至器件管芯48内的集成电路(诸如晶体管)。根据本发明的一些示例性实施例,如图8所示,金属柱54被介电层51覆盖,介电层51的顶面高于金属柱54的顶面。介电层51进一步延伸到金属柱54之间的间隙中。根据本发明的可选实施例,金属柱54的顶面与对应的介电层51的顶面共面。根据一些示例性实施例,介电层51可以由诸如PBO的聚合物形成。金属柱 54可以是铜柱,并且还可以包括诸如铝、镍等的其他导电/金属材料。
参照图9,密封材料52被密封在器件管芯48和通孔46上。在图23 所示的工艺流程中以步骤216示出对应的步骤。密封材料52填充相邻器件管芯48之间的间隙,并环绕每一个器件管芯48。密封材料52可以包括模塑料、模制底部填充物、环氧树脂或树脂。在密封工艺之后,密封材料52 的顶面高于金属柱54和通孔46的顶端。
接下来,执行诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化工艺以平坦化密封材料52,直到露出通孔46为止。在图23所示的工艺流程中以步骤216示出对应的步骤。在图10中示出所得到的结构。器件管芯 48的金属柱54也作为平坦化的结果而露出。由于平坦化,通孔46的顶面基本与金属柱54的顶面平齐(共面),并且基本与密封材料52的顶面平齐(共面)。
图11至图18示出了前侧RDL和对应介电层的形成。参照图11,形成介电层56。在图23所示的工艺流程中以步骤218示出对应的步骤。根据本发明的一些实施例,介电层56由有机材料形成,其可以是诸如PBO、聚酰亚胺、聚并环丁烯(BCB)等的聚合物。根据一些实施例,介电层56 由无机材料形成,诸如氮化硅、氧化硅等。介电层56可以涂覆为流体,然后固化。根据一些实施例,介电层56由预形成膜形成并且被层压。开口 58形成在介电层56中以露出通孔46和金属柱54。可以通过光刻工艺来执行开口58的形成。
还如图11所示,形成晶种层60,其包括延伸到开口58(图11)中的部分和位于介电层56上方的部分。晶种层60可以包括钛层和位于钛层上方的铜层。可选地,晶种层60包括铜层而不具有钛层。例如可以使用物理气相沉积(PVD)来形成晶种层60。
接下来,参照图12,在晶种层60上方形成图案化掩模62。根据一些实施例,图案化掩模62由光刻胶形成,其被图案化以露出晶种层60的一些部分。接下来,执行镀步骤以在图案化掩模62的开口中形成再分布线 (RDL)64,其中诸如铜的金属材料被镀在晶种层60的露出部分上。在图 23所示的工艺流程中以步骤220示出对应的步骤。RDL 64连接至金属柱 54和通孔46。RDL 64包括位于介电层56上方的金属迹线(包括金属线和 /或金属焊盘)64A。RDL 64还包括位于开口58(图11)中的通孔64B。晶种层60与镀材料重叠的部分还被认为是RDL 64的部分。在镀之后,去除图案化掩模62,露出下方晶种层60的部分。如图13所示,然后蚀刻晶种层60的露出部分,留下RDL 64。
根据本发明的一些实施例,控制镀工艺并选择通孔64B的尺寸,使得 RDL 64的顶面平坦或基本平坦。图22A、图22B、图22C和图22D示出了通孔64B和对应的连接金属迹线64A的一些示例性截面形状。在这些实例中,金属迹线64A包括与通孔64B不重合(不直接位于其上方)的金属迹线部分64A’。金属迹线部分64A’的顶面64A1是平坦的,而通孔64B和上方的金属迹线部分(64A”)可以具有不同的轮廓。图22A示出了共形 RDL 64。RDL 64的不同部分(包括通孔64B和金属迹线64A)具有相同 (或基本相同)的厚度T1。因此,通孔64B的顶面64B1的最低点比顶面 64A1低高度差ΔH,该高度差等于介电层56的厚度T2。
图22B示出了RDL 64的轮廓,其包括具有凹部的金属迹线64A以及位于金属迹线64A下方的通孔64B。金属迹线64A包括直接位于通孔64B 上方的部分64A”以及高于通孔64B但不与通孔64B对齐的部分64A’。金属迹线部分64A”的顶面64B1的最低点的中心从金属迹线部分64A’的顶面 64A1凹陷。高度差ΔH小于介电层56的厚度T2,并且可以小于厚度T1。在这些实施例中,顶面64B1的最低点还可以高于介电层56的顶面56A。
图22C示出了RDL 64的轮廓,其包括具有凸块的金属迹线64A以及直接位于凸块下方的通孔64B。金属迹线部分64A”的顶面64B1的中心高于金属迹线部分64A’的顶面64A1。凸块的最高点和顶面64A1之间的高度差ΔH大于约0.5μm,并且可以大于约1μm。
图22D示出了RDL 64的轮廓,其具有彼此相互共面或基本彼此共面的顶面金属迹线部分64A’和64A”。根据本发明的这些实施例,由于具有基本共面顶面的RDL 64,金属迹线64A”的最高点(如果为凸块)或最低点(如果为凹部)与金属迹线部分64A’的顶面64A1之间的高度差ΔH(如果有的话)小于约1μm,并且可以小于约0.5μm。注意,RDL 64的顶面被认为是(基本)平坦还是不平坦与金属迹线部分64A’的厚度T1相关,如果认为是平坦或基本平坦,则厚度T1越小,需要的高度差ΔH越小。在整个描述中,术语“基本平坦”表示高度差ΔH小于厚度T1的20%或者更小。根据布线要求,术语“基本平坦”也可以表示高度差ΔH小于厚度T1的10%或5%,或者更小。例如,当厚度T1约为2μm时,ΔH需要小于0.4μm或者更小,而当厚度T1约为4μm时,ΔH需要小于约0.8μm或者更小。根据本发明的一些实施例,RDL的平坦顶面是镀的结果,并且没有将诸如化学机械抛光(CMP)或研磨的平坦化用于实现平坦的顶面。
根据本发明的一些实施例,可以共同地调整各种因素来实现图22D所示的轮廓,其中RDL 64具有平坦或基本平坦的顶面。例如,可以减小通孔尺寸Wv1(长度或宽度)以实现平坦的RDL顶面。意识到,如果通孔尺寸Wv1太大,则可以形成图22A所示的轮廓。减小通孔尺寸Wv1,可以实现图22B所示的轮廓。然而,如果通孔尺寸太小,则不期望在通孔64B 中形成凸块(图22C)、接缝或气隙。因此,通孔尺寸需要在特定范围内。根据一些示例性实施例,为了实现图22D所示平坦的顶面,通孔尺寸Wv1 可以小于约10μm。通孔尺寸Wv1还可以小于约7μm和大于约4μm。
影响RDL 64的顶面轮廓的其他因素包括用于镀RDL 64(图12)的镀速率(每单位时间厚度的增加)。较低的镀速率可以导致图22A所示的共形RDL 64。当镀速率增加时,可以实现图22B的轮廓。进一步增加镀速率可以产生图22D所示的平坦顶面。在一些实施例中,进一步增加镀速率可以引起图22C所示的凸块。根据一些示例性实施例,镀速率在大约0.1微米/分钟和大约1.0微米/分钟的范围内。可以通过调整用于镀的电流来测量 (和控制)镀速率,其中通过对应的镀溶液传导电流。在一些示例性实施例中,电流大于约2.0安培/平方分米(ASD)以形成具有平坦顶面的RDL。除这些因素之外,诸如RDL 64的厚度的其他因素也影响RDL 64的轮廓。意识到,各种因素共同影响RDL 64的顶面轮廓,并且可以通过实验针对所选RDL找到最佳的通孔尺寸和镀速率。
参照图13,根据一些实施例,介电层66形成在RDL 64上方。在图 23所示工艺流程中以步骤222示出对应的步骤。介电层66可以由从用于形成介电层56的相同候选材料中所选择的材料形成,并且可以通过涂覆或层压来形成该介电层。然后,如图14所示,在介电层66中形成开口68以露出RDL 64。
接下来,执行镀步骤,可以类似于图12中RDL 64的形成来执行该镀步骤。结果,如图15所示,形成RDL 70。在图23所示的工艺流程中以步骤224示出对应的步骤。RDL 70包括金属迹线70A和通孔70B。类似地,当采用不同的通孔尺寸和/或不同的镀速率时,也可以使RDL 70具有不同的顶面轮廓。根据本发明的一些实施例,如参照图22B至图22D所讨论的,选择诸如通孔70B的尺寸和镀速率的形成因素,使得RDL 70的顶面是基本平坦的。
图15示出了堆叠通孔,其中一些通孔70B与对应下方的通孔64B垂直对齐(直接位于其上方)。当下面的RDL具有平坦顶面时,即使上面的通孔直接位于下方的通孔上方,上面的RDL 70的顶面也不会凹陷或凸起。如果下面的RDL 64具有图22A、图22B或图22C所示的轮廓,则会影响上方的RDL 70的轮廓,其中,RDL 70直接位于通孔64B上方的顶面被凹陷或凸起。当更多的通孔被直接堆叠在已经堆叠的通孔上方时,凹陷效应或凸起效应会愈加严重,最终由凹陷或凸起引起的拓扑结构可能会导致上部(或顶部)RDL断裂。在本发明的实施例中,通过使RDL 64和70的顶面平坦,可以消除这些问题。
参照图16,根据各个实施例,介电层72形成在RDL 70上方。在图 23所示的工艺流程中以步骤226示出对应的步骤。介电层72可以由从用于形成介电层56的相同候选材料中所选择的材料形成,并且可以通过涂覆或层压形成该介电层。然后,如图16所示,在介电层72中形成开口74。
接下来,执行镀步骤,可以类似于图12中的RDL 64的形成而执行该镀步骤。结果,如图17所示,形成RDL 76(包括76C、76D和76E)。在图23所示的工艺流程中以步骤228示出对应的步骤。RDL 76包括金属迹线76A和通孔76B。根据本发明的一些实施例,如参照图22B至图22D所讨论,选择通孔76B的尺寸和镀速率,使得RDL 76的顶面基本共面。
图17还示出了直接堆叠在已经堆叠的通孔70B和64B上方的更多的通孔76B。此外,一些通孔76B连接至相同的金属迹线76A。例如,如图 17所示,三个所示通孔76B连接至相同的金属迹线76A1,并且两个所示通孔76B连接至相同金属迹线76A2。根据一些实施例,通孔76B可以形成阵列(例如,2×2阵列、2×3阵列或3×3阵列)。每个通孔76B都可以一一对应关系与一个通孔70B对齐。应该理解,在芯片中,可以需要不同的通孔尺寸。例如,用于传导电源(诸如VDD)通孔由于更大的电流而需要大于信号通孔。然而,增加通孔的尺寸会导致相同芯片上对应的RDL具有不同的轮廓(图22A至图22D),因此如前所述,由通孔凹陷或突出而使得堆叠通孔存在问题。在本发明的实施例中,无论何时需要较大的通孔,较大的通孔都与较小通孔分离,使得相同介电层中的所有通孔的尺寸(在同一封装件中)都基本均匀。例如,在所示的封装件中,相同层级的通孔的尺寸在预期通孔尺寸的大约80%至大约120%的范围内。
参照图18,介电层78形成在RDL 76上方。介电层78也由从用于形成介电层56的相同候选材料所选择的材料形成,并且可以通过涂覆或层压来形成该介电层。然后,在介电层78中形成开口80。
图19示出了根据本发明的一些示例性实施例的电连接件82的形成。在图23所示的工艺流程中以步骤230示出对应的步骤。电连接件82电耦合至RDL 64/70/76、金属柱54和/或通孔46。电连接件82的形成可以包括:在RDL 76上方放置焊球,然后回流焊盘。根据本发明的可选实施例,电连接件82的形成包括执行镀步骤以在RDL 76上方形成焊料区域,然后回流焊料区域。根据一些实施例,焊料印刷工艺用于形成电连接件82。电连接件82还可以包括金属柱,或者金属柱和焊料盖,也可以通过镀工艺来形成该电连接件。在整个说明书中,包括器件管芯48、通孔46、密封材料 52、RDL 64/70/76和介电材料56/66/72的组合结构被称为晶圆级封装件84,该组合结构是包括多个器件管芯48的组合晶圆。
图19示出了三个RDL层。根据一些实施例,根据对应封装件的布线要求,可以具有单层、双层或多于三层的RDL。
接下来,封装件84与载体30分离(图19)。根据示例性剥离工艺,切割带86(图20)附接至封装件84以保护电连接件82,其中切割带86 固定至切割框架(未示出)。例如,通过在粘合层32(图19)上照射UV 光或激光来执行剥离。例如,当粘合层32由LTHC形成时,由光或激光所生成的热量使得LTHC分解,因此载体30与晶圆级封装件84分离。在图 20中示出所得到的结构。
图20还示出了用于在介电层34中形成开口88的图案化。在图23所示的工艺流程中以步骤232示出对应的步骤。例如,当介电层34是聚合物层时,可以使用激光钻(通过激光束89)进行图案化,以去除与通孔46 重叠的部分,使得通过开口88露出通孔46。
在导电晶种层40的一部分由钛形成的实施例中,导电晶种层40的钛层也可以被去除。例如,氟化氢(HF)气体或稀释HF溶液可用于蚀刻钛。导电晶种层40中的铜被露出,因此其上可以形成随后形成的背侧RDL或电连接件,诸如焊料区域。
在后续步骤中,如图20所示,封装件84被切割为多个封装件184,每一个封装件184都包括器件管芯48和对应的通孔46中的一个。在图23 所示的工艺流程中以步骤234示出对应的步骤。
图21示出了封装件300与封装件184的接合,因此形成PoP封装件 20。在图23所示的工艺流程中以步骤236示出对应的步骤。封装件300和 184也被分别称为PoP封装件20的顶部封装件和底部封装件。在图21所示的示例性实施例中,在封装件184中没有示出背侧RDL,而可以根据可选实施例来形成背侧RDL。通过焊料区域90来执行接合,该焊料区域将通孔46接合至上覆封装件300中的金属焊盘。根据本发明的一些实施例,封装件300包括器件管芯304,该器件管芯可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储管芯。在一些示例性实施例中,存储管芯还可以接合至封装衬底302。在将顶部封装件300接合至底部封装件184之后,在顶部封装件300和底部封装件 184之间的间隙中设置底部填充物87,然后进行固化该底部填充物。
本发明的一些实施例具有一些有利特征。通过形成RDL与它们的通孔并且RDL具有相互基本共面的顶面,可以在下部通孔上方直接堆叠更多的通孔而不需要关注由高拓扑结构所引起的问题。这具有两个有利特征。首先,如果不使用本发明的实施例,则上覆通孔可能与下方的通孔不重合,以防止拓扑结构随着RDL层数量的增加而变得日益严峻。在本发明的一些实施例中,可以堆叠通孔,并且节省了芯片面积。RDL可以放置为相互更靠近。第二,通过堆叠通孔,可以缩短信号路径,因此可以降低诸如由加长的信号路径所引起的寄生电容的副作用。这尤其有利于高频信号。
根据本发明的一些实施例,一种方法包括:在导电部件上方形成第一介电层;在第一介电层中形成第一开口;以及镀金属材料以形成电耦合至导电部件的再分布线。再分布线包括位于开口中的通孔和金属迹线。该金属迹线包括直接位于通孔上方的第一部分和与通孔不重合的第二部分。金属迹线的第一部分的第一顶面与第二部分的第二顶面基本共面。
优选地,方法还包括:在所述第一金属迹线上方形成第二介电层;在所述第二介电层中形成第二开口,通过所述第二开口露出所述第一金属迹线的第一部分;以及镀附加金属材料以形成第二再分布线,其中,所述第二再分布线包括:第二通孔,位于所述第二开口中,所述第二通孔包括与所述第一顶面接触的底面;和第二金属迹线,包括直接位于所述第二通孔上方的第三部分和与所述第二通孔不重合的第四部分,所述第二金属迹线的所述第三部分的第三顶面与所述第四部分的第四顶面基本共面。
优选地,方法还包括:形成位于所述第二金属迹线上方并且电耦合至所述第二金属迹线的焊料区域。
优选地,所述焊料区域与所述第一通孔和所述第二通孔在垂直方向上不重合。
优选地,对所述第一金属迹线不执行平坦化。
优选地,形成所述第一介电层包括涂覆聚合物。
优选地,形成所述第一介电层包括层压聚合物膜。
优选地,方法还包括:在密封材料中密封器件管芯,所述第一介电层覆盖所述器件管芯和所述密封材料。
优选地,所述第一再分布线位于封装件中,所述封装件包括位于所述第一介电层中的多个通孔,并且所述第一介电层中的所有通孔均具有基本相同的尺寸。
根据本发明的可选实施例,一种方法包括:在导电部件上方形成第一介电层;在第一介电层中形成第一开口,通过第一开口露出导电部件的一部分;以及镀第一再分布线,第一再分布线包括第一通孔和第一金属迹线。第一通孔位于所述第一开口中。第一金属迹线包括直接位于第一通孔上方的第一部分和与通孔不重合的第二部分。该方法还包括:在第一金属迹线上方形成第二介电层;在第二介电层中形成第二开口,通过第二开口露出第一金属迹线的第一部分的第一顶面;以及镀第二再分布线。第二再分布线包括第二通孔和第二金属迹线。第二通孔位于第二开口中,并包括与第一再分布线的第一顶面接触的底面。第二金属迹线包括直接位于第二通孔上方的第三部分和与第二通孔不重合的第四部分。
优选地,所述第一顶面与所述第一金属迹线的第二部分的第二顶面基本共面,并且在形成所述第一金属迹线的过程中不对所述第一再分布线执行平坦化。
优选地,所述第一顶面和所述第二顶面之间的高度差小于约1.0μm。
优选地,所述第一再分布线包括位于所述第一介电层中的第一通孔阵列,所述第一通孔位于所述第一通孔阵列中,并且第二再分布线包括位于所述第二介电层中的第二通孔阵列,所述第二通孔位于所述第二通孔阵列中,并且所述第二通孔阵列中的每一个通孔均以一一对应的关系直接位于所述第一通孔阵列中的一个通孔上方。
优选地,方法还包括与所述第二再分布线物理接触的焊料区域,所述焊料区域与所述第二通孔不重合。
根据本发明的可选实施例,一种方法包括:在密封材料中密封器件管芯;执行平坦化以露出器件管芯内的金属柱;形成与器件管芯和密封材料均重叠的第一聚合物层;在第一聚合物层中形成第一开口以露出金属柱;以及形成包括第一通孔和第一金属线的第一再分布线。第一通孔位于第一开口中。第一金属迹线位于第一聚合物层上方。该方法还包括:在第一再分布线上方形成第二聚合物层;在第二聚合物层中形成第一开口阵列以露出第一再分布线;镀第二再分布线,该第二再分布线包括第一通孔阵列和第二金属迹线。第一通孔阵列位于第一开口阵列中。第二金属迹线位于第一通孔阵列上方并接触第一通孔阵列。该方法还包括:在第二再分布线上方形成第三聚合物层;在第三聚合物层中形成第二开口阵列以露出第二再分布线;以及镀第三再分布线,该第三再分布线包括第二通孔阵列和第三金属迹线。第二通孔阵列位于第二开口阵列中,其中,第二通孔阵列中的每个通孔均以一一对应的关系与第一通孔阵列中的一个通孔重叠。第三金属迹线位于第二通孔阵列上方并接触第二通孔阵列。
优选地,镀所述第一再分布线包括:在所述第一聚合物层上方形成晶种层;在所述晶种层上方形成图案化掩模;在所述图案化掩模的开口中以及在所述晶种层上方镀所述第一再分布线;去除所述图案化掩模;以及去除所述晶种层中被去除的所述图案化掩模所覆盖的部分。
优选地,方法还包括:直接在所述第二通孔阵列上方堆叠第三通孔阵列。
优选地,在镀之后,所述第二再分布线的整个顶面基本平坦。
优选地,方法包括:形成电耦合至所述第二通孔阵列的焊料区域。
优选地,所述焊料区域与所述第二通孔阵列不重合。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以容易地以本发明为基础设计或修改其他用于执行与本文所述实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员还应该意识到,这些等效结构不背离本发明的精神和范围,并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。
Claims (18)
1.一种形成封装件的方法,包括:
在导电部件上方形成第一介电层;
在所述第一介电层中形成第一开口;以及
镀金属材料以形成电耦合至所述导电部件的第一再分布线,其中所述第一再分布线包括:
第一通孔,位于所述第一开口中;和
第一金属迹线,包括直接位于所述第一通孔上方的第一部分和与所述第一通孔不重合的第二部分,所述第一金属迹线的所述第一部分的第一顶面与所述第二部分的第二顶面共面;
在所述第一金属迹线上方形成第二介电层;
在所述第二介电层中形成第二开口,通过所述第二开口露出所述第一金属迹线的第一部分;以及
镀附加金属材料以形成第二再分布线,其中,所述第二再分布线包括:
第二通孔,位于所述第二开口中,所述第二通孔包括与所述第一顶面接触的底面;和
第二金属迹线,包括直接位于所述第二通孔上方的第三部分和与所述第二通孔不重合的第四部分,所述第二金属迹线的所述第三部分的第三顶面与所述第四部分的第四顶面共面。
2.根据权利要求1所述的方法,还包括:
形成位于所述第二金属迹线上方并且电耦合至所述第二金属迹线的焊料区域。
3.根据权利要求2所述的方法,其中,所述焊料区域与所述第一通孔和所述第二通孔在垂直方向上不重合。
4.根据权利要求1所述的方法,其中,对所述第一金属迹线不执行平坦化。
5.根据权利要求1所述的方法,其中,形成所述第一介电层包括涂覆聚合物。
6.根据权利要求1所述的方法,其中,形成所述第一介电层包括层压聚合物膜。
7.根据权利要求1所述的方法,还包括:
在密封材料中密封器件管芯,所述第一介电层覆盖所述器件管芯和所述密封材料。
8.根据权利要求1所述的方法,其中,所述第一再分布线位于封装件中,所述封装件包括位于所述第一介电层中的多个通孔,并且所述第一介电层中的所有通孔均具有相同的尺寸。
9.一种形成封装件的方法,包括:
在导电部件上方形成第一介电层;
在所述第一介电层中形成第一开口,通过所述第一开口露出所述导电部件的一部分;
镀第一再分布线,所述第一再分布线包括:
第一通孔,位于所述第一开口中;和
第一金属迹线,包括直接位于所述第一通孔上方的第一部分和与所述第一通孔不重合的第二部分;
在所述第一金属迹线上方形成第二介电层;
在所述第二介电层中形成第二开口,通过所述第二开口露出所述第一金属迹线的第一部分的第一顶面;以及
镀第二再分布线,所述第二再分布线包括:
第二通孔,位于所述第二开口中,所述第二通孔包括与所述第一金属迹线的第一顶面接触的底面;和
第二金属迹线,包括直接位于所述第二通孔上方的第三部分和与所述第二通孔不重合的第四部分;
其中,所述第一顶面和所述第一金属迹线的第二部分的第二顶面之间的高度差小于1.0μm。
10.根据权利要求9所述的方法,其中,在形成所述第一金属迹线的过程中不对所述第一再分布线执行平坦化。
11.根据权利要求9所述的方法,其中,所述第一再分布线包括位于所述第一介电层中的第一通孔阵列,所述第一通孔位于所述第一通孔阵列中,并且第二再分布线包括位于所述第二介电层中的第二通孔阵列,所述第二通孔位于所述第二通孔阵列中,并且所述第二通孔阵列中的每一个通孔均以一一对应的关系直接位于所述第一通孔阵列中的一个通孔上方。
12.根据权利要求9所述的方法,还包括与所述第二再分布线物理接触的焊料区域,所述焊料区域与所述第二通孔不重合。
13.一种形成封装件的方法,包括:
在密封材料中密封器件管芯;
执行平坦化以露出所述器件管芯内的金属柱;
形成与所述器件管芯和所述密封材料均重叠的第一聚合物层;
在所述第一聚合物层中形成第一开口以露出所述金属柱;
形成第一再分布线,所述第一再分布线包括位于所述第一开口中的第一通孔和位于所述第一聚合物层上方的第一金属迹线;
在所述第一再分布线上方形成第二聚合物层;
在所述第二聚合物层中形成第一开口阵列以露出所述第一再分布线;
镀第二再分布线,所述第二再分布线包括:
第一通孔阵列,位于所述第一开口阵列中;和
第二金属迹线,位于所述第一通孔阵列上方并接触所述第一通孔阵列;
在所述第二再分布线上方形成第三聚合物层;
在所述第三聚合物层中形成第二开口阵列以露出所述第二再分布线;以及
镀第三再分布线,所述第三再分布线包括:
第二通孔阵列,位于所述第二开口阵列中,所述第二通孔阵列中的每个通孔均以一一对应的关系与所述第一通孔阵列中的一个通孔重叠;和
第三金属迹线,位于所述第二通孔阵列上方并接触所述第二通孔阵列。
14.根据权利要求13所述的方法,其中,镀所述第一再分布线包括:
在所述第一聚合物层上方形成晶种层;
在所述晶种层上方形成图案化掩模;
在所述图案化掩模的开口中以及在所述晶种层上方镀所述第一再分布线;
去除所述图案化掩模;以及
去除所述晶种层中被去除的所述图案化掩模所覆盖的部分。
15.根据权利要求13所述的方法,还包括:直接在所述第二通孔阵列上方堆叠第三通孔阵列。
16.根据权利要求13所述的方法,其中,在镀之后,所述第二再分布线的整个顶面平坦。
17.根据权利要求13所述的方法,包括:形成电耦合至所述第二通孔阵列的焊料区域。
18.根据权利要求17所述的方法,其中,所述焊料区域与所述第二通孔阵列不重合。
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