CN102640283A - 具有嵌入式管芯的半导体封装及其制造方法 - Google Patents

具有嵌入式管芯的半导体封装及其制造方法 Download PDF

Info

Publication number
CN102640283A
CN102640283A CN2010800546504A CN201080054650A CN102640283A CN 102640283 A CN102640283 A CN 102640283A CN 2010800546504 A CN2010800546504 A CN 2010800546504A CN 201080054650 A CN201080054650 A CN 201080054650A CN 102640283 A CN102640283 A CN 102640283A
Authority
CN
China
Prior art keywords
dielectric layer
tube core
encapsulation
welding
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010800546504A
Other languages
English (en)
Other versions
CN102640283B (zh
Inventor
J·S·居泽克
J·S·冈萨雷斯
N·R·沃茨
R·K·纳拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN102640283A publication Critical patent/CN102640283A/zh
Application granted granted Critical
Publication of CN102640283B publication Critical patent/CN102640283B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/27312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92132—Sequential connecting processes the first connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/40—Details of apparatuses used for either manufacturing connectors or connecting the semiconductor or solid-state body
    • H01L2924/401—LASER
    • H01L2924/402—Type
    • H01L2924/4025—Type being a gas
    • H01L2924/40252—CO2 LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/40—Details of apparatuses used for either manufacturing connectors or connecting the semiconductor or solid-state body
    • H01L2924/401—LASER
    • H01L2924/402—Type
    • H01L2924/404—Type being a solid state
    • H01L2924/40407—Yb:YAG LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/40—Details of apparatuses used for either manufacturing connectors or connecting the semiconductor or solid-state body
    • H01L2924/401—LASER
    • H01L2924/405—Wavelength
    • H01L2924/40501—UV spectrum
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明的实施例描述了具有嵌入式管芯的半导体封装。半导体封装包括包含嵌入的管芯的无芯基底。半导体封装提供了管芯堆叠或封装堆叠能力。此外，本发明的实施例描述了最小化组装成本的制造半导体封装的方法。

Description

具有嵌入式管芯的半导体封装及其制造方法
技术领域
本发明涉及半导体封装领域，并且更具体地涉及半导体封装中的嵌入式管芯及其制造方法。
背景技术
半导体封装用于保护集成电路（IC）芯片或管芯，并且也给管芯提供了与外部电路的电接口。随着对更小电子器件的不断增长的需求，半导体封装被设计得更加紧凑并且必须支持更大的布图密度。例如，现在某些半导体封装使用无芯基底，该无芯基底不包括通常在常规基底中发现的厚树脂芯层。此外，对更高性能的器件的需求导致改善半导体封装的需要，这使得能够在保持薄封装外形（profile）的同时，实现混合技术管芯堆叠或提供封装堆叠能力。
附图说明
图1是示出根据本发明的一个实施例的半导体封装的截面图；
图2是示出根据本发明的另一实施例的半导体封装的截面图；
图3是示出根据本发明的另一实施例的半导体封装的截面图；
图4是示出根据本发明的另一实施例的半导体封装的截面图；
图5是示出根据本发明的另一实施例的半导体封装的截面图；
图6A-6O是示出制造图1中所示的半导体封装的方法的截面图；
图7A-7E是示出制造图5中所示的半导体器件的方法的截面图；
图8是根据本发明的实施例的系统。
具体实施方式
描述了具有嵌入式管芯的半导体封装及其制造方法。在以下描述中，为了提供对本发明的全面理解，阐述了许多特定细节。在其它实例中，为了不必要地使本发明难以理解，未特别详细描述公知的半导体处理技术和特征。
本发明的实施例描述了具有嵌入式管芯的半导体封装。在一个实施例中，半导体封装包括包含嵌入式管芯的无芯基底。通过在无芯基底中嵌入管芯，消除了在常规倒装芯片组装中通常使用的组装步骤，从而减少了组装成本。此外，半导体封装能实现混合技术管芯堆叠或封装堆叠。因此，半导体封装提供了具有管芯堆叠或封装堆叠能力的薄外形封装在减少封装组装成本方面的优势。
图1示出了根据本发明的一个实施例的半导体封装201的截面图。半导体封装201包括具有管芯空腔213的第一电介质层210。在一个实施例中，管芯空腔213设置在中间，并且贯穿第一电介质层210。粘附层220形成在管芯空腔213中。在本发明的实施例中，粘附层220具有顶表面221，其基本上与第一电介质层210的顶表面221共面。
集成电路（IC）芯片或管芯300布置在管芯空腔213中。管芯300包括前侧310和后侧320。在一个实施例中，管芯300的后侧320固定或粘附于粘附层220的底表面222。在一个实施例中，前侧310包括多个管芯焊盘341、342。
第二电介质层250形成在第一电介质层210的底表面上。第二电介质层250也包封管芯300。在一个实施例中，多个管芯互连271、272形成在第二电介质层250中，其中管芯互连271、272与管芯300上的管芯焊盘341、342电耦合。
在本发明的实施例中，第三电介质层280形成在第二电介质层250上。在一个实施例中，多个管芯互连291、292形成在第三电介质层280中。在第三电介质层280中的管芯互连291、292与第二电介质层250中的管芯互连271、272电耦合。
在本发明的实施例中，多个封装焊盘231、232、233、234形成在第一电介质层210中。封装焊盘231、232、233、234形成在管芯300的外围区域。在一个实施例中，每个封装焊盘231、232、233、234都包括基本上与第一电介质层210的顶表面211共面的暴露的表面。此外，多个封装互连273、274、275、276形成在第二电介质层250中，并且与封装焊盘231、232、233、234电耦合。在一个实施例中，附加的封装互连293、294形成在第三电介质层280中，并且与第二电介质层250中的封装互连273、276电耦合。在一个实施例中，管芯互连291、292形成在第三电介质层中，其中管芯互连291、292与管芯互连271、272电耦合。
在一个实施例中，阻焊层400形成在第三电介质层280上。在一个实施例中，阻焊层400包括暴露管芯互连291、292和封装互连293、294的开口。焊球或焊料凸块411、412、413、414形成在管芯互连291、292和封装互连293、294上。焊料凸块411、412与管芯互连291、292电耦合。焊料凸块413、414与封装互连293、294电耦合。图1示出了在半导体封装201上形成焊料凸块411、412、413、414以产生球栅阵列（BGA）布图。BGA布图的布线或迹线能够形成在阻焊层400上。能够明白其它类型的布图，例如平面栅格阵列（LGA），能够形成在半导体封装201上。
在一个实施例中，具有管芯互连271、272、291、292和封装互连273-276、293、294的电介质层210、250、280构成无芯基底，其中管芯300整个地嵌入在无芯基底中。通过将管芯300嵌入在半导体封装201的无芯基底中，消除了在常规倒装芯片组装中所通常使用的组装步骤，从而减少了组装成本。另外，半导体封装201不再限于带状制造能力，其能实现全面板（fullpanel）处理，进一步减少了制造成本。此外，半导体封装201能实现混合技术管芯堆叠或封装堆叠。因此，半导体封装201提供了低外形封装、薄管芯组装、POP兼容性、混合技术（例如引线键合）管芯堆叠在减少封装组装成本方面的优势。
图2示出了在半导体封装201上的管芯堆叠的范例。在一个实施例中，另一管芯500附着在半导体封装201上。管芯500固定或粘附于粘附层220的顶表面221。多个引线键合互连511、512、513、514将管芯500与半导体封装201的封装焊盘231、232、233、234电耦合。能够将模制化合物层（未示出）用于保护顶部管芯并包封引线键合。在本发明的实施例中，能够将图2中所示的最终封装附着至印刷电路板（PCB），其中，封装焊盘231、232、233、234和封装互连273、274、275、276、293、294用作管芯500与PCB上的迹线之间的电连接。
在本发明的实施例中，具有附加管芯500的半导体封装201形成能够用在各种应用中的系统级封装（SIP），例如便携或手持设备，诸如膝上型电脑或移动电话。在特定实施例中，管芯300是包含处理器模块的片上系统（SOC），而管芯500是用于SOC的存储模块。
图3示出了在半导体封装201上的封装堆叠的范例。在本发明的实施例中，能够将另一封装600附着至半导体封装201，以形成封装上封装（POP）结构。在一个实施例中，封装600包括与封装基底620电耦合的管芯610。模制帽（mold cap）包封管芯610，并且用作管芯610的保护盖（cover）。在一个实施例中，多个互连，例如焊料凸块651、652、653、654能够用于将管芯610与半导体封装201的封装焊盘231、232、233、234电耦合。
在一个实施例中，图3中所示的POP结构是系统级封装。在特定实施例中，管芯300可以是包含处理器模块的SOC，而管芯610可以是用于SOC的附加逻辑芯片。在一个实施例中，封装600是倒装芯片封装。
在本发明的实施例中，能够结合管芯堆叠和封装堆叠技术来使用半导体封装201。在一个实施例中，如图4中所示，管芯500附着至粘附层220的顶表面221。引线键合互连512、513将管芯500与封装焊盘232、233电耦合。封装600堆叠在管芯500和半导体封装201上。焊料凸块651、654将封装600与封装焊盘231、234电耦合。
在替代实施例中，管芯300完全嵌入在没有封装焊盘231、232、233、234和封装互连273、274、275、276、293、294的半导体封装中。例如，图5示出了包括管芯互连271、272、291、292、295、296的替代的半导体封装201’。焊料凸块411、412、413、414形成在管芯互连291、292、295、296上。
图6A-6L示出了形成图1中所示的半导体封装201的方法。如图6A中所示，半导体封装201的制造从提供面板或载体100开始。在一个实施例中，载体100包括能在其上进行镀覆的导电表面110。在特定实施例中，载体100由诸如铜的导电金属制成，并且导电表面110是铜表面。在一个实施例中，载体100的厚度大约为50μm。
接下来，如图6B中所示，第一电介质层210形成在载体100的导电表面110上。在一个实施例中，第一电介质层210包括顶表面211和底表面212，其中顶表面211形成在导电表面110上。在一个实施例中，第一电介质层210的厚度与随后嵌入到第一电介质层210中的管芯的厚度大致相同。例如，第一电介质层的厚度大约为50-150μm。接下来，如图6C中所示，管芯空腔213和多个焊盘开口214、215、216、217形成在第一电介质层210中。在一个实施例中，管芯空腔213设置在中间，并且延伸穿过第一电介质层210，以暴露导电表面110上的管芯区域111。多个焊盘开口214、215、216、217暴露导电表面110上的多个焊盘区域112、113、114、115。
在本发明的实施例中，第一电介质层210由光可成像或光可限定材料制成。在一个实施例中，第一电介质层210由正性光可限定材料制成，其中通过对第一电介质层210进行显影来去除第一电介质层210暴露于辐射源的部分。在另一实施例中，第一电介质层210由负性光可限定材料制成，其中通过对第一电介质层210进行显影来保留第一电介质层210暴露于辐射源的部分。光可限定材料包括但不限于基于环氧树脂的光致抗蚀剂。在本发明的实施例中，（光可限定的）第一电介质层210的制造从在导电表面110上层压光可限定材料层开始（如图6B中所示）。接下来，光可限定材料暴露于辐射源并且随后被显影以限定管芯空腔211和多个焊盘开口212、213、214、215（如图6C中所示）。
在替代实施例中，第一电介质层210由非光可限定的普通电介质材料制成。在此情况下，通过在导电表面110上沉积第一电介质层210来制造第一电介质层210（如图6B中所示），接着在第一电介质层210中限定管芯空腔211和焊盘开口212、213、214、215（如图6C中所示）。在一个实施例中，通过普通光刻和蚀刻工艺来限定或产生管芯空腔211和焊盘开口212、213、214、215，诸如但不限于等离子体蚀刻工艺。在另一实施例中，通过使用半导体制造中通常使用的激光或机械钻孔工艺来限定管芯空腔211和焊盘开口212、213、214、215。
接下来，如图6D中所示，粘附层220形成在导电表面110的管芯区域111上。粘附层220包括顶表面221和底表面222。在一个实施例中，顶表面221形成在管芯区域111上，使得其基本上与第一电介质层210的顶表面211共面。在一个实施例中，粘附层220喷涂在管芯区域111上。在另一实施例中，通过使用公知的丝网印刷技术来形成粘附层220。例如，使用网格掩模（未示出）将粘附材料印刷在管芯区域111上，并且接下来固化粘附材料以形成覆盖整个管芯区域111的粘附层220。在一个实施例中，粘附层220仅选择性地形成在管芯区域111上。也就是说，粘附层220不形成在焊盘区域112、113、114、115上。
在一个实施例中，形成的粘附层220的厚度大约为10至50μm。粘附层220由诸如但不限于填充的基于环氧树脂的材料的材料制成。在本发明的实施例中，粘附层220保持作为半导体封装201的永久特征，用于保护随后嵌入到第一电介质层210中的管芯。此外，能够将粘附层220用作用于随后进行标记的表面或者用于最小化任何可能发生在管芯内的翘曲。
接下来，如图6E中所示，多个封装焊盘231、232、233、234形成在导电表面110的焊盘区域112、113、114、115上。在本发明的实施例中，通过使用公知的电解镀覆技术来形成多个封装焊盘231、232、233、234。在一个实施例中，焊盘区域112、113、114、115的电镀从在第一电介质层210上形成抗蚀剂层（未示出）开始，其中对抗蚀剂层进行构图以暴露焊盘区域112、113、114、115。接下来，使用诸如但不限于金（Au）、钯（Pd）、镍（Ni）和铜（Cu）的金属来电镀焊盘区域112、113、114、115。在本发明的特定实施例中，以下列顺序电镀焊盘区域112、113、114、115：金，接着是钯，接着是镍。在此情况下，多个封装焊盘231、232、233、234包括金、钯和镍的合成物或多层堆叠。在电镀工艺完成后，从第一电介质层210去除抗蚀剂层。
接下来，如图6F中所示，管芯300附着至粘附层220。管芯300包括前侧310和后侧320。在一个实施例中，管芯300的前侧310包括多个管芯焊盘341、342。在一个实施例中，能够使用公知的管芯设置技术来将管芯300插入至管芯空腔211中。随后将管芯300固定或粘附至粘附层220。在一个实施例中，管芯240的后侧320粘附至粘附层220。
图6D和6F描述了在将管芯300附着至粘附层220上之前，在载体100上形成粘附层220。在替代实施例中，在将带有粘附膜的管芯300设置到载体100上之前，先将粘附膜附着至管芯后侧320。例如，从图6C开始，将在其后侧320上带有粘附膜的管芯300设置在载体的管芯区域111上，使得粘附膜将管芯300固定在载体100上。在此情况下，粘附膜仅形成在管芯300的下方，且不延伸到管芯300的边缘之外。也就是说，粘附膜不覆盖整个管芯区域111。
粘附层220用作管芯后侧320的保护层。此外，能够将粘附层220用于最小化任何可能发生在管芯300内的翘曲。在一个实施例中，粘附层220包括UV-可固化的特性，随后能够将其激活以将引线键合管芯附着至粘附层220的顶表面221。在一个实施例中，粘附层220包括导热特性，这有利于管芯300的热耗散。
接下来，如图6G中所示，第二电介质层250形成在第一电介质层210和管芯300上。在本发明的实施例中，第二电介质层250由公知的层压技术来形成。第二电介质层250能够由诸如但不限于填充的基于环氧树脂的合成材料的材料制造。在一个实施例中，形成的第二电介质层250的厚度大约为10-30μm。
在一个实施例中，第二电介质层250包封了整个管芯300，包括管芯300的前侧310和侧壁。此外，第二电介质层250形成在多个封装焊盘231、232、233、234上。在一个实施例中，第二电介质层250形成有水平表面251，以有利于随后的内建（build-up）工艺。
接下来，多个互连形成在管芯焊盘341、342和封装焊盘231、232、233、234上。在本发明的实施例中，使用半加成工艺（SAP）来形成所述多个互连。例如，在图6H中，多个互连的制造从在第二电介质层250中形成通路孔261、262、263、264、265、266开始。在一个实施例中，通路孔261、262暴露管芯300的前侧310上的管芯焊盘341、342，而通路孔263、264、265、266则暴露封装焊盘231、232、233、234。
在一个实施例中，通过机械或激光钻孔工艺来形成通路孔261、262、263、264、265、266。在一个实施例中，由于不同的直径和深度，在单独的钻孔工艺中限定通路孔261、262和通路孔263、264、265、266。例如，通过使用UVYAG激光源来形成通路孔261、262。形成的通路孔261、262的直径尺寸小于50μm。然后，用CO2激光源来形成通路孔263、264、265、266。形成的通路孔263、264、265、266的直径尺寸大约为50-150μm。在本发明的实施例中，通过使用在基底制造中通常使用的、基于高锰酸盐化学反应（chemistry）的表面沾污去除工艺能够清洁通路孔261、262、263、264、265、266的表面。
在形成通路孔261、262、263、264、265、266之后，金属层（未示出）沉积在通路孔261、262、263、264、265、266中，并且沉积在管芯焊盘341、342和封装焊盘231、232、233、234上。在特定实施例中，金属层从由无电镀覆沉积的铜晶种层开始。随后，使用公知的光刻、电解铜镀覆、脱胶以及蚀刻技术来对金属层进行构图，以形成图6I中所示的单独的互连271、272、273、274、275、276。在一个实施例中，管芯互连271、272形成在管芯焊盘341、342上，而封装互连273、274、275、276则形成在封装焊盘231、232、233、234上。可以在单独的工艺中形成管芯互连271、272和封装互连273、274、275、276。
通过使用SAP内建工艺，能够增加半导体封装中内建层的数量。例如，重复形成电介质层接着形成互连的步骤，从而产生更多的金属化层。例如，在图6J中，第三电介质层280形成在第二电介质层250和互连271、272、273、274、275、276上。然后，多个互连291、292、293、294形成在第三电介质层280中。在一个实施例中，管芯互连291、292形成在管芯互连271、272上，使得互连291、292与管芯互连271、272电耦合。封装互连293、294形成在互连273、276上，其中封装互连293、294与互连273、276电耦合。
为了例示的目的，图6J仅示出了两层内建层（即电介质层250、280）。能够明白的是能够根据封装设计增加电介质层或内建层的数量。在通常的设计中，大约3-6层内建层构成半导体封装。
在本发明的实施例中，如图6K中所示，阻焊层400形成在最上方的电介质层（即第三电介质层280）上。在一个实施例中，阻焊层400形成有暴露管芯互连291、292和封装互连293、294的开口。在一个实施例中，能够在第三电介质层280上丝网印刷或层压阻焊层400。然后，能够在阻焊层400上执行激光处理来限定暴露管芯互连291、292和封装互连293、294的开口。在另一实施例中，阻焊层400由能够暴露于辐射源并显影以形成开口的光可限定聚合物材料制成。
接下来，如图6L中所示，从半导体封装201去除载体100，以暴露封装焊盘231、232、233、234和粘附层220。在一个实施例中，通过使用公知的蚀刻工艺来去除载体100。在一个实施例中，蚀刻使用基本上对第一电介质层210、粘附层220和封装焊盘231、232、233、234是选择性的蚀刻化学反应。也就是说，蚀刻化学反应去除载体100比它去除第一电介质层210、粘附层220或封装焊盘231、232、233、234要快。
然后，焊球或焊料凸块411、412形成在暴露的互连292、293上。焊料凸块411、412由公知的焊接材料制成并且通过公知的技术（诸如但不限于蒸发、电镀或直接设置）形成。这完成了图1中所示的半导体器件的制造。图6A-6K示出了在载体100的一侧上的半导体封装201的制造。能够理解的是，能够使用载体100的两侧来同时形成两个半导体封装。在另一实施例中，可以先将管芯300附着至载体100（图6M）。例如，通过层压工艺，可以在管芯上形成层211（图6N）。例如，可以使用单层211来替代图6I的两层210和250来根据本文中先前描述的方法形成图6O中的结构。
图7A-7E示出了形成图5中所示的半导体封装201’的方法。除了半导体封装201’中未形成封装互连以外，半导体封装201’的制造类似于图6A-6L中所描述的工艺。从图6B继续，如图7A中所示，仅在第一电介质层210中形成管芯空腔213。接下来，如图7B中所示，粘附层220和管芯300附着在载体100的管芯区域111上。形成粘附层220和附着管芯300的方法类似于图6D和6F，因此这里不再赘述。
接下来，在图7C中，第二电介质层250形成在第一电介质层210和管芯300上，接着在管芯焊盘341、342上形成管芯互连271、272。形成第二电介质层250和管芯互连271、272的方法类似于图6G、6H和6I中所描述的工艺。在一个实施例中，在管芯互连271、272的制造期间，形成金属线277、278。然后，如图7D中所示，第三电介质层280形成在第二电介质层290上。管芯互连291、292、295、296形成在第三电介质层280上。在此情况下，附加的管芯互连295、296形成在金属线277、278上。阻焊层400形成在第三电介质层280上并且暴露管芯互连291、292、295、296。
接下来，在图7E中，使用与图6K中所描述的类似的方法，从半导体封装201去除载体100。然后，在管芯互连291、292、295、296上形成焊料凸块411、412、413、414。这完成了如图5中所示的半导体封装201’的制造。在另一实施例中，可以先将管芯300附着至载体100，并且通过层压处理，例如以类似于图6M-6O中所示出的方式，可以在管芯300上形成可以代替层210和250的单层（类似于图6N中的层211）。
图8示出了根据本发明的实施例的计算机系统。在某些实施例中，系统800包括处理器810、存储器件820、存储器控制器830、图形控制器840、输入和输出（I/O）控制器850、显示器852、键盘854、定位设备856以及外围设备858，所有的这些可以通过总线860互相通信地耦合。处理器810可以是通用处理器或专用集成电路（ASIC）。I/O控制器850可以包括用于有线或无线通信的通信模块。存储器件820可以是动态随机存取存储（DRAM）器件、静态随机存取存储（SRAM）器件、闪存器件或者这些存储器件的组合。因此，在某些实施例中，系统800中的存储器件820不是必须包括DRAM器件。
系统800中所示的一个或多个部件可以包括在一个或多个集成电路封装中，并且或者可以包括一个或多个集成电路封装，诸如（例如）图7E的封装结构。例如，处理器810或存储器件820或至少部分I/O控制器850或这些部件的组合可以包括在包括各个实施例中所描述的结构的至少一个实施例的集成电路封装中。
这些元件执行本领域公知的它们的常规的功能。特别地，在某些情况下，可以使用存储器件820来提供对根据本发明的实施例形成封装结构的方法的可执行指令的长期存储，并且在其它实施例中，存储器件820可以用于短期存储在处理器810执行期间根据本发明的实施例形成封装结构的方法的可执行指令。此外，可以存储指令，否则，所述指令可以与与系统通信地耦合的机器可存取介质相关联，例如，与系统通信地耦合的机器可存取介质诸如光盘只读存储器（CD-ROM）、数字多功能盘（DVD）和软盘、载波和/或其它传播信号。在一个实施例中，存储器件820可以给处理器810提供用于执行的可执行指令。
系统800可以包括计算机（例如，台式电脑、膝上型电脑、手持电脑、服务器、网络设备、路由器等）、无线通信设备（例如，蜂窝电话、无绳电话、寻呼机、个人数字助理等）、计算机相关外围设备（例如，打印机，扫描仪、监视器等）、娱乐设备（例如，电视、收音机、立体声、磁带及光盘播放器、盒式录像机、摄像放像机、数码相机、MP3（动态影像专家组，音频层3）播放器、视频游戏、手表等），等等。
已经描述了本发明的数个实施例。然而，本领域技术人员会认识到本发明不限于所描述的实施例，而能够在以下所附的权利要求的精神和范围内以修改和变化实施本发明。

Claims (21)

1.一种形成半导体封装的方法，包括：
提供具有导电表面的载体；
在所述载体的所述导电表面上形成第一电介质层，所述第一电介质层具有暴露所述导电表面上的管芯区域的管芯空腔；
在所述导电表面的所述管芯区域上形成粘附层；
将管芯附着到所述粘附层上，所述管芯具有固定至所述粘附层的后侧和具有多个管芯焊盘的前侧；
在所述第一电介质层和所述管芯上沉积第二电介质层；
在所述管芯的所述前侧上的所述多个管芯焊盘上形成多个管芯互连；以及
去除所述载体以暴露所述粘附层。
2.根据权利要求1所述的方法，其中，形成所述第一电介质层还包括：
在所述第一电介质层中形成多个焊盘开口，所述多个焊盘开口暴露所述导电表面上的多个焊盘区域；
在所述导电表面的所述多个焊盘区域上形成多个封装焊盘；以及
在所述多个封装焊盘上形成多个封装互连。
3.根据权利要求2所述的方法，其中，所述第一电介质层是光可限定电介质材料。
4.根据权利要求3所述的方法，其中，通过以下步骤形成所述第一电介质层：
在所述导电表面上层压所述光可限定电介质材料；以及
将所述第一电介质层曝光于辐射源，并且对所述第一电介质层进行显影，以在所述第一电介质层中限定所述管芯空腔和所述多个焊盘开口。
5.根据权利要求2所述的方法，其中，形成所述第一电介质层包括：
在所述导电表面上沉积所述第一电介质层；以及
在所述第一电介质层中限定所述管芯空腔和所述多个焊盘开口。
6.根据权利要求5所述的方法，其中，通过蚀刻工艺来限定所述管芯空腔和所述多个焊盘开口。
7.根据权利要求5所述的方法，其中，通过激光或机械钻孔工艺来限定所述管芯空腔和所述多个焊盘开口。
8.根据权利要求2所述的方法，其中，通过电解镀覆所述多个焊盘区域来形成所述多个封装焊盘。
9.根据权利要求1所述的方法，其中，在所述管芯区域上喷涂或丝网印刷所述粘附层。
10.根据权利要求1所述的方法，其中，形成所述多个管芯互连包括：
在所述第二电介质层中形成多个第一通路孔，所述多个第一通路孔暴露所述管芯的所述前侧的所述多个管芯焊盘；
在所述多个第一通路孔中和所述多个管芯焊盘上形成金属层；以及
蚀刻所述金属层以形成所述多个管芯互连。
11.根据权利要求2所述的方法，其中，形成所述多个封装互连包括：
在所述电介质层中形成多个第二通路孔，所述多个第二通路孔暴露所述多个封装焊盘；
在所述多个第二通路孔中和所述多个封装焊盘上形成金属层；以及
蚀刻所述金属层以形成所述多个封装互连。
12.根据权利要求2所述的方法，还包括：
在所述第二电介质层上沉积第三电介质层；以及
在所述多个管芯互连或所述多个封装互连上形成多个互连。
13.根据权利要求2所述的方法，还包括：
在所述第二电介质层上形成阻焊层；以及
形成多个焊料凸块，其中所述多个焊料凸块与所述多个管芯互连或者所述多个封装互连电耦合。
14.一种半导体封装，包括：
第一封装，包括：
第一电介质层，具有上表面和延伸穿过所述第一电介质层的空腔；
形成在所述第一电介质层的所述空腔中的粘附层，所述粘附层具有上表面和下表面，其中所述上表面基本上与所述第一电介质层的顶表面共面；
形成在所述空腔中的第一管芯，所述第一管芯具有前侧和后侧，其中所述前侧包括多个管芯焊盘，并且其中所述后侧粘附于所述粘附层的所述下表面；
形成在所述第一电介质层的底表面和所述第一管芯的所述前侧上的第二电介质层；以及
电耦合到所述第一管芯的所述前侧上的所述多个管芯焊盘的多个管芯互连。
15.根据权利要求14所述的半导体封装，还包括：
形成在所述第一电介质层中的多个封装焊盘，其中所述多个封装焊盘中的每个封装焊盘都包括基本上与所述第一电介质层的所述顶表面共面的暴露的表面；以及
电耦合到所述多个封装焊盘的多个封装互连。
16.根据权利要求15所述的半导体封装，还包括：
粘附至所述第一封装中的所述粘附层的所述上表面的第二管芯；以及
将所述第二管芯电耦合到所述第一封装的所述多个封装焊盘的多个引线键合互连。
17.根据权利要求15所述的半导体封装，还包括：
第二封装，包括：
第三管芯；以及
将所述第三管芯电耦合到所述第一封装中的所述多个封装焊盘的多个互连。
18.根据权利要求15所述的半导体封装，其中，所述多个封装焊盘包括金、钯和镍的合成物。
19.根据权利要求14所述的半导体器件，还包括：
电耦合到所述多个管芯互连的多个第一焊料凸块。
20.根据权利要求15所述的半导体器件，还包括：
电耦合到所述多个封装互连的多个第二焊料凸块。
21.根据权利要求14所述的半导体器件，还包括系统，所述系统包括：
通信地耦合到所述结构的总线；以及
通信地耦合到所述总线的DRAM。
CN201080054650.4A 2009-12-29 2010-12-07 具有嵌入式管芯的半导体封装及其制造方法 Active CN102640283B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/655,335 2009-12-29
US12/655,335 US8901724B2 (en) 2009-12-29 2009-12-29 Semiconductor package with embedded die and its methods of fabrication
PCT/US2010/059237 WO2011090570A2 (en) 2009-12-29 2010-12-07 Semiconductor package with embedded die and its methods of fabrication

Publications (2)

Publication Number Publication Date
CN102640283A true CN102640283A (zh) 2012-08-15
CN102640283B CN102640283B (zh) 2015-10-07

Family

ID=44307449

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080054650.4A Active CN102640283B (zh) 2009-12-29 2010-12-07 具有嵌入式管芯的半导体封装及其制造方法

Country Status (5)

Country Link
US (2) US8901724B2 (zh)
KR (1) KR101478515B1 (zh)
CN (1) CN102640283B (zh)
TW (1) TWI539574B (zh)
WO (1) WO2011090570A2 (zh)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103366798A (zh) * 2013-07-10 2013-10-23 格科微电子（上海）有限公司 动态随机存取存储器及制造方法、半导体封装件及封装方法
WO2014114003A1 (en) * 2013-01-28 2014-07-31 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including embedded controller die and method of making same
CN104040713A (zh) * 2012-09-29 2014-09-10 英特尔公司 用于层叠封装架构的嵌入式结构
CN104051379A (zh) * 2013-03-13 2014-09-17 英特尔公司 具有超薄介电层的无焊内建层（bbul）半导体封装
CN104221146A (zh) * 2012-09-29 2014-12-17 英特尔公司 在无芯衬底中具有嵌入式rf管芯的系统级封装
CN104900626A (zh) * 2014-03-05 2015-09-09 英特尔公司 管芯到管芯接合以及相关联的封装构造
CN106033753A (zh) * 2015-03-12 2016-10-19 恒劲科技股份有限公司 封装模块及其基板结构
CN106068558A (zh) * 2014-03-04 2016-11-02 高通股份有限公司 包括高密度互连和重分布层的集成器件
CN106409810A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
TWI584410B (zh) * 2014-12-11 2017-05-21 聯發科技股份有限公司 晶片封裝結構及其製造方法
CN106960799A (zh) * 2016-01-12 2017-07-18 飞思卡尔半导体公司 制造三维扇出结构的方法
CN107078101A (zh) * 2014-11-07 2017-08-18 高通股份有限公司 在封装层中包括硅桥接的集成器件封装
CN107768320A (zh) * 2016-08-18 2018-03-06 恒劲科技股份有限公司 电子封装件及其制法
TWI628772B (zh) * 2013-12-16 2018-07-01 新加坡商星科金朋有限公司 具有嵌設元件的積體電路封裝系統及製造該積體電路封裝系統的方法
CN110299329A (zh) * 2018-03-21 2019-10-01 华为技术有限公司 一种封装结构及其制作方法、电子设备
CN111199938A (zh) * 2018-11-16 2020-05-26 赛灵思公司 高密度基板和具有高密度基板的堆叠式硅封装组件

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9049807B2 (en) * 2008-06-24 2015-06-02 Intel Corporation Processes of making pad-less interconnect for electrical coreless substrate
KR20100095268A (ko) * 2009-02-20 2010-08-30 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US8264849B2 (en) * 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8216918B2 (en) * 2010-07-23 2012-07-10 Freescale Semiconductor, Inc. Method of forming a packaged semiconductor device
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8127979B1 (en) 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
KR101632249B1 (ko) 2011-10-31 2016-07-01 인텔 코포레이션 멀티 다이 패키지 구조들
CN103107099B (zh) * 2011-11-14 2015-10-14 联合科技(股份有限)公司 半导体封装以及封装半导体器件的方法
US9613917B2 (en) * 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
CN104321864B (zh) 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
TWI467714B (zh) * 2012-06-18 2015-01-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9721878B2 (en) * 2012-09-28 2017-08-01 Intel Corporation High density second level interconnection for bumpless build up layer (BBUL) packaging technology
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
KR102107038B1 (ko) * 2012-12-11 2020-05-07 삼성전기주식회사 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법
US9064880B2 (en) 2012-12-28 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Zero stand-off bonding system and method
US9953907B2 (en) 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
KR101462770B1 (ko) 2013-04-09 2014-11-20 삼성전기주식회사 인쇄회로기판과 그의 제조방법 및 그 인쇄회로기판을 포함하는 반도체 패키지
US9685414B2 (en) 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations
CN104299919B (zh) * 2013-07-15 2017-05-24 碁鼎科技秦皇岛有限公司 无芯层封装结构及其制造方法
KR102192356B1 (ko) 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
KR101491606B1 (ko) * 2013-10-14 2015-02-11 대덕전자 주식회사 회로배선판 제조방법
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
US9379041B2 (en) * 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
US9824989B2 (en) 2014-01-17 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package and methods of forming thereof
US11523520B2 (en) * 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US9673171B1 (en) * 2014-03-26 2017-06-06 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
JP2015211194A (ja) 2014-04-30 2015-11-24 イビデン株式会社 プリント配線板および半導体パッケージ、ならびにプリント配線板の製造方法
KR102281458B1 (ko) * 2014-06-23 2021-07-27 삼성전기주식회사 소자 내장형 인쇄회로기판, 반도체 패키지 및 그 제조방법
US9502270B2 (en) * 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
JP6249578B2 (ja) * 2014-07-28 2017-12-20 インテル・コーポレーション 密なパッケージ配線を有するマルチチップモジュールの半導体チップパッケージ
US20160064340A1 (en) * 2014-08-28 2016-03-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9496154B2 (en) * 2014-09-16 2016-11-15 Invensas Corporation Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
US9177957B1 (en) * 2014-10-16 2015-11-03 Delta Electronics, Inc. Embedded packaging device
TWI559829B (zh) 2014-10-22 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
TWI552282B (zh) * 2014-11-03 2016-10-01 矽品精密工業股份有限公司 封裝結構及其製法
US9570322B2 (en) * 2014-11-26 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
KR102333084B1 (ko) * 2014-12-10 2021-12-01 삼성전기주식회사 임베디드 인쇄회로기판 및 그 제조 방법
US10306777B2 (en) * 2014-12-15 2019-05-28 Bridge Semiconductor Corporation Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same
US9576900B2 (en) * 2015-02-11 2017-02-21 Endura Technologies LLC Switched power stage with integrated passive components
US9691694B2 (en) * 2015-02-18 2017-06-27 Qualcomm Incorporated Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate
US10199337B2 (en) 2015-05-11 2019-02-05 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US9984979B2 (en) 2015-05-11 2018-05-29 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package and method of manufacturing the same
KR20160132751A (ko) * 2015-05-11 2016-11-21 삼성전기주식회사 전자부품 패키지 및 그 제조방법
US9741586B2 (en) 2015-06-30 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structures
US9935047B2 (en) 2015-10-16 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods forming the same
US10756072B2 (en) 2015-12-25 2020-08-25 Intel Corporation Conductive wire through-mold connection apparatus and method
KR102360319B1 (ko) * 2016-03-12 2022-02-08 닝보 써니 오포테크 코., 엘티디. 카메라 모듈, 그 감광성 부품 및 그 제조 방법
US9842818B2 (en) * 2016-03-28 2017-12-12 Intel Corporation Variable ball height on ball grid array packages by solder paste transfer
US9832865B2 (en) * 2016-04-26 2017-11-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods and devices for providing increased routing flexibility in multi-layer printed circuit boards
DE112016006809B4 (de) * 2016-04-28 2024-08-29 Intel Corporation Integrierte schaltungsstrukturen mit erweiterten leitungswegen und verfahren zur herstellung einer integrierten-schaltungs-anordnung
US10224299B2 (en) 2016-12-29 2019-03-05 Intel Corporation Sintered solder for fine pitch first-level interconnect (FLI) applications
US10644046B2 (en) * 2017-04-07 2020-05-05 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
US10410940B2 (en) * 2017-06-30 2019-09-10 Intel Corporation Semiconductor package with cavity
US10515921B2 (en) * 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
US20190103357A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Methods of forming package on package assemblies with reduced z height and structures formed thereby
US20190122897A1 (en) * 2017-10-24 2019-04-25 Global Circuit Innovations Inc. Low Profile Electronic System Method and Apparatus
KR101901712B1 (ko) 2017-10-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101912290B1 (ko) * 2017-12-06 2018-10-29 삼성전기 주식회사 팬-아웃 반도체 패키지
CN110769598B (zh) * 2018-07-27 2021-11-16 宏启胜精密电子(秦皇岛)有限公司 内埋式电路板及其制作方法
US20220157865A1 (en) * 2019-03-13 2022-05-19 Sony Semiconductor Solutions Corporation Semiconductor apparatus, imaging apparatus, and method of producing a semiconductor apparatus
US11145624B2 (en) * 2019-07-26 2021-10-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11069537B2 (en) 2019-10-18 2021-07-20 Hamilton Sundstrand Corporation Method for delidding a hermetically sealed circuit package
KR102573573B1 (ko) 2019-10-25 2023-09-01 삼성전자주식회사 반도체 패키지
KR20210073802A (ko) * 2019-12-11 2021-06-21 삼성전기주식회사 전자부품 내장기판
US11310911B2 (en) * 2020-07-14 2022-04-19 Qualcomm Incorporated Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
US6872589B2 (en) * 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same
US20050161833A1 (en) * 2004-01-20 2005-07-28 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20080116569A1 (en) * 2006-11-16 2008-05-22 Cheng-Hung Huang Embedded chip package with improved heat dissipation performance and method of making the same

Family Cites Families (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691628A (en) * 1969-10-31 1972-09-19 Gen Electric Method of fabricating composite integrated circuits
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6326696B1 (en) * 1998-02-04 2001-12-04 International Business Machines Corporation Electronic package with interconnected chips
TWI255853B (en) 1998-08-21 2006-06-01 Kirin Brewery Method for modifying chromosomes
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
EP1259103B1 (en) * 2000-02-25 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board and method for producing multilayer printed wiring board
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
JP3945483B2 (ja) * 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
US7786591B2 (en) * 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
TWI301660B (en) * 2004-11-26 2008-10-01 Phoenix Prec Technology Corp Structure of embedding chip in substrate and method for fabricating the same
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
TWI269423B (en) * 2005-02-02 2006-12-21 Phoenix Prec Technology Corp Substrate assembly with direct electrical connection as a semiconductor package
TWI264094B (en) 2005-02-22 2006-10-11 Phoenix Prec Technology Corp Package structure with chip embedded in substrate
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
JP2007305955A (ja) * 2006-04-10 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
TWI308382B (en) 2006-07-25 2009-04-01 Phoenix Prec Technology Corp Package structure having a chip embedded therein and method fabricating the same
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
US7619901B2 (en) 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
TW200952142A (en) 2008-06-13 2009-12-16 Phoenix Prec Technology Corp Package substrate having embedded semiconductor chip and fabrication method thereof
US20100101491A1 (en) * 2008-10-29 2010-04-29 Asm Japan K.K. Wafer lift pins suspended and supported at underside of susceptor
US20110108999A1 (en) 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8264849B2 (en) 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
US20110316140A1 (en) 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US20120112336A1 (en) 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US8841171B2 (en) * 2010-11-22 2014-09-23 Bridge Semiconductor Corporation Method of making stackable semiconductor assembly with bump/flange heat spreader and dual build-up circuitry
US20120139095A1 (en) 2010-12-03 2012-06-07 Manusharow Mathew J Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
US8508037B2 (en) 2010-12-07 2013-08-13 Intel Corporation Bumpless build-up layer and laminated core hybrid structures and methods of assembling same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
US6872589B2 (en) * 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same
US20050161833A1 (en) * 2004-01-20 2005-07-28 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20080116569A1 (en) * 2006-11-16 2008-05-22 Cheng-Hung Huang Embedded chip package with improved heat dissipation performance and method of making the same

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104040713A (zh) * 2012-09-29 2014-09-10 英特尔公司 用于层叠封装架构的嵌入式结构
CN104221146A (zh) * 2012-09-29 2014-12-17 英特尔公司 在无芯衬底中具有嵌入式rf管芯的系统级封装
US9748177B2 (en) 2012-09-29 2017-08-29 Intel Corporation Embedded structures for package-on-package architecture
CN104769712B (zh) * 2013-01-28 2018-07-13 晟碟信息科技（上海）有限公司 包括嵌入式控制器裸芯的半导体器件和其制造方法
WO2014114003A1 (en) * 2013-01-28 2014-07-31 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including embedded controller die and method of making same
CN104769712A (zh) * 2013-01-28 2015-07-08 晟碟信息科技（上海）有限公司 包括嵌入式控制器裸芯的半导体器件和其制造方法
US9236368B2 (en) 2013-01-28 2016-01-12 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including embedded controller die and method of making same
CN104051379A (zh) * 2013-03-13 2014-09-17 英特尔公司 具有超薄介电层的无焊内建层（bbul）半导体封装
CN104051379B (zh) * 2013-03-13 2017-09-22 英特尔公司 具有超薄介电层的无焊内建层（bbul）半导体封装
US9287268B2 (en) 2013-07-10 2016-03-15 Galaxycore Shanghai Limited Corporation Dynamic random access memory (DRAM) and production method, semiconductor packaging component and packaging method
CN103366798A (zh) * 2013-07-10 2013-10-23 格科微电子（上海）有限公司 动态随机存取存储器及制造方法、半导体封装件及封装方法
CN103366798B (zh) * 2013-07-10 2016-02-17 格科微电子（上海）有限公司 动态随机存取存储器及制造方法、半导体封装件及封装方法
TWI628772B (zh) * 2013-12-16 2018-07-01 新加坡商星科金朋有限公司 具有嵌設元件的積體電路封裝系統及製造該積體電路封裝系統的方法
CN106068558A (zh) * 2014-03-04 2016-11-02 高通股份有限公司 包括高密度互连和重分布层的集成器件
CN104900626A (zh) * 2014-03-05 2015-09-09 英特尔公司 管芯到管芯接合以及相关联的封装构造
CN107078101A (zh) * 2014-11-07 2017-08-18 高通股份有限公司 在封装层中包括硅桥接的集成器件封装
TWI584410B (zh) * 2014-12-11 2017-05-21 聯發科技股份有限公司 晶片封裝結構及其製造方法
US10354974B2 (en) 2014-12-11 2019-07-16 Mediatek Inc. Structure and formation method of chip package structure
CN106033753B (zh) * 2015-03-12 2019-07-12 恒劲科技股份有限公司 封装模块及其基板结构
CN106033753A (zh) * 2015-03-12 2016-10-19 恒劲科技股份有限公司 封装模块及其基板结构
CN106409810B (zh) * 2015-07-31 2019-03-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
CN106409810A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
CN106960799A (zh) * 2016-01-12 2017-07-18 飞思卡尔半导体公司 制造三维扇出结构的方法
CN106960799B (zh) * 2016-01-12 2022-11-22 恩智浦美国有限公司 集成电路装置及其三维扇出结构和制造方法
CN107768320A (zh) * 2016-08-18 2018-03-06 恒劲科技股份有限公司 电子封装件及其制法
CN110299329A (zh) * 2018-03-21 2019-10-01 华为技术有限公司 一种封装结构及其制作方法、电子设备
CN111199938A (zh) * 2018-11-16 2020-05-26 赛灵思公司 高密度基板和具有高密度基板的堆叠式硅封装组件

Also Published As

Publication number Publication date
WO2011090570A2 (en) 2011-07-28
US20110215464A1 (en) 2011-09-08
US20150050781A1 (en) 2015-02-19
US8901724B2 (en) 2014-12-02
TW201131735A (en) 2011-09-16
CN102640283B (zh) 2015-10-07
KR20120098844A (ko) 2012-09-05
TWI539574B (zh) 2016-06-21
KR101478515B1 (ko) 2015-01-02
US9780054B2 (en) 2017-10-03
WO2011090570A3 (en) 2011-10-13

Similar Documents

Publication Publication Date Title
CN102640283B (zh) 具有嵌入式管芯的半导体封装及其制造方法
CN102656686B (zh) 凹陷型嵌入式管芯无核封装
US7591067B2 (en) Thermally enhanced coreless thin substrate with embedded chip and method for manufacturing the same
US7436074B2 (en) Chip package without core and stacked chip package structure thereof
CN103270586A (zh) 具有含多个垂直嵌入管芯的衬底的多芯片封装以及形成所述封装的工艺
US20090134528A1 (en) Semiconductor package, electronic device including the semiconductor package, and method of manufacturing the semiconductor package
US7208824B2 (en) Land grid array module
US7748111B2 (en) Manufacturing process of a carrier
US7550316B2 (en) Board on chip package and manufacturing method thereof
TW201041105A (en) Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
JP2002057241A (ja) 移植性導電パターンを含む半導体パッケージ及びその製造方法
TW201232751A (en) Substrate with embedded stacked through-silicon via die
TW202127597A (zh) 封裝結構及其製造方法
US7101733B2 (en) Leadframe with a chip pad for two-sided stacking and method for manufacturing the same
TWI781735B (zh) 半導體封裝及其製造方法
US20070290344A1 (en) Printed circuit board for package of electronic components and manufacturing method thereof
US8187922B2 (en) Low cost flexible substrate
US7652382B2 (en) Micro chip-scale-package system
US20070020816A1 (en) Manufacturing process for chip package without core
KR100743653B1 (ko) 적층 반도체 패키지 및 그 제조 방법
US20080245551A1 (en) Circuit board structure for embedding semiconductor chip therein and method for fabricating the same
US20090288861A1 (en) Circuit board with buried conductive trace formed thereon and method for manufacturing the same
US20240030121A1 (en) Package structure and manufacturing method thereof
TWI853713B (zh) 半導體封裝及其製造方法
CN111106123A (zh) 一种三维堆叠存储芯片结构及其封装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant