CN102640283B - 具有嵌入式管芯的半导体封装及其制造方法 - Google Patents

具有嵌入式管芯的半导体封装及其制造方法 Download PDF

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Publication number
CN102640283B
CN102640283B CN201080054650.4A CN201080054650A CN102640283B CN 102640283 B CN102640283 B CN 102640283B CN 201080054650 A CN201080054650 A CN 201080054650A CN 102640283 B CN102640283 B CN 102640283B
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dielectric layer
tube core
encapsulation
semiconductor packages
welding
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CN102640283A (zh
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J·S·居泽克
J·S·冈萨雷斯
N·R·沃茨
R·K·纳拉
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Intel Corp
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Intel Corp
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Abstract

本发明的实施例描述了具有嵌入式管芯的半导体封装。半导体封装包括包含嵌入的管芯的无芯基底。半导体封装提供了管芯堆叠或封装堆叠能力。此外，本发明的实施例描述了最小化组装成本的制造半导体封装的方法。

Description

具有嵌入式管芯的半导体封装及其制造方法
技术领域
本发明涉及半导体封装领域，并且更具体地涉及半导体封装中的嵌入式管芯及其制造方法。
背景技术
半导体封装用于保护集成电路（IC）芯片或管芯，并且也给管芯提供了与外部电路的电接口。随着对更小电子器件的不断增长的需求，半导体封装被设计得更加紧凑并且必须支持更大的布图密度。例如，现在某些半导体封装使用无芯基底，该无芯基底不包括通常在常规基底中发现的厚树脂芯层。此外，对更高性能的器件的需求导致改善半导体封装的需要，这使得能够在保持薄封装外形（profile）的同时，实现混合技术管芯堆叠或提供封装堆叠能力。
附图说明
图1是示出根据本发明的一个实施例的半导体封装的截面图；
图2是示出根据本发明的另一实施例的半导体封装的截面图；
图3是示出根据本发明的另一实施例的半导体封装的截面图；
图4是示出根据本发明的另一实施例的半导体封装的截面图；
图5是示出根据本发明的另一实施例的半导体封装的截面图；
图6A-6O是示出制造图1中所示的半导体封装的方法的截面图；
图7A-7E是示出制造图5中所示的半导体器件的方法的截面图；
图8是根据本发明的实施例的系统。
具体实施方式
描述了具有嵌入式管芯的半导体封装及其制造方法。在以下描述中，为了提供对本发明的全面理解，阐述了许多特定细节。在其它实例中，为了不必要地使本发明难以理解，未特别详细描述公知的半导体处理技术和特征。
本发明的实施例描述了具有嵌入式管芯的半导体封装。在一个实施例中，半导体封装包括包含嵌入式管芯的无芯基底。通过在无芯基底中嵌入管芯，消除了在常规倒装芯片组装中通常使用的组装步骤，从而减少了组装成本。此外，半导体封装能实现混合技术管芯堆叠或封装堆叠。因此，半导体封装提供了具有管芯堆叠或封装堆叠能力的薄外形封装在减少封装组装成本方面的优势。
图1示出了根据本发明的一个实施例的半导体封装201的截面图。半导体封装201包括具有管芯空腔213的第一电介质层210。在一个实施例中，管芯空腔213设置在中间，并且贯穿第一电介质层210。粘附层220形成在管芯空腔213中。在本发明的实施例中，粘附层220具有顶表面221，其基本上与第一电介质层210的顶表面221共面。
集成电路（IC）芯片或管芯300布置在管芯空腔213中。管芯300包括前侧310和后侧320。在一个实施例中，管芯300的后侧320固定或粘附于粘附层220的底表面222。在一个实施例中，前侧310包括多个管芯焊盘341、342。
第二电介质层250形成在第一电介质层210的底表面上。第二电介质层250也包封管芯300。在一个实施例中，多个管芯互连271、272形成在第二电介质层250中，其中管芯互连271、272与管芯300上的管芯焊盘341、342电耦合。
在本发明的实施例中，第三电介质层280形成在第二电介质层250上。在一个实施例中，多个管芯互连291、292形成在第三电介质层280中。在第三电介质层280中的管芯互连291、292与第二电介质层250中的管芯互连271、272电耦合。
在本发明的实施例中，多个封装焊盘231、232、233、234形成在第一电介质层210中。封装焊盘231、232、233、234形成在管芯300的外围区域。在一个实施例中，每个封装焊盘231、232、233、234都包括基本上与第一电介质层210的顶表面211共面的暴露的表面。此外，多个封装互连273、274、275、276形成在第二电介质层250中，并且与封装焊盘231、232、233、234电耦合。在一个实施例中，附加的封装互连293、294形成在第三电介质层280中，并且与第二电介质层250中的封装互连273、276电耦合。在一个实施例中，管芯互连291、292形成在第三电介质层中，其中管芯互连291、292与管芯互连271、272电耦合。
在一个实施例中，阻焊层400形成在第三电介质层280上。在一个实施例中，阻焊层400包括暴露管芯互连291、292和封装互连293、294的开口。焊球或焊料凸块411、412、413、414形成在管芯互连291、292和封装互连293、294上。焊料凸块411、412与管芯互连291、292电耦合。焊料凸块413、414与封装互连293、294电耦合。图1示出了在半导体封装201上形成焊料凸块411、412、413、414以产生球栅阵列（BGA）布图。BGA布图的布线或迹线能够形成在阻焊层400上。能够明白其它类型的布图，例如平面栅格阵列（LGA），能够形成在半导体封装201上。
在一个实施例中，具有管芯互连271、272、291、292和封装互连273-276、293、294的电介质层210、250、280构成无芯基底，其中管芯300整个地嵌入在无芯基底中。通过将管芯300嵌入在半导体封装201的无芯基底中，消除了在常规倒装芯片组装中所通常使用的组装步骤，从而减少了组装成本。另外，半导体封装201不再限于带状制造能力，其能实现全面板（fullpanel）处理，进一步减少了制造成本。此外，半导体封装201能实现混合技术管芯堆叠或封装堆叠。因此，半导体封装201提供了低外形封装、薄管芯组装、POP兼容性、混合技术（例如引线键合）管芯堆叠在减少封装组装成本方面的优势。
图2示出了在半导体封装201上的管芯堆叠的范例。在一个实施例中，另一管芯500附着在半导体封装201上。管芯500固定或粘附于粘附层220的顶表面221。多个引线键合互连511、512、513、514将管芯500与半导体封装201的封装焊盘231、232、233、234电耦合。能够将模制化合物层（未示出）用于保护顶部管芯并包封引线键合。在本发明的实施例中，能够将图2中所示的最终封装附着至印刷电路板（PCB），其中，封装焊盘231、232、233、234和封装互连273、274、275、276、293、294用作管芯500与PCB上的迹线之间的电连接。
在本发明的实施例中，具有附加管芯500的半导体封装201形成能够用在各种应用中的系统级封装（SIP），例如便携或手持设备，诸如膝上型电脑或移动电话。在特定实施例中，管芯300是包含处理器模块的片上系统（SOC），而管芯500是用于SOC的存储模块。
图3示出了在半导体封装201上的封装堆叠的范例。在本发明的实施例中，能够将另一封装600附着至半导体封装201，以形成封装上封装（POP）结构。在一个实施例中，封装600包括与封装基底620电耦合的管芯610。模制帽（mold cap）包封管芯610，并且用作管芯610的保护盖（cover）。在一个实施例中，多个互连，例如焊料凸块651、652、653、654能够用于将管芯610与半导体封装201的封装焊盘231、232、233、234电耦合。
在一个实施例中，图3中所示的POP结构是系统级封装。在特定实施例中，管芯300可以是包含处理器模块的SOC，而管芯610可以是用于SOC的附加逻辑芯片。在一个实施例中，封装600是倒装芯片封装。
在本发明的实施例中，能够结合管芯堆叠和封装堆叠技术来使用半导体封装201。在一个实施例中，如图4中所示，管芯500附着至粘附层220的顶表面221。引线键合互连512、513将管芯500与封装焊盘232、233电耦合。封装600堆叠在管芯500和半导体封装201上。焊料凸块651、654将封装600与封装焊盘231、234电耦合。
在替代实施例中，管芯300完全嵌入在没有封装焊盘231、232、233、234和封装互连273、274、275、276、293、294的半导体封装中。例如，图5示出了包括管芯互连271、272、291、292、295、296的替代的半导体封装201’。焊料凸块411、412、413、414形成在管芯互连291、292、295、296上。
图6A-6L示出了形成图1中所示的半导体封装201的方法。如图6A中所示，半导体封装201的制造从提供面板或载体100开始。在一个实施例中，载体100包括能在其上进行镀覆的导电表面110。在特定实施例中，载体100由诸如铜的导电金属制成，并且导电表面110是铜表面。在一个实施例中，载体100的厚度大约为50μm。
接下来，如图6B中所示，第一电介质层210形成在载体100的导电表面110上。在一个实施例中，第一电介质层210包括顶表面211和底表面212，其中顶表面211形成在导电表面110上。在一个实施例中，第一电介质层210的厚度与随后嵌入到第一电介质层210中的管芯的厚度大致相同。例如，第一电介质层的厚度大约为50-150μm。接下来，如图6C中所示，管芯空腔213和多个焊盘开口214、215、216、217形成在第一电介质层210中。在一个实施例中，管芯空腔213设置在中间，并且延伸穿过第一电介质层210，以暴露导电表面110上的管芯区域111。多个焊盘开口214、215、216、217暴露导电表面110上的多个焊盘区域112、113、114、115。
在本发明的实施例中，第一电介质层210由光可成像或光可限定材料制成。在一个实施例中，第一电介质层210由正性光可限定材料制成，其中通过对第一电介质层210进行显影来去除第一电介质层210暴露于辐射源的部分。在另一实施例中，第一电介质层210由负性光可限定材料制成，其中通过对第一电介质层210进行显影来保留第一电介质层210暴露于辐射源的部分。光可限定材料包括但不限于基于环氧树脂的光致抗蚀剂。在本发明的实施例中，（光可限定的）第一电介质层210的制造从在导电表面110上层压光可限定材料层开始（如图6B中所示）。接下来，光可限定材料暴露于辐射源并且随后被显影以限定管芯空腔211和多个焊盘开口212、213、214、215（如图6C中所示）。
在替代实施例中，第一电介质层210由非光可限定的普通电介质材料制成。在此情况下，通过在导电表面110上沉积第一电介质层210来制造第一电介质层210（如图6B中所示），接着在第一电介质层210中限定管芯空腔211和焊盘开口212、213、214、215（如图6C中所示）。在一个实施例中，通过普通光刻和蚀刻工艺来限定或产生管芯空腔211和焊盘开口212、213、214、215，诸如但不限于等离子体蚀刻工艺。在另一实施例中，通过使用半导体制造中通常使用的激光或机械钻孔工艺来限定管芯空腔211和焊盘开口212、213、214、215。
接下来，如图6D中所示，粘附层220形成在导电表面110的管芯区域111上。粘附层220包括顶表面221和底表面222。在一个实施例中，顶表面221形成在管芯区域111上，使得其基本上与第一电介质层210的顶表面211共面。在一个实施例中，粘附层220喷涂在管芯区域111上。在另一实施例中，通过使用公知的丝网印刷技术来形成粘附层220。例如，使用网格掩模（未示出）将粘附材料印刷在管芯区域111上，并且接下来固化粘附材料以形成覆盖整个管芯区域111的粘附层220。在一个实施例中，粘附层220仅选择性地形成在管芯区域111上。也就是说，粘附层220不形成在焊盘区域112、113、114、115上。
在一个实施例中，形成的粘附层220的厚度大约为10至50μm。粘附层220由诸如但不限于填充的基于环氧树脂的材料的材料制成。在本发明的实施例中，粘附层220保持作为半导体封装201的永久特征，用于保护随后嵌入到第一电介质层210中的管芯。此外，能够将粘附层220用作用于随后进行标记的表面或者用于最小化任何可能发生在管芯内的翘曲。
接下来，如图6E中所示，多个封装焊盘231、232、233、234形成在导电表面110的焊盘区域112、113、114、115上。在本发明的实施例中，通过使用公知的电解镀覆技术来形成多个封装焊盘231、232、233、234。在一个实施例中，焊盘区域112、113、114、115的电镀从在第一电介质层210上形成抗蚀剂层（未示出）开始，其中对抗蚀剂层进行构图以暴露焊盘区域112、113、114、115。接下来，使用诸如但不限于金（Au）、钯（Pd）、镍（Ni）和铜（Cu）的金属来电镀焊盘区域112、113、114、115。在本发明的特定实施例中，以下列顺序电镀焊盘区域112、113、114、115：金，接着是钯，接着是镍。在此情况下，多个封装焊盘231、232、233、234包括金、钯和镍的合成物或多层堆叠。在电镀工艺完成后，从第一电介质层210去除抗蚀剂层。
接下来，如图6F中所示，管芯300附着至粘附层220。管芯300包括前侧310和后侧320。在一个实施例中，管芯300的前侧310包括多个管芯焊盘341、342。在一个实施例中，能够使用公知的管芯设置技术来将管芯300插入至管芯空腔211中。随后将管芯300固定或粘附至粘附层220。在一个实施例中，管芯240的后侧320粘附至粘附层220。
图6D和6F描述了在将管芯300附着至粘附层220上之前，在载体100上形成粘附层220。在替代实施例中，在将带有粘附膜的管芯300设置到载体100上之前，先将粘附膜附着至管芯后侧320。例如，从图6C开始，将在其后侧320上带有粘附膜的管芯300设置在载体的管芯区域111上，使得粘附膜将管芯300固定在载体100上。在此情况下，粘附膜仅形成在管芯300的下方，且不延伸到管芯300的边缘之外。也就是说，粘附膜不覆盖整个管芯区域111。
粘附层220用作管芯后侧320的保护层。此外，能够将粘附层220用于最小化任何可能发生在管芯300内的翘曲。在一个实施例中，粘附层220包括UV-可固化的特性，随后能够将其激活以将引线键合管芯附着至粘附层220的顶表面221。在一个实施例中，粘附层220包括导热特性，这有利于管芯300的热耗散。
接下来，如图6G中所示，第二电介质层250形成在第一电介质层210和管芯300上。在本发明的实施例中，第二电介质层250由公知的层压技术来形成。第二电介质层250能够由诸如但不限于填充的基于环氧树脂的合成材料的材料制造。在一个实施例中，形成的第二电介质层250的厚度大约为10-30μm。
在一个实施例中，第二电介质层250包封了整个管芯300，包括管芯300的前侧310和侧壁。此外，第二电介质层250形成在多个封装焊盘231、232、233、234上。在一个实施例中，第二电介质层250形成有水平表面251，以有利于随后的内建（build-up）工艺。
接下来，多个互连形成在管芯焊盘341、342和封装焊盘231、232、233、234上。在本发明的实施例中，使用半加成工艺（SAP）来形成所述多个互连。例如，在图6H中，多个互连的制造从在第二电介质层250中形成通路孔261、262、263、264、265、266开始。在一个实施例中，通路孔261、262暴露管芯300的前侧310上的管芯焊盘341、342，而通路孔263、264、265、266则暴露封装焊盘231、232、233、234。
在一个实施例中，通过机械或激光钻孔工艺来形成通路孔261、262、263、264、265、266。在一个实施例中，由于不同的直径和深度，在单独的钻孔工艺中限定通路孔261、262和通路孔263、264、265、266。例如，通过使用UVYAG激光源来形成通路孔261、262。形成的通路孔261、262的直径尺寸小于50μm。然后，用CO2激光源来形成通路孔263、264、265、266。形成的通路孔263、264、265、266的直径尺寸大约为50-150μm。在本发明的实施例中，通过使用在基底制造中通常使用的、基于高锰酸盐化学反应（chemistry）的表面沾污去除工艺能够清洁通路孔261、262、263、264、265、266的表面。
在形成通路孔261、262、263、264、265、266之后，金属层（未示出）沉积在通路孔261、262、263、264、265、266中，并且沉积在管芯焊盘341、342和封装焊盘231、232、233、234上。在特定实施例中，金属层从由无电镀覆沉积的铜晶种层开始。随后，使用公知的光刻、电解铜镀覆、脱胶以及蚀刻技术来对金属层进行构图，以形成图6I中所示的单独的互连271、272、273、274、275、276。在一个实施例中，管芯互连271、272形成在管芯焊盘341、342上，而封装互连273、274、275、276则形成在封装焊盘231、232、233、234上。可以在单独的工艺中形成管芯互连271、272和封装互连273、274、275、276。
通过使用SAP内建工艺，能够增加半导体封装中内建层的数量。例如，重复形成电介质层接着形成互连的步骤，从而产生更多的金属化层。例如，在图6J中，第三电介质层280形成在第二电介质层250和互连271、272、273、274、275、276上。然后，多个互连291、292、293、294形成在第三电介质层280中。在一个实施例中，管芯互连291、292形成在管芯互连271、272上，使得互连291、292与管芯互连271、272电耦合。封装互连293、294形成在互连273、276上，其中封装互连293、294与互连273、276电耦合。
为了例示的目的，图6J仅示出了两层内建层（即电介质层250、280）。能够明白的是能够根据封装设计增加电介质层或内建层的数量。在通常的设计中，大约3-6层内建层构成半导体封装。
在本发明的实施例中，如图6K中所示，阻焊层400形成在最上方的电介质层（即第三电介质层280）上。在一个实施例中，阻焊层400形成有暴露管芯互连291、292和封装互连293、294的开口。在一个实施例中，能够在第三电介质层280上丝网印刷或层压阻焊层400。然后，能够在阻焊层400上执行激光处理来限定暴露管芯互连291、292和封装互连293、294的开口。在另一实施例中，阻焊层400由能够暴露于辐射源并显影以形成开口的光可限定聚合物材料制成。
接下来，如图6L中所示，从半导体封装201去除载体100，以暴露封装焊盘231、232、233、234和粘附层220。在一个实施例中，通过使用公知的蚀刻工艺来去除载体100。在一个实施例中，蚀刻使用基本上对第一电介质层210、粘附层220和封装焊盘231、232、233、234是选择性的蚀刻化学反应。也就是说，蚀刻化学反应去除载体100比它去除第一电介质层210、粘附层220或封装焊盘231、232、233、234要快。
然后，焊球或焊料凸块411、412形成在暴露的互连292、293上。焊料凸块411、412由公知的焊接材料制成并且通过公知的技术（诸如但不限于蒸发、电镀或直接设置）形成。这完成了图1中所示的半导体器件的制造。图6A-6K示出了在载体100的一侧上的半导体封装201的制造。能够理解的是，能够使用载体100的两侧来同时形成两个半导体封装。在另一实施例中，可以先将管芯300附着至载体100（图6M）。例如，通过层压工艺，可以在管芯上形成层211（图6N）。例如，可以使用单层211来替代图6I的两层210和250来根据本文中先前描述的方法形成图6O中的结构。
图7A-7E示出了形成图5中所示的半导体封装201’的方法。除了半导体封装201’中未形成封装互连以外，半导体封装201’的制造类似于图6A-6L中所描述的工艺。从图6B继续，如图7A中所示，仅在第一电介质层210中形成管芯空腔213。接下来，如图7B中所示，粘附层220和管芯300附着在载体100的管芯区域111上。形成粘附层220和附着管芯300的方法类似于图6D和6F，因此这里不再赘述。
接下来，在图7C中，第二电介质层250形成在第一电介质层210和管芯300上，接着在管芯焊盘341、342上形成管芯互连271、272。形成第二电介质层250和管芯互连271、272的方法类似于图6G、6H和6I中所描述的工艺。在一个实施例中，在管芯互连271、272的制造期间，形成金属线277、278。然后，如图7D中所示，第三电介质层280形成在第二电介质层290上。管芯互连291、292、295、296形成在第三电介质层280上。在此情况下，附加的管芯互连295、296形成在金属线277、278上。阻焊层400形成在第三电介质层280上并且暴露管芯互连291、292、295、296。
接下来，在图7E中，使用与图6K中所描述的类似的方法，从半导体封装201去除载体100。然后，在管芯互连291、292、295、296上形成焊料凸块411、412、413、414。这完成了如图5中所示的半导体封装201’的制造。在另一实施例中，可以先将管芯300附着至载体100，并且通过层压处理，例如以类似于图6M-6O中所示出的方式，可以在管芯300上形成可以代替层210和250的单层（类似于图6N中的层211）。
图8示出了根据本发明的实施例的计算机系统。在某些实施例中，系统800包括处理器810、存储器件820、存储器控制器830、图形控制器840、输入和输出（I/O）控制器850、显示器852、键盘854、定位设备856以及外围设备858，所有的这些可以通过总线860互相通信地耦合。处理器810可以是通用处理器或专用集成电路（ASIC）。I/O控制器850可以包括用于有线或无线通信的通信模块。存储器件820可以是动态随机存取存储（DRAM）器件、静态随机存取存储（SRAM）器件、闪存器件或者这些存储器件的组合。因此，在某些实施例中，系统800中的存储器件820不是必须包括DRAM器件。
系统800中所示的一个或多个部件可以包括在一个或多个集成电路封装中，并且或者可以包括一个或多个集成电路封装，诸如（例如）图7E的封装结构。例如，处理器810或存储器件820或至少部分I/O控制器850或这些部件的组合可以包括在包括各个实施例中所描述的结构的至少一个实施例的集成电路封装中。
这些元件执行本领域公知的它们的常规的功能。特别地，在某些情况下，可以使用存储器件820来提供对根据本发明的实施例形成封装结构的方法的可执行指令的长期存储，并且在其它实施例中，存储器件820可以用于短期存储在处理器810执行期间根据本发明的实施例形成封装结构的方法的可执行指令。此外，可以存储指令，否则，所述指令可以与与系统通信地耦合的机器可存取介质相关联，例如，与系统通信地耦合的机器可存取介质诸如光盘只读存储器（CD-ROM）、数字多功能盘（DVD）和软盘、载波和/或其它传播信号。在一个实施例中，存储器件820可以给处理器810提供用于执行的可执行指令。
系统800可以包括计算机（例如，台式电脑、膝上型电脑、手持电脑、服务器、网络设备、路由器等）、无线通信设备（例如，蜂窝电话、无绳电话、寻呼机、个人数字助理等）、计算机相关外围设备（例如，打印机，扫描仪、监视器等）、娱乐设备（例如，电视、收音机、立体声、磁带及光盘播放器、盒式录像机、摄像放像机、数码相机、MP3（动态影像专家组，音频层3）播放器、视频游戏、手表等），等等。
已经描述了本发明的数个实施例。然而，本领域技术人员会认识到本发明不限于所描述的实施例，而能够在以下所附的权利要求的精神和范围内以修改和变化实施本发明。

Claims (19)

1.一种形成半导体封装的方法，包括：
提供具有导电表面的载体；
在所述载体的所述导电表面上形成第一电介质层，所述第一电介质层具有暴露所述导电表面上的管芯区域的管芯空腔；
在所述导电表面的所述管芯区域上形成粘附层；
将第一管芯附着到所述粘附层的下表面上，所述第一管芯具有固定至所述粘附层的后侧和具有多个管芯焊盘的前侧；
在所述第一电介质层和所述第一管芯上沉积第二电介质层；
在所述第一管芯的所述前侧上的所述多个管芯焊盘上形成多个管芯互连；
去除所述载体以暴露所述粘附层；
将第二管芯粘附至所述粘附层的上表面；以及
将另一封装附着至所述半导体封装，并堆叠在所述第二管芯和所述半导体封装上，其中所述另一封装包括第三管芯，
其中，形成所述第一电介质层还包括：
在所述第一电介质层中形成多个焊盘开口，所述多个焊盘开口暴露所述导电表面上的多个焊盘区域；
在所述导电表面的所述多个焊盘区域上形成多个封装焊盘；以及
在所述多个封装焊盘上形成多个封装互连，其中所述多个封装互连形成在所述第二电介质层中，并且与形成在所述第一电介质层中的所述多个封装焊盘电耦合。
2.根据权利要求1所述的方法，其中，所述第一电介质层是光可限定电介质材料。
3.根据权利要求2所述的方法，其中，通过以下步骤形成所述第一电介质层：
在所述导电表面上层压所述光可限定电介质材料；以及
将所述第一电介质层曝光于辐射源，并且对所述第一电介质层进行显影，以在所述第一电介质层中限定所述管芯空腔和所述多个焊盘开口。
4.根据权利要求1所述的方法，其中，形成所述第一电介质层包括：
在所述导电表面上沉积所述第一电介质层；以及
在所述第一电介质层中限定所述管芯空腔和所述多个焊盘开口。
5.根据权利要求4所述的方法，其中，通过蚀刻工艺来限定所述管芯空腔和所述多个焊盘开口。
6.根据权利要求4所述的方法，其中，通过激光或机械钻孔工艺来限定所述管芯空腔和所述多个焊盘开口。
7.根据权利要求1所述的方法，其中，通过电解镀覆所述多个焊盘区域来形成所述多个封装焊盘。
8.根据权利要求1所述的方法，其中，在所述管芯区域上喷涂或丝网印刷所述粘附层。
9.根据权利要求1所述的方法，其中，形成所述多个管芯互连包括：
在所述第二电介质层中形成多个第一通路孔，所述多个第一通路孔暴露所述第一管芯的所述前侧的所述多个管芯焊盘；
在所述多个第一通路孔中和所述多个管芯焊盘上形成金属层；以及
蚀刻所述金属层以形成所述多个管芯互连。
10.根据权利要求1所述的方法，其中，形成所述多个封装互连包括：
在所述电介质层中形成多个第二通路孔，所述多个第二通路孔暴露所述多个封装焊盘；
在所述多个第二通路孔中和所述多个封装焊盘上形成金属层；以及
蚀刻所述金属层以形成所述多个封装互连。
11.根据权利要求1所述的方法，还包括：
在所述第二电介质层上沉积第三电介质层；以及
在所述多个管芯互连或所述多个封装互连上形成多个互连。
12.根据权利要求1所述的方法，还包括：
在所述第二电介质层上形成阻焊层；以及
形成多个焊料凸块，其中所述多个焊料凸块与所述多个管芯互连或者所述多个封装互连电耦合。
13.一种半导体封装，包括：
第一封装，包括：
第一电介质层，具有顶表面和延伸穿过所述第一电介质层的空腔；
形成在所述第一电介质层的所述空腔中的粘附层，所述粘附层具有上表面和下表面，其中所述上表面基本上与所述第一电介质层的顶表面共面；
形成在所述空腔中的第一管芯，所述第一管芯具有前侧和后侧，其中所述前侧包括多个管芯焊盘，并且其中所述后侧粘附于所述粘附层的所述下表面；
形成在所述第一电介质层的底表面和所述第一管芯的所述前侧上的第二电介质层；
电耦合到所述第一管芯的所述前侧上的所述多个管芯焊盘的多个管芯互连；
形成在所述第一电介质层中的多个封装焊盘，其中所述多个封装焊盘中的每个封装焊盘都包括基本上与所述第一电介质层的所述顶表面共面的暴露的表面；以及
电耦合到所述多个封装焊盘的多个封装互连，其中所述多个封装互连形成在所述第二电介质层中；
第二管芯，所述第二管芯粘附至所述第一封装中的所述粘附层的所述上表面；以及
第二封装，所述第二封装附着至所述第一封装并堆叠在所述第二管芯和所述第一封装上，其中所述第二封装包括第三管芯。
14.根据权利要求13所述的半导体封装，还包括：
将所述第二管芯电耦合到所述第一封装的所述多个封装焊盘的多个引线键合互连。
15.根据权利要求13所述的半导体封装，其中所述第二封装还包括：将所述第三管芯电耦合到所述第一封装中的所述多个封装焊盘的多个互连。
16.根据权利要求13所述的半导体封装，其中，所述多个封装焊盘包括金、钯和镍的合成物。
17.根据权利要求13所述的半导体封装，还包括：
电耦合到所述多个管芯互连的多个第一焊料凸块。
18.根据权利要求13所述的半导体封装，还包括：
电耦合到所述多个封装互连的多个第二焊料凸块。
19.根据权利要求13所述的半导体封装，其中，处理器、或存储器件、或至少部分I/O控制器中的任一个被包括在所述半导体封装中。
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US9780054B2 (en) 2017-10-03
US8901724B2 (en) 2014-12-02
TW201131735A (en) 2011-09-16
US20150050781A1 (en) 2015-02-19
WO2011090570A3 (en) 2011-10-13
TWI539574B (zh) 2016-06-21
KR101478515B1 (ko) 2015-01-02
WO2011090570A2 (en) 2011-07-28
CN102640283A (zh) 2012-08-15
US20110215464A1 (en) 2011-09-08
KR20120098844A (ko) 2012-09-05

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