US9673171B1 - Integrated circuit packaging system with coreless substrate and method of manufacture thereof - Google Patents

Integrated circuit packaging system with coreless substrate and method of manufacture thereof Download PDF

Info

Publication number
US9673171B1
US9673171B1 US14/226,711 US201414226711A US9673171B1 US 9673171 B1 US9673171 B1 US 9673171B1 US 201414226711 A US201414226711 A US 201414226711A US 9673171 B1 US9673171 B1 US 9673171B1
Authority
US
United States
Prior art keywords
semiconductor die
layer
integrated circuit
insulation layer
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/226,711
Inventor
HeeJo Chi
Heesoo Lee
Omin Kwon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to US14/226,711 priority Critical patent/US9673171B1/en
Assigned to STATS CHIPPAC LTD. reassignment STATS CHIPPAC LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHI, HEEJO, KWON, OMIN, LEE, HEESOO
Assigned to STATS ChipPAC Pte. Ltd. reassignment STATS ChipPAC Pte. Ltd. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: STATS CHIPPAC LTD.
Application granted granted Critical
Publication of US9673171B1 publication Critical patent/US9673171B1/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates generally to an integrated circuit packaging system, and more particularly to a system for packaging integrated circuit die with a coreless substrate.
  • the commercial demand for more function in less space can cause manufacturers to make compromises that decrease reliability or manufacturing yield.
  • the additional pressure of cost reductions can pressure manufacturers to make compromises that can reduce the long term reliability of the integrated circuit products.
  • the present invention provides a method of manufacture of an integrated circuit packaging system including: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
  • the present invention provides an integrated circuit packaging system, including: a semiconductor die having semiconductor die contacts; an insulation layer on the semiconductor die including the semiconductor die contacts exposed from the insulation layer; a conductive layer on the semiconductor die contacts and the insulation layer; and system interconnects coupled to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
  • FIG. 1 is a bottom view of a first embodiment of an integrated circuit packaging system.
  • FIG. 2 is a cross-sectional view of the first embodiment of the integrated circuit packaging system along the section line 2 - 2 of FIG. 1 .
  • FIG. 3 is a cross-sectional view of a second embodiment of the integrated circuit packaging system along the section line 2 - 2 of FIG. 1 .
  • FIG. 4 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in a substrate forming phase of manufacturing.
  • FIG. 5 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in a semiconductor die attach phase of manufacturing.
  • FIG. 6 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in an insulation layer forming phase of manufacturing.
  • FIG. 7 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in a conductor deposition phase of manufacturing.
  • FIG. 8 is a cross-sectional view of the embodiment of the base substrate in a package separation phase of manufacturing.
  • FIG. 9 is a cross-sectional view of a sub-assembly of a third embodiment of the integrated circuit packaging system in an insulation layer forming phase of manufacturing.
  • FIG. 10 is a cross-sectional view of a sub-assembly of the third embodiment of the integrated circuit packaging system in a contact forming phase of manufacturing.
  • FIG. 11 is a cross-sectional view of the third embodiment of the integrated circuit packaging system in a package separation phase of manufacturing.
  • FIG. 12 is a cross-sectional view of a fourth embodiment of the integrated circuit packaging system along the section line substantially similar to 2 - 2 of FIG. 1 .
  • FIG. 13 is a cross-sectional view of a fifth embodiment of the integrated circuit packaging system along the section line substantially similar to 2 - 2 of FIG. 1 .
  • FIG. 14 is a cross-sectional view of a sixth embodiment of the integrated circuit packaging system along the section line substantially similar to 2 - 2 of FIG. 1 .
  • FIG. 15 is a flow chart of a method of manufacture of an integrated circuit packaging system in a further embodiment of the present invention.
  • the term “horizontal” as used herein is defined as a plane parallel to the plane or active surface of the semiconductor die, regardless of its orientation.
  • the term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures.
  • the term “on” means there is direct physical contact between elements with no intervening elements.
  • processing includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
  • FIG. 1 therein is shown a bottom view of a first embodiment of an integrated circuit packaging system 100 .
  • the bottom view of the first embodiment of the integrated circuit packaging system 100 depicts a base package 102 having an array of system interconnects 104 mounted in contact with a solder resist layer 106 .
  • the number and position of the system interconnects 104 is an example only and the actual number and position can differ.
  • the integrated circuit packaging system 100 is shown as a square shape having an equal number of columns and rows of the system interconnects 104 , but it is understood that the system interconnects 104 can form any pattern on the integrated circuit packaging system 100 .
  • a section line 2 - 2 can show the position and direction of view of the integrated circuit packaging system 100 in FIG. 2 .
  • FIG. 2 therein is shown a cross-sectional view of the first embodiment of the integrated circuit packaging system 100 along the section line 2 - 2 of FIG. 1 .
  • the cross-sectional view of the first embodiment of the integrated circuit packaging system 100 depicts the base package 102 having a semiconductor die 202 with an inactive side coupled to an adhesive 204 , such as a thermal adhesive, a die attach adhesive, a thermal epoxy, or the like.
  • An insulation layer 206 can be formed on the semiconductor die 202 and coplanar with the adhesive 204 and a contact layer 208 , such as a copper foil layer, sputtered metal layer, or a patterned metal insert.
  • the insulation layer 206 can have boundary regions plated with a conductive layer 209 , such as copper, tin, nickel, silver, gold, or an alloy thereof, for forming filled vias 210 , open vias 212 , or a heat slug 214 .
  • the filled vias 210 can provide reliable, low resistance connections between the contact layer 208 and the system interconnects 104 .
  • the open vias 212 can be barrel shaped conductors formed in the insulation layer 206 and can be coupled directly on multiple of the system interconnects 104 in order to provide a reliable connection between the contact layer 208 , semiconductor die contacts 216 , and the system interconnects 104 .
  • the heat slug 214 can be formed of a thermally conductive material including copper foil, sputtered metal, a formed metal plug, thermal epoxy, or the like. The heat slug 214 can be in direct physical contact with an active side of the semiconductor die 202 and spaced away from the semiconductor die contacts 216 .
  • the solder resist layer 106 can be formed on the insulation layer 206 , the filled vias 210 , the open vias, 212 , and the heat slug 214 .
  • the solder resist layer 106 can be in contact with the system interconnects 104 and the inside region of the open vias 212 .
  • the base package 102 can provide a thin and reliable platform for assembling multiple integrated circuits in a single package format.
  • the base package 102 is able to be tested prior to further assembly and can represent a reliable and manufacturable package substrate for assembly of additional electronic functions.
  • a planar component surface 218 of the base package 102 can provide a mounting surface for a first stacked integrated circuit 220 , discrete analog components 222 , a flip chip integrated circuit 224 , or a combination thereof.
  • the discrete analog components 222 can include resistors, capacitors, inductors, diodes, transistors, voltage regulators, oscillators, filters, or the like.
  • a second stacked integrated circuit 226 can be mounted over the first stacked integrated circuit 220 .
  • a third stacked integrated circuit 228 can be mounted over the first stacked integrated circuit 220 and the second stacked integrated circuit 226 .
  • Component interconnects 230 such as bond wires, solder bumps, solder paste, stud bumps, solder columns, or the like, can couple the first stacked integrated circuit 220 , the discrete analog components 222 , the flip chip integrated circuit 224 , the second stacked integrated circuit 226 , and the third stacked integrated circuit 228 to the contact layer 208 of the planar component surface 218 .
  • a molded package body 232 can be formed on the first stacked integrated circuit 220 , the discrete analog components 222 , the flip chip integrated circuit 224 , the second stacked integrated circuit 226 , and the third stacked integrated circuit 228 to the contact layer 208 of the planar component surface 218 .
  • an embodiment of the integrated circuit packaging system 100 can provide a flexible and high volume platform for integration of multiple functions, in different technologies, including integrated circuit logic, the discrete analog components 222 , and thermal management features.
  • the base package 102 can be fabricated in various forms and can include one or more of the semiconductor die 202 as part of the available function.
  • the semiconductor die 202 can utilize the heat slug 214 for managing thermal reliability during operation.
  • FIG. 3 therein is shown a cross-sectional view of a second embodiment 300 of the integrated circuit packaging system 100 along the section line 2 - 2 of FIG. 1 .
  • the cross-sectional view of a second embodiment 300 depicts the base package 102 having the semiconductor die 202 mounted on the adhesive 204 .
  • the insulation layer 206 can be formed on the semiconductor die 202 to be coplanar with the adhesive 204 and the contact layer 208 , such as a copper foil layer, sputtered metal layer, or a patterned metal insert.
  • the insulation layer 206 can have boundary regions plated with a conductive material, such as copper, tin, nickel, silver, gold, or an alloy thereof, for forming the open vias 212 or the heat slug 214 .
  • the open vias 212 can be barrel shaped conductors formed in the insulation layer 206 and can be coupled to multiple of the system interconnects 104 in order to provide a reliable connection between the contact layer 208 , the semiconductor die contacts 216 , and the system interconnects 104 .
  • the heat slug 214 can be formed of a thermally conductive material including copper foil, sputtered metal, a formed metal plug, thermal epoxy, or the like.
  • the heat slug 214 can be in direct physical contact with an insulated area of the active side of the semiconductor die 202 .
  • the solder resist layer 106 can be formed on the insulation layer 206 , the open vias, 212 , and the heat slug 214 .
  • the solder resist layer 106 can be in contact with the system interconnects 104 and the inside region of the open vias 212 .
  • the second embodiment 300 of the integrated circuit packaging system 100 can provide a reduced size while maintaining the ability to house the first stacked integrated circuit 220 and the second stacked integrated circuit 226 .
  • the component interconnects 230 can electrically connect the first stacked integrated circuit 220 , the second stacked integrated circuit 226 , and the semiconductor die 202 through the contact layer 208 and the open vias 212 .
  • a connection to the next level system (not shown) can be made through the system interconnects 104 coupled to the open vias 212 .
  • the molded package body 232 can protect the component interconnects 230 and provide a rigid support for the base package 102 .
  • the shape of the molded package body 232 is an example only and the actual shape may differ. It is understood that the second embodiment 300 is an example of the possible configurations of the integrated circuit packaging system 100 .
  • the first stacked integrated circuit 220 and the second stacked integrated circuit 226 could be replaced by the flip chip integrated circuit 224 without changing the features of the second embodiment 300 .
  • FIG. 4 therein is shown a cross-sectional view of a sub-assembly 400 of the integrated circuit packaging system 100 of FIG. 1 in a substrate forming phase of manufacturing.
  • the cross-sectional view of a sub-assembly 400 depicts a manufacturing substrate 402 having a detachable material 404 on a top and bottom surfaces.
  • the detachable material 404 can be any material that can provide a releasable structure.
  • the detachable material 404 can be a “3 um Ni layer” between a “seed copper layer” and a “copperlayer”. Due to low adhesion between copper and Ni, the substrate is easily detached from the core during a detaching process.
  • the contact layer 208 such as a copper foil or sputtered metal layer, can be attached to the surface of the detachable material 404 opposite the manufacturing substrate 402 .
  • the detachable material 404 can be a thermally reactive adhesive that releases its adhesion with a thermal or ultrasonic stimulus.
  • the thickness of the contact layer 208 can be greater than or less that the thickness of the manufacturing substrate 402 .
  • the manufacturing substrate 402 can be formed of metal, polymer, composition material, such as FR4, or the like.
  • the detachable material 404 can be an ultra-violet releasable film that loses its adhesion when exposed to ultra-violet light.
  • the detachable material 404 can include thermally releasable material, or any adhesive material that can be released by an external source.
  • the manufacturing substrate 402 can be formed of an FR4 core having a copper layer applied to the top and bottom surfaces, or the manufacturing substrate 402 can be formed of a stainless steel core having a multi-level metal coating, including a 10 micro-meter copper layer with a 3 micro-meter nickel layer and a 3 micro-meter copper seed layer. It is understood that the manufacturing substrate 402 can be formed of other materials and of different thicknesses in embodiments of the present invention.
  • the manufacturing substrate 402 can provide assembly regions on both sides at the same time in order to double the productivity of the manufacturing process without increasing cost or compromising quality. It is understood that the manufacturing substrate 402 can be utilized on one side or both sides without changing the claimed embodiment of the invention.
  • FIG. 5 therein is shown a cross-sectional view of a sub-assembly 500 of the integrated circuit packaging system 100 of FIG. 1 in a semiconductor die 202 attach phase of manufacturing.
  • the cross-sectional view of a sub-assembly 500 depicts the contact layer 208 having been patterned to provide individual regions for electrical connection within the base package 102 of FIG. 2 .
  • the patterning of the contact layer 208 can be performed by etching or laser ablation with the detachable material 404 acting as a stop layer.
  • the adhesive 204 has been disposed within the patterned regions between the contact layer 208 for mounting the semiconductor die 202 .
  • the inactive side of the semiconductor die 202 can be in contact with the adhesive 204 .
  • the active side of the semiconductor die 202 can face away from the manufacturing substrate 402 .
  • the semiconductor die 202 attach phase of manufacturing can process both sides of the manufacturing substrate 402 concurrently.
  • the patterning of the contact layer 208 is an example only and the entire region beneath the semiconductor die can be removed. In the case that there is none of the contact layer 208 between the semiconductor die 202 and the detachable material 404 , the adhesive 204 will only be applied to the space directly between the semiconductor die 202 and the detachable material 404 .
  • FIG. 6 therein is shown a cross-sectional view of a sub-assembly 600 of the integrated circuit packaging system 100 of FIG. 1 in an insulation layer 206 forming phase of manufacturing.
  • the cross-sectional view of the sub-assembly 600 depicts the insulation layer 206 formed on the semiconductor die 202 and the contact layer 208 .
  • Via openings 602 can be formed in the insulation layer 206 for exposing the contact layer 208 and the semiconductor die contacts 216 .
  • the via opening 602 can also expose the insulated surface of the active side of the semiconductor die 202 separated from the semiconductor die contacts 216 .
  • the configuration of the sub-assembly 600 is built on both sides of the manufacturing substrate 402 at the same time.
  • the detachable material 404 will subsequently allow the release of the finished package.
  • FIG. 7 therein is shown a cross-sectional view of a sub-assembly 700 of the integrated circuit packaging system 100 of FIG. 1 in a conductor deposition phase of manufacturing.
  • the cross-sectional view of the sub-assembly 700 depicts a conductive material 209 , such as a metal, alloy, or conductive epoxy, applied on all of the surfaces that were exposed in the sub-assembly 600 of FIG. 6 .
  • the conductive material 209 can subsequently be patterned to form circuits for electrical connection to the semiconductor die 202 or through the base package 102 of FIG. 2 .
  • the conductive material 209 can provide an electrically conductive path to the contact layer 208 and the semiconductor die contacts 216 .
  • the conductive material 209 can form the heat slug 214 on the insulated region of the active side of the semiconductor die 202 . It is understood that the area of the active region of the semiconductor die 202 that is away from the semiconductor die contacts 216 will be coated by a polysilicon material to electrically insulate the circuits within the semiconductor die 202 from external electrical contact but is a good conductor of heat.
  • the forming of the heat slug 214 directly on the area of the active region of the semiconductor die 202 that is away from the semiconductor die contacts 216 will provide a very efficient thermal management feature without adding additional components or processes.
  • the conductive material 209 can be used to fill the via opening 602 of FIG. 6 in order to form the filled vias 210 of FIG. 2 or just to coat the sidewalls of the via opening 602 in order to form the open vias 212 of FIG. 2 .
  • the solder resist layer 106 can be formed on the conductive material 209 , the insulation layer 206 and the heat slug 214 .
  • the solder resist layer 106 can then be patterned to provide access sites 704 for electrical connection to the system interconnects 104 of FIG. 1 . It is understood that the configuration of the sub-assembly 700 is built on both sides of the manufacturing substrate 402 at the same time.
  • the detachable material 404 will subsequently allow the release of the finished package.
  • FIG. 8 therein is shown a cross-sectional view of the embodiment of the base package 102 in a package separation phase of manufacturing.
  • the cross-sectional view of the embodiment of the base package 102 depicts the base package 102 having been released from the manufacturing substrate 402 of FIG. 7 by activating the detachable material 404 of FIG. 7 .
  • the activation of the detachable material 404 can be the result of a change in temperature, being subject to ultra-sonic energy, being subject to ultra-violet light, or the like.
  • the features of the base package 102 can function as a stand-alone integrated circuit package and can be tested as such prior to additional assembly.
  • the addition of the heat slug 214 can allow the base package 102 to integrate high power devices or large highly integrated versions of the semiconductor die 202 .
  • the inclusion of the contact layer 208 and the adhesive 204 can provide additional thermal management features as well as options for further electrical connections.
  • the base package 102 can support electrical connections between the semiconductor die 202 , the system interconnects 104 , the contact layer 208 or a combination thereof.
  • the contact layer 208 exposed on a coplanar surface of the base package 102 opposite the system interconnects 104 can provide for additional vertical integration of the first stacked integrated circuit 220 of FIG. 2 , the discrete analog components 222 of FIG. 2 , a flip chip integrated circuit 224 of FIG. 2 , or a combination thereof.
  • FIG. 9 therein is shown a cross-sectional view of a sub-assembly 900 of a third embodiment of the integrated circuit packaging system 100 of FIG. 1 in an insulation layer forming phase of manufacturing.
  • the cross-sectional view of the third embodiment 900 depicts the manufacturing substrate 402 having the detachable material 404 on opposing surfaces.
  • a heat spreader 902 can optionally be attached to the detachable material 404 .
  • the heat spreader 902 can be a copper film, a plate, a sputtered metal layer, or a thermal epoxy.
  • the semiconductor die 202 can be attached to the heat spreader 902 by the adhesive 204 , such as a thermal interface material, a die attach material, or thermal epoxy. In the event the heat spreader 902 is not implemented, the adhesive 204 can be attached directly to the detachable material 404 .
  • a stiffener 904 can be attached to the heat spreader 902 and completely surrounds the semiconductor die 202 .
  • the stiffener 904 can be formed from a metal sheet, preformed and cured thermal epoxy, preformed and cured epoxy molding compound, or a thermal crystal.
  • the stiffener 904 can be attached to the heat spreader 902 by a die attach material. In the event the heat spreader 902 is not implemented, the stiffener 904 can be attached directly to the detachable material 404 .
  • the insulation layer 206 can be formed on the heat spreader 902 , the semiconductor die 202 , the adhesive 204 , and the stiffener 904 . In the event the heat spreader 902 is not implemented, the insulation layer can be formed directly on the detachable material 404 . The insulation layer 206 can be patterned to open channels 906 to expose the semiconductor die contacts 216 of the semiconductor die 202 .
  • stiffener 904 can prevent the warping of a base package during the attachment to the next level system (not shown).
  • the selection of the material of the stiffener 904 can provide additional thermal management for the semiconductor die 202 that generates excessive heat.
  • FIG. 10 therein is shown a cross-sectional view of a sub-assembly 1000 of the third embodiment of the integrated circuit packaging system 100 in a contact forming phase of manufacturing.
  • the cross-sectional view of a sub-assembly 1000 depicts the conductive layer 209 deposited on the insulation layer 206 and the semiconductor die contacts 216 of the semiconductor die 202 .
  • the conductive layer 209 can be deposited through an opening in the insulation layer 206 to contact the stiffener 904 for providing an additional thermal management feature.
  • the solder resist layer 106 can be deposited on the conductive layer 209 and the insulation layer 206 .
  • the solder resist layer 106 can then be patterned to provide the access sites 704 for electrical connection to the system interconnects 104 of FIG. 1 . It is understood that the configuration of the sub-assembly 1000 is built on both sides of the manufacturing substrate 402 at the same time.
  • the detachable material 404 will subsequently allow the release of the base package.
  • FIG. 11 therein is shown a cross-sectional view of the third embodiment 1100 of the integrated circuit packaging system 100 in a package separation phase of manufacturing.
  • the cross-sectional view of the third embodiment 1100 depicts a base package 1102 having the semiconductor die 202 physically and thermally coupled to the heat spreader 902 by the adhesive 204 .
  • the stiffener 904 can provide a rigid platform and prevents the warping of the base package 1102 during the reflow process of the system interconnects 104 during assembly.
  • the base package 1102 can provide an ultra-thin ball grid array package with thermal management features.
  • the heat slug 214 of FIG. 2 can optionally be implemented in the area of the active region of the semiconductor die 202 that is away from the semiconductor die contacts 216 in order to provide a very efficient thermal management feature without adding additional components or processes.
  • the optional combination the heat spreader 902 , the stiffener 904 , coupled to the system interconnects 104 , and the heat slug 214 can provide extensive thermal management capable of supporting high power versions of the semiconductor die 202 in a high volume and reliable integrated circuit package.
  • the integrated circuit packaging system and device or product of the embodiments of the present invention furnish important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for manufacturing high volume flexible and reliable multi chip integrated circuit packages with thermal management features.
  • FIG. 12 therein is shown a cross-sectional view of a fourth embodiment 1200 of the integrated circuit packaging system 100 along the section line substantially similar to 2 - 2 of FIG. 1 .
  • the cross-sectional view of the fourth embodiment 1200 of the integrated circuit packaging system 100 includes the base package 102 having a top package 1202 mounted by package interconnects 1204 , such as solder balls, solder posts, solder bumps, stud bumps, or the like in a fan-out configuration.
  • the top package 1202 can include a top substrate 1206 having the first stacked integrated circuit 220 and the second stacked integrated circuit 226 .
  • a top package body 1208 can be formed of a molding compound, such as an epoxy molding compound, to cover the first stacked integrated circuit 220 , the second stacked integrated circuit 226 , and the component interconnects 230 .
  • the component interconnects 230 can electrically connect the first stacked integrated circuit 220 , the second stacked integrated circuit 226 , and the semiconductor die 202 through the package interconnects 1204 , contact layer 208 , and the open vias 212 .
  • FIG. 13 therein is shown a cross-sectional view of a fifth embodiment 1300 of the integrated circuit packaging system 100 along the section line substantially similar to 2 - 2 of FIG. 1 .
  • the cross-sectional view of the fifth embodiment 1300 of the integrated circuit packaging system 100 includes the base package 102 having a top package 1302 mounted by package interconnects 1204 , such as solder balls, solder posts, solder bumps, stud bumps, or the like in a fan-in configuration.
  • the top package 1302 can include the top substrate 1206 having the first stacked integrated circuit 220 and the second stacked integrated circuit 226 .
  • a top package body 1208 can be formed of a molding compound, such as an epoxy molding compound, to cover the first stacked integrated circuit 220 , the second stacked integrated circuit 226 , and the component interconnects 230 .
  • the component interconnects 230 can electrically connect the first stacked integrated circuit 220 , the second stacked integrated circuit 226 , and the semiconductor die 202 through the package interconnects 1204 , contact layer 208 , and the open vias 212 .
  • FIG. 14 therein is shown a cross-sectional view of a sixth embodiment 1400 of the integrated circuit packaging system 100 along the section line substantially similar to 2 - 2 of FIG. 1 .
  • the cross-sectional view of the sixth embodiment 1400 of the integrated circuit packaging system 100 includes the base package 102 having a top package 1402 mounted by package interconnects 1204 , such as solder balls, solder posts, solder bumps, stud bumps, or the like in a fan-out configuration.
  • the top package 1402 can include the top substrate 1206 having the discrete analog components 222 and the flip chip integrated circuit 224 mounted thereon.
  • the top package 1402 can be coupled to the base package 102 through the package interconnects 1204 . It is understood that the top package 1402 can be implemented without the discrete analog components 222 without changing the embodiment of the invention. It is further understood that the top package 1402 can include the flip chip integrated circuit 224 having a different number of the component interconnects 230 .
  • the method 1500 includes: providing a semiconductor die having semiconductor die contacts in a block 1502 ; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed in a block 1504 ; applying a conductive layer on the semiconductor die contacts and the insulation layer in a block 1506 ; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects in a block 1508 .
  • Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.

Abstract

An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.

Description

TECHNICAL FIELD
The present invention relates generally to an integrated circuit packaging system, and more particularly to a system for packaging integrated circuit die with a coreless substrate.
BACKGROUND ART
Electronic products have become an integral part of our daily lives. Packages of components such as semiconductor circuits, transistors, diodes, and other electronic devices have become smaller and thinner with more function and connections. In packaging components, the need for coupling components together in a reliable manner can influence the manufacturing processes.
The commercial demand for more function in less space can cause manufacturers to make compromises that decrease reliability or manufacturing yield. The additional pressure of cost reductions can pressure manufacturers to make compromises that can reduce the long term reliability of the integrated circuit products.
Thus, a need still remains for an integrated circuit packaging system that can reduce package size, support increased function, and maintain both manufacturing yield and long term reliability. In view of the extensive commercial pressures for high volume, small size, and reliability, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method of manufacture of an integrated circuit packaging system including: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
The present invention provides an integrated circuit packaging system, including: a semiconductor die having semiconductor die contacts; an insulation layer on the semiconductor die including the semiconductor die contacts exposed from the insulation layer; a conductive layer on the semiconductor die contacts and the insulation layer; and system interconnects coupled to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
Certain embodiments of the invention have other steps or elements in addition to or in place of those mentioned above. The steps or element will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a bottom view of a first embodiment of an integrated circuit packaging system.
FIG. 2 is a cross-sectional view of the first embodiment of the integrated circuit packaging system along the section line 2-2 of FIG. 1.
FIG. 3 is a cross-sectional view of a second embodiment of the integrated circuit packaging system along the section line 2-2 of FIG. 1.
FIG. 4 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in a substrate forming phase of manufacturing.
FIG. 5 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in a semiconductor die attach phase of manufacturing.
FIG. 6 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in an insulation layer forming phase of manufacturing.
FIG. 7 is a cross-sectional view of a sub-assembly of the integrated circuit packaging system in a conductor deposition phase of manufacturing.
FIG. 8 is a cross-sectional view of the embodiment of the base substrate in a package separation phase of manufacturing.
FIG. 9 is a cross-sectional view of a sub-assembly of a third embodiment of the integrated circuit packaging system in an insulation layer forming phase of manufacturing.
FIG. 10 is a cross-sectional view of a sub-assembly of the third embodiment of the integrated circuit packaging system in a contact forming phase of manufacturing.
FIG. 11 is a cross-sectional view of the third embodiment of the integrated circuit packaging system in a package separation phase of manufacturing.
FIG. 12 is a cross-sectional view of a fourth embodiment of the integrated circuit packaging system along the section line substantially similar to 2-2 of FIG. 1.
FIG. 13 is a cross-sectional view of a fifth embodiment of the integrated circuit packaging system along the section line substantially similar to 2-2 of FIG. 1.
FIG. 14 is a cross-sectional view of a sixth embodiment of the integrated circuit packaging system along the section line substantially similar to 2-2 of FIG. 1.
FIG. 15 is a flow chart of a method of manufacture of an integrated circuit packaging system in a further embodiment of the present invention.
 BEST MODE FOR CARRYING OUT THE INVENTION
The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.
The drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawing FIGs. Similarly, although the views in the drawings for ease of description generally show similar orientations, this depiction in the FIGs. is arbitrary for the most part. Generally, the invention can be operated in any orientation.
The same numbers are used in all the drawing FIGs. to relate to the same elements. The embodiments have been numbered first embodiment, second embodiment, etc. as a matter of descriptive convenience and are not intended to have any other significance or provide limitations for the present invention.
For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or active surface of the semiconductor die, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures. The term “on” means there is direct physical contact between elements with no intervening elements.
The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
Referring now to FIG. 1, therein is shown a bottom view of a first embodiment of an integrated circuit packaging system 100. The bottom view of the first embodiment of the integrated circuit packaging system 100 depicts a base package 102 having an array of system interconnects 104 mounted in contact with a solder resist layer 106.
It is understood that the number and position of the system interconnects 104 is an example only and the actual number and position can differ. By way of an example the integrated circuit packaging system 100 is shown as a square shape having an equal number of columns and rows of the system interconnects 104, but it is understood that the system interconnects 104 can form any pattern on the integrated circuit packaging system 100. A section line 2-2 can show the position and direction of view of the integrated circuit packaging system 100 in FIG. 2.
Referring now to FIG. 2, therein is shown a cross-sectional view of the first embodiment of the integrated circuit packaging system 100 along the section line 2-2 of FIG. 1. The cross-sectional view of the first embodiment of the integrated circuit packaging system 100 depicts the base package 102 having a semiconductor die 202 with an inactive side coupled to an adhesive 204, such as a thermal adhesive, a die attach adhesive, a thermal epoxy, or the like.
An insulation layer 206 can be formed on the semiconductor die 202 and coplanar with the adhesive 204 and a contact layer 208, such as a copper foil layer, sputtered metal layer, or a patterned metal insert. The insulation layer 206 can have boundary regions plated with a conductive layer 209, such as copper, tin, nickel, silver, gold, or an alloy thereof, for forming filled vias 210, open vias 212, or a heat slug 214. The filled vias 210 can provide reliable, low resistance connections between the contact layer 208 and the system interconnects 104. The open vias 212 can be barrel shaped conductors formed in the insulation layer 206 and can be coupled directly on multiple of the system interconnects 104 in order to provide a reliable connection between the contact layer 208, semiconductor die contacts 216, and the system interconnects 104. The heat slug 214 can be formed of a thermally conductive material including copper foil, sputtered metal, a formed metal plug, thermal epoxy, or the like. The heat slug 214 can be in direct physical contact with an active side of the semiconductor die 202 and spaced away from the semiconductor die contacts 216.
The solder resist layer 106 can be formed on the insulation layer 206, the filled vias 210, the open vias, 212, and the heat slug 214. The solder resist layer 106 can be in contact with the system interconnects 104 and the inside region of the open vias 212.
It has been discovered that the base package 102 can provide a thin and reliable platform for assembling multiple integrated circuits in a single package format. The base package 102 is able to be tested prior to further assembly and can represent a reliable and manufacturable package substrate for assembly of additional electronic functions.
A planar component surface 218 of the base package 102 can provide a mounting surface for a first stacked integrated circuit 220, discrete analog components 222, a flip chip integrated circuit 224, or a combination thereof. The discrete analog components 222 can include resistors, capacitors, inductors, diodes, transistors, voltage regulators, oscillators, filters, or the like.
A second stacked integrated circuit 226 can be mounted over the first stacked integrated circuit 220. A third stacked integrated circuit 228 can be mounted over the first stacked integrated circuit 220 and the second stacked integrated circuit 226. Component interconnects 230, such as bond wires, solder bumps, solder paste, stud bumps, solder columns, or the like, can couple the first stacked integrated circuit 220, the discrete analog components 222, the flip chip integrated circuit 224, the second stacked integrated circuit 226, and the third stacked integrated circuit 228 to the contact layer 208 of the planar component surface 218. A molded package body 232 can be formed on the first stacked integrated circuit 220, the discrete analog components 222, the flip chip integrated circuit 224, the second stacked integrated circuit 226, and the third stacked integrated circuit 228 to the contact layer 208 of the planar component surface 218.
It has been unexpectedly discovered that an embodiment of the integrated circuit packaging system 100 can provide a flexible and high volume platform for integration of multiple functions, in different technologies, including integrated circuit logic, the discrete analog components 222, and thermal management features. The base package 102 can be fabricated in various forms and can include one or more of the semiconductor die 202 as part of the available function. The semiconductor die 202 can utilize the heat slug 214 for managing thermal reliability during operation.
Referring now to FIG. 3, therein is shown a cross-sectional view of a second embodiment 300 of the integrated circuit packaging system 100 along the section line 2-2 of FIG. 1. The cross-sectional view of a second embodiment 300 depicts the base package 102 having the semiconductor die 202 mounted on the adhesive 204.
The insulation layer 206 can be formed on the semiconductor die 202 to be coplanar with the adhesive 204 and the contact layer 208, such as a copper foil layer, sputtered metal layer, or a patterned metal insert. The insulation layer 206 can have boundary regions plated with a conductive material, such as copper, tin, nickel, silver, gold, or an alloy thereof, for forming the open vias 212 or the heat slug 214. The open vias 212 can be barrel shaped conductors formed in the insulation layer 206 and can be coupled to multiple of the system interconnects 104 in order to provide a reliable connection between the contact layer 208, the semiconductor die contacts 216, and the system interconnects 104. The heat slug 214 can be formed of a thermally conductive material including copper foil, sputtered metal, a formed metal plug, thermal epoxy, or the like. The heat slug 214 can be in direct physical contact with an insulated area of the active side of the semiconductor die 202.
The solder resist layer 106 can be formed on the insulation layer 206, the open vias, 212, and the heat slug 214. The solder resist layer 106 can be in contact with the system interconnects 104 and the inside region of the open vias 212.
The second embodiment 300 of the integrated circuit packaging system 100 can provide a reduced size while maintaining the ability to house the first stacked integrated circuit 220 and the second stacked integrated circuit 226. The component interconnects 230 can electrically connect the first stacked integrated circuit 220, the second stacked integrated circuit 226, and the semiconductor die 202 through the contact layer 208 and the open vias 212. A connection to the next level system (not shown) can be made through the system interconnects 104 coupled to the open vias 212.
The molded package body 232 can protect the component interconnects 230 and provide a rigid support for the base package 102. The shape of the molded package body 232 is an example only and the actual shape may differ. It is understood that the second embodiment 300 is an example of the possible configurations of the integrated circuit packaging system 100. The first stacked integrated circuit 220 and the second stacked integrated circuit 226 could be replaced by the flip chip integrated circuit 224 without changing the features of the second embodiment 300.
Referring now to FIG. 4, therein is shown a cross-sectional view of a sub-assembly 400 of the integrated circuit packaging system 100 of FIG. 1 in a substrate forming phase of manufacturing. The cross-sectional view of a sub-assembly 400 depicts a manufacturing substrate 402 having a detachable material 404 on a top and bottom surfaces. The detachable material 404 can be any material that can provide a releasable structure. By way of an example, the detachable material 404 can be a “3 um Ni layer” between a “seed copper layer” and a “copperlayer”. Due to low adhesion between copper and Ni, the substrate is easily detached from the core during a detaching process. The contact layer 208, such as a copper foil or sputtered metal layer, can be attached to the surface of the detachable material 404 opposite the manufacturing substrate 402. The detachable material 404 can be a thermally reactive adhesive that releases its adhesion with a thermal or ultrasonic stimulus.
It is understood that the thickness of the contact layer 208 can be greater than or less that the thickness of the manufacturing substrate 402. The manufacturing substrate 402 can be formed of metal, polymer, composition material, such as FR4, or the like. The detachable material 404 can be an ultra-violet releasable film that loses its adhesion when exposed to ultra-violet light. The detachable material 404 can include thermally releasable material, or any adhesive material that can be released by an external source.
By way of an example, the manufacturing substrate 402 can be formed of an FR4 core having a copper layer applied to the top and bottom surfaces, or the manufacturing substrate 402 can be formed of a stainless steel core having a multi-level metal coating, including a 10 micro-meter copper layer with a 3 micro-meter nickel layer and a 3 micro-meter copper seed layer. It is understood that the manufacturing substrate 402 can be formed of other materials and of different thicknesses in embodiments of the present invention.
It has been discovered that the manufacturing substrate 402 can provide assembly regions on both sides at the same time in order to double the productivity of the manufacturing process without increasing cost or compromising quality. It is understood that the manufacturing substrate 402 can be utilized on one side or both sides without changing the claimed embodiment of the invention.
Referring now to FIG. 5, therein is shown a cross-sectional view of a sub-assembly 500 of the integrated circuit packaging system 100 of FIG. 1 in a semiconductor die 202 attach phase of manufacturing. The cross-sectional view of a sub-assembly 500 depicts the contact layer 208 having been patterned to provide individual regions for electrical connection within the base package 102 of FIG. 2. The patterning of the contact layer 208 can be performed by etching or laser ablation with the detachable material 404 acting as a stop layer.
The adhesive 204 has been disposed within the patterned regions between the contact layer 208 for mounting the semiconductor die 202. The inactive side of the semiconductor die 202 can be in contact with the adhesive 204. The active side of the semiconductor die 202 can face away from the manufacturing substrate 402. The semiconductor die 202 attach phase of manufacturing can process both sides of the manufacturing substrate 402 concurrently.
It is understood that the patterning of the contact layer 208 is an example only and the entire region beneath the semiconductor die can be removed. In the case that there is none of the contact layer 208 between the semiconductor die 202 and the detachable material 404, the adhesive 204 will only be applied to the space directly between the semiconductor die 202 and the detachable material 404.
Referring now to FIG. 6, therein is shown a cross-sectional view of a sub-assembly 600 of the integrated circuit packaging system 100 of FIG. 1 in an insulation layer 206 forming phase of manufacturing. The cross-sectional view of the sub-assembly 600 depicts the insulation layer 206 formed on the semiconductor die 202 and the contact layer 208. Via openings 602 can be formed in the insulation layer 206 for exposing the contact layer 208 and the semiconductor die contacts 216. Optionally the via opening 602 can also expose the insulated surface of the active side of the semiconductor die 202 separated from the semiconductor die contacts 216.
It is understood that the configuration of the sub-assembly 600 is built on both sides of the manufacturing substrate 402 at the same time. The detachable material 404 will subsequently allow the release of the finished package.
Referring now to FIG. 7, therein is shown a cross-sectional view of a sub-assembly 700 of the integrated circuit packaging system 100 of FIG. 1 in a conductor deposition phase of manufacturing. The cross-sectional view of the sub-assembly 700 depicts a conductive material 209, such as a metal, alloy, or conductive epoxy, applied on all of the surfaces that were exposed in the sub-assembly 600 of FIG. 6. The conductive material 209 can subsequently be patterned to form circuits for electrical connection to the semiconductor die 202 or through the base package 102 of FIG. 2.
The conductive material 209 can provide an electrically conductive path to the contact layer 208 and the semiconductor die contacts 216. Optionally the conductive material 209 can form the heat slug 214 on the insulated region of the active side of the semiconductor die 202. It is understood that the area of the active region of the semiconductor die 202 that is away from the semiconductor die contacts 216 will be coated by a polysilicon material to electrically insulate the circuits within the semiconductor die 202 from external electrical contact but is a good conductor of heat. The forming of the heat slug 214 directly on the area of the active region of the semiconductor die 202 that is away from the semiconductor die contacts 216 will provide a very efficient thermal management feature without adding additional components or processes.
Based on the intended use of the base package 102 the conductive material 209 can be used to fill the via opening 602 of FIG. 6 in order to form the filled vias 210 of FIG. 2 or just to coat the sidewalls of the via opening 602 in order to form the open vias 212 of FIG. 2. The solder resist layer 106 can be formed on the conductive material 209, the insulation layer 206 and the heat slug 214. The solder resist layer 106 can then be patterned to provide access sites 704 for electrical connection to the system interconnects 104 of FIG. 1. It is understood that the configuration of the sub-assembly 700 is built on both sides of the manufacturing substrate 402 at the same time. The detachable material 404 will subsequently allow the release of the finished package.
Referring now to FIG. 8, therein is shown a cross-sectional view of the embodiment of the base package 102 in a package separation phase of manufacturing. The cross-sectional view of the embodiment of the base package 102 depicts the base package 102 having been released from the manufacturing substrate 402 of FIG. 7 by activating the detachable material 404 of FIG. 7. The activation of the detachable material 404 can be the result of a change in temperature, being subject to ultra-sonic energy, being subject to ultra-violet light, or the like.
The features of the base package 102, including the semiconductor die 202 coupled to the system interconnects 104 by the open vias 212, can function as a stand-alone integrated circuit package and can be tested as such prior to additional assembly. The addition of the heat slug 214 can allow the base package 102 to integrate high power devices or large highly integrated versions of the semiconductor die 202. The inclusion of the contact layer 208 and the adhesive 204 can provide additional thermal management features as well as options for further electrical connections. The base package 102 can support electrical connections between the semiconductor die 202, the system interconnects 104, the contact layer 208 or a combination thereof. The contact layer 208 exposed on a coplanar surface of the base package 102 opposite the system interconnects 104 can provide for additional vertical integration of the first stacked integrated circuit 220 of FIG. 2, the discrete analog components 222 of FIG. 2, a flip chip integrated circuit 224 of FIG. 2, or a combination thereof.
Referring now to FIG. 9, therein is shown a cross-sectional view of a sub-assembly 900 of a third embodiment of the integrated circuit packaging system 100 of FIG. 1 in an insulation layer forming phase of manufacturing. The cross-sectional view of the third embodiment 900 depicts the manufacturing substrate 402 having the detachable material 404 on opposing surfaces.
A heat spreader 902 can optionally be attached to the detachable material 404. The heat spreader 902 can be a copper film, a plate, a sputtered metal layer, or a thermal epoxy. The semiconductor die 202 can be attached to the heat spreader 902 by the adhesive 204, such as a thermal interface material, a die attach material, or thermal epoxy. In the event the heat spreader 902 is not implemented, the adhesive 204 can be attached directly to the detachable material 404.
A stiffener 904 can be attached to the heat spreader 902 and completely surrounds the semiconductor die 202. The stiffener 904 can be formed from a metal sheet, preformed and cured thermal epoxy, preformed and cured epoxy molding compound, or a thermal crystal. The stiffener 904 can be attached to the heat spreader 902 by a die attach material. In the event the heat spreader 902 is not implemented, the stiffener 904 can be attached directly to the detachable material 404.
The insulation layer 206 can be formed on the heat spreader 902, the semiconductor die 202, the adhesive 204, and the stiffener 904. In the event the heat spreader 902 is not implemented, the insulation layer can be formed directly on the detachable material 404. The insulation layer 206 can be patterned to open channels 906 to expose the semiconductor die contacts 216 of the semiconductor die 202.
It has been discovered that the stiffener 904 can prevent the warping of a base package during the attachment to the next level system (not shown). The selection of the material of the stiffener 904 can provide additional thermal management for the semiconductor die 202 that generates excessive heat.
Referring now to FIG. 10, therein is shown a cross-sectional view of a sub-assembly 1000 of the third embodiment of the integrated circuit packaging system 100 in a contact forming phase of manufacturing. The cross-sectional view of a sub-assembly 1000 depicts the conductive layer 209 deposited on the insulation layer 206 and the semiconductor die contacts 216 of the semiconductor die 202. Optionally the conductive layer 209 can be deposited through an opening in the insulation layer 206 to contact the stiffener 904 for providing an additional thermal management feature.
The solder resist layer 106 can be deposited on the conductive layer 209 and the insulation layer 206. The solder resist layer 106 can then be patterned to provide the access sites 704 for electrical connection to the system interconnects 104 of FIG. 1. It is understood that the configuration of the sub-assembly 1000 is built on both sides of the manufacturing substrate 402 at the same time. The detachable material 404 will subsequently allow the release of the base package.
Referring now to FIG. 11, therein is shown a cross-sectional view of the third embodiment 1100 of the integrated circuit packaging system 100 in a package separation phase of manufacturing. The cross-sectional view of the third embodiment 1100 depicts a base package 1102 having the semiconductor die 202 physically and thermally coupled to the heat spreader 902 by the adhesive 204. The stiffener 904 can provide a rigid platform and prevents the warping of the base package 1102 during the reflow process of the system interconnects 104 during assembly.
It has been unexpectedly determined that the base package 1102 can provide an ultra-thin ball grid array package with thermal management features. The heat slug 214 of FIG. 2 can optionally be implemented in the area of the active region of the semiconductor die 202 that is away from the semiconductor die contacts 216 in order to provide a very efficient thermal management feature without adding additional components or processes. The optional combination the heat spreader 902, the stiffener 904, coupled to the system interconnects 104, and the heat slug 214 can provide extensive thermal management capable of supporting high power versions of the semiconductor die 202 in a high volume and reliable integrated circuit package.
Thus, it has been discovered that the integrated circuit packaging system and device or product of the embodiments of the present invention furnish important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for manufacturing high volume flexible and reliable multi chip integrated circuit packages with thermal management features.
Referring now to FIG. 12, therein is shown a cross-sectional view of a fourth embodiment 1200 of the integrated circuit packaging system 100 along the section line substantially similar to 2-2 of FIG. 1. The cross-sectional view of the fourth embodiment 1200 of the integrated circuit packaging system 100 includes the base package 102 having a top package 1202 mounted by package interconnects 1204, such as solder balls, solder posts, solder bumps, stud bumps, or the like in a fan-out configuration.
The top package 1202 can include a top substrate 1206 having the first stacked integrated circuit 220 and the second stacked integrated circuit 226. A top package body 1208 can be formed of a molding compound, such as an epoxy molding compound, to cover the first stacked integrated circuit 220, the second stacked integrated circuit 226, and the component interconnects 230. The component interconnects 230 can electrically connect the first stacked integrated circuit 220, the second stacked integrated circuit 226, and the semiconductor die 202 through the package interconnects 1204, contact layer 208, and the open vias 212.
Referring now to FIG. 13, therein is shown a cross-sectional view of a fifth embodiment 1300 of the integrated circuit packaging system 100 along the section line substantially similar to 2-2 of FIG. 1. The cross-sectional view of the fifth embodiment 1300 of the integrated circuit packaging system 100 includes the base package 102 having a top package 1302 mounted by package interconnects 1204, such as solder balls, solder posts, solder bumps, stud bumps, or the like in a fan-in configuration.
The top package 1302 can include the top substrate 1206 having the first stacked integrated circuit 220 and the second stacked integrated circuit 226. A top package body 1208 can be formed of a molding compound, such as an epoxy molding compound, to cover the first stacked integrated circuit 220, the second stacked integrated circuit 226, and the component interconnects 230. The component interconnects 230 can electrically connect the first stacked integrated circuit 220, the second stacked integrated circuit 226, and the semiconductor die 202 through the package interconnects 1204, contact layer 208, and the open vias 212.
Referring now to FIG. 14, therein is shown a cross-sectional view of a sixth embodiment 1400 of the integrated circuit packaging system 100 along the section line substantially similar to 2-2 of FIG. 1. The cross-sectional view of the sixth embodiment 1400 of the integrated circuit packaging system 100 includes the base package 102 having a top package 1402 mounted by package interconnects 1204, such as solder balls, solder posts, solder bumps, stud bumps, or the like in a fan-out configuration.
The top package 1402 can include the top substrate 1206 having the discrete analog components 222 and the flip chip integrated circuit 224 mounted thereon. The top package 1402 can be coupled to the base package 102 through the package interconnects 1204. It is understood that the top package 1402 can be implemented without the discrete analog components 222 without changing the embodiment of the invention. It is further understood that the top package 1402 can include the flip chip integrated circuit 224 having a different number of the component interconnects 230.
Referring now to FIG. 15, therein is shown a flow chart of a method 1500 of manufacture of an integrated circuit packaging system in a further embodiment of the present invention. The method 1500 includes: providing a semiconductor die having semiconductor die contacts in a block 1502; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed in a block 1504; applying a conductive layer on the semiconductor die contacts and the insulation layer in a block 1506; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects in a block 1508.
The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit packaging systems fully compatible with conventional manufacturing methods or processes and technologies.
Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims (20)

What is claimed is:
1. A method of manufacture of an integrated circuit packaging system comprising:
depositing an insulation layer on a semiconductor die having semiconductor die contacts, the semiconductor die contacts exposed;
applying a conductive layer on the semiconductor die contacts and the insulation layer, the applying including forming a heat slug directly on an active region of the semiconductor die, spaced away from the semiconductor die contacts; and
coupling system interconnects directly on the conductive layer for electrically connecting the semiconductor die, the system interconnects, a contact layer, or a combination thereof in a base package having an adhesive layer and the contact layer each having an exposed surface that is coplanar with a surface of the base package that is opposite to the system interconnects, the system interconnects coupled on the heat slugs.
2. The method as claimed in claim 1 further comprising forming a planar component surface over the semiconductor die.
3. The method as claimed in claim 1 wherein applying the conductive layer on the semiconductor die contacts and the insulation layer includes forming open vias on the insulation layer.
4. The method as claimed in claim 1 further comprising:
mounting a stacked integrated circuit over the semiconductor die;
coupling a component contact between the stacked integrated circuit and the conductive layer; and
forming a molded package body on the stacked integrated circuit, the component contact and the insulation layer.
5. The method as claimed in claim 1 further comprising:
adhering a heat spreader over the semiconductor die by the adhesive layer; and
mounting a stiffener, to the heat spreader, adjacent to the semiconductor die and the adhesive layer.
6. A method of manufacture of an integrated circuit packaging system comprising:
depositing an insulation layer on a semiconductor die having semiconductor die contacts, the semiconductor die contacts exposed;
patterning a conductive layer on the semiconductor die contacts and the insulation layer, the patterning including forming a heat slug directly on an active region of the semiconductor die, spaced away from the semiconductor die contacts;
applying a solder resist layer on the conductive layer and the insulation layer, the applying including forming access sites over the conductive layer; and
coupling system interconnects, through the access sites, directly on the conductive layer for electrically connecting the semiconductor die, the system interconnects, a contact layer, or a combination thereof in a base package having an adhesive layer and the contact layer each having an exposed surface that is coplanar with a surface of the base package that is opposite to the system interconnects, the system interconnects coupled on the heat slugs.
7. The method as claimed in claim 6 further comprising forming a planar component surface over the semiconductor die wherein forming the planar component surface includes mounting the contact layer, on the conductive layer, coplanar with the insulation layer.
8. The method as claimed in claim 6 wherein patterning the conductive layer on the semiconductor die contacts and the insulation layer includes forming filled vias, open vias, the heat slug, or a combination thereof on the insulation layer.
9. The method as claimed in claim 6 further comprising:
positioning the contact layer over the semiconductor die;
mounting a stacked integrated circuit, a flip chip integrated circuit, discrete analog components, or a combination thereof over the contact layer;
coupling a component contact between the stacked integrated circuit, the flip chip integrated circuit, the discrete analog components, or the combination thereof and the contact layer; and
forming a molded package body on the stacked integrated circuit, the flip chip integrated circuit, the discrete analog components, or the combination thereof, the component contact and the insulation layer.
10. The method as claimed in claim 6 further comprising:
adhering a heat spreader over the semiconductor die by the adhesive layer;
attaching a stiffener, to the heat spreader, adjacent to the semiconductor die and the adhesive layer; and
wherein:
depositing the insulation layer on the semiconductor die includes forming the insulation layer on the heat spreader, the stiffener, and the adhesive layer.
11. An integrated circuit packaging system comprising:
a semiconductor die having semiconductor die contacts;
an insulation layer on the semiconductor die, the semiconductor die contacts exposed from the insulation layer;
a conductive layer on the semiconductor die contacts and the insulation layer, a heat slug formed directly on an active region of the semiconductor die, spaced away from the semiconductor die contacts; and
system interconnects coupled directly on the conductive layer for electrically connecting the semiconductor die, the system interconnects, a contact layer, or a combination thereof in a base package having an adhesive layer and the contact layer each having an exposed surface that is coplanar with a surface of the base package that is opposite to the system interconnects, the system interconnects coupled on the heat slugs.
12. The system as claimed in claim 11 further comprising a planar component surface formed over the semiconductor die.
13. The system as claimed in claim 11 wherein the conductive layer on the semiconductor die contacts and the insulation layer includes open vias formed on the insulation layer.
14. The system as claimed in claim 11 further comprising:
a stacked integrated circuit mounted over the semiconductor die;
a component contact coupled between the stacked integrated circuit and the conductive layer; and
a molded package body formed on the stacked integrated circuit, the component contact and the insulation layer.
15. The system as claimed in claim 11 further comprising:
a heat spreader adhered over the semiconductor die by the adhesive layer; and
a stiffener, mounted to the heat spreader, adjacent to the semiconductor die and the adhesive layer.
16. The system as claimed in claim 11 further comprising a solder resist layer applied on the conductive layer and the insulation layer including access sites, in the solder resist layer, over the conductive layer.
17. The system as claimed in claim 16 further comprising a planar component surface over the semiconductor die wherein the planar component surface includes the contact layer, on the conductive layer, coplanar with the insulation layer.
18. The system as claimed in claim 16 wherein the conductive layer on the semiconductor die contacts and the insulation layer includes filled vias, open vias, the heat slug, or a combination thereof formed on the insulation layer.
19. The system as claimed in claim 16 further comprising:
the contact layer over the semiconductor die;
a stacked integrated circuit, a flip chip integrated circuit, discrete analog components, or a combination thereof over the contact layer;
a component contact between the stacked integrated circuit, the flip chip integrated circuit, the discrete analog components, or the combination thereof and the contact layer; and
a molded package body on the stacked integrated circuit, the flip chip integrated circuit, the discrete analog components, or the combination thereof, the component contact, the contact layer, and the insulation layer.
20. The system as claimed in claim 16 further comprising:
a heat spreader over the semiconductor die adhered by the adhesive layer;
a stiffener, attached to the heat spreader, adjacent to the semiconductor die and the adhesive layer; and
wherein:
the insulation layer on the semiconductor die includes the insulation layer on the heat spreader, the stiffener, and the adhesive layer.
US14/226,711 2014-03-26 2014-03-26 Integrated circuit packaging system with coreless substrate and method of manufacture thereof Active 2034-05-03 US9673171B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/226,711 US9673171B1 (en) 2014-03-26 2014-03-26 Integrated circuit packaging system with coreless substrate and method of manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/226,711 US9673171B1 (en) 2014-03-26 2014-03-26 Integrated circuit packaging system with coreless substrate and method of manufacture thereof

Publications (1)

Publication Number Publication Date
US9673171B1 true US9673171B1 (en) 2017-06-06

Family

ID=58776450

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/226,711 Active 2034-05-03 US9673171B1 (en) 2014-03-26 2014-03-26 Integrated circuit packaging system with coreless substrate and method of manufacture thereof

Country Status (1)

Country Link
US (1) US9673171B1 (en)

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020127780A1 (en) * 2000-10-18 2002-09-12 Qing Ma Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US20030112604A1 (en) * 2001-12-18 2003-06-19 Chi-Hsing Hsu Multi-chip package with embedded cooling element
US20050248029A1 (en) 2004-05-10 2005-11-10 Roger Chang Embedded chip semiconductor without wire bondings
US20060115931A1 (en) * 2004-11-26 2006-06-01 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded chip and fabrication method thereof
US7078788B2 (en) 2000-08-16 2006-07-18 Intel Corporation Microelectronic substrates with integrated devices
US7312536B2 (en) 2004-10-22 2007-12-25 Shinko Electric Industries Co., Ltd. Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same
US7320173B2 (en) 2003-02-06 2008-01-22 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7563987B2 (en) 2004-03-29 2009-07-21 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US7573135B2 (en) 2003-01-23 2009-08-11 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film
US20100255673A1 (en) * 2004-12-13 2010-10-07 Renesas Technology Corp. Semiconductor device having elastic solder bump to prevent disconnection
US20110063805A1 (en) * 2007-08-31 2011-03-17 Samsung Electronics Co., Ltd. Stack-type semiconductor package, method of forming the same and electronic system including the same
US20110084382A1 (en) * 2009-10-07 2011-04-14 Wei-Ming Chen Chip package and fabrication method thereof
US20110193225A1 (en) * 2010-02-10 2011-08-11 Wei-Ming Chen Electronic device package and fabrication method thereof
US20110215464A1 (en) * 2009-12-29 2011-09-08 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US20120038053A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers
US20120104581A1 (en) * 2010-11-02 2012-05-03 Global Unichip Corporation Semiconductor package device with a heat dissipation structure and the packaging method thereof
US8335084B2 (en) 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US20130026632A1 (en) * 2010-04-08 2013-01-31 Nec Corporation Semiconductor element-embedded wiring substrate
US20140008814A1 (en) 2012-07-05 2014-01-09 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078788B2 (en) 2000-08-16 2006-07-18 Intel Corporation Microelectronic substrates with integrated devices
US20020127780A1 (en) * 2000-10-18 2002-09-12 Qing Ma Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US20030112604A1 (en) * 2001-12-18 2003-06-19 Chi-Hsing Hsu Multi-chip package with embedded cooling element
US7573135B2 (en) 2003-01-23 2009-08-11 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film
US7320173B2 (en) 2003-02-06 2008-01-22 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7563987B2 (en) 2004-03-29 2009-07-21 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US20050248029A1 (en) 2004-05-10 2005-11-10 Roger Chang Embedded chip semiconductor without wire bondings
US7312536B2 (en) 2004-10-22 2007-12-25 Shinko Electric Industries Co., Ltd. Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same
US20060115931A1 (en) * 2004-11-26 2006-06-01 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded chip and fabrication method thereof
US7449363B2 (en) 2004-11-26 2008-11-11 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded chip and fabrication method thereof
US20100255673A1 (en) * 2004-12-13 2010-10-07 Renesas Technology Corp. Semiconductor device having elastic solder bump to prevent disconnection
US8335084B2 (en) 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US20110063805A1 (en) * 2007-08-31 2011-03-17 Samsung Electronics Co., Ltd. Stack-type semiconductor package, method of forming the same and electronic system including the same
US20110084382A1 (en) * 2009-10-07 2011-04-14 Wei-Ming Chen Chip package and fabrication method thereof
US8227927B2 (en) 2009-10-07 2012-07-24 Wei-Ming Chen Chip package and fabrication method thereof
US20110215464A1 (en) * 2009-12-29 2011-09-08 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US20110193225A1 (en) * 2010-02-10 2011-08-11 Wei-Ming Chen Electronic device package and fabrication method thereof
US20130026632A1 (en) * 2010-04-08 2013-01-31 Nec Corporation Semiconductor element-embedded wiring substrate
US20120038053A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers
US20120104581A1 (en) * 2010-11-02 2012-05-03 Global Unichip Corporation Semiconductor package device with a heat dissipation structure and the packaging method thereof
US20140008814A1 (en) 2012-07-05 2014-01-09 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing

Similar Documents

Publication Publication Date Title
US11145603B2 (en) Integrated circuit packaging system with shielding and method of manufacture thereof
US9202715B2 (en) Integrated circuit packaging system with connection structure and method of manufacture thereof
KR101634067B1 (en) Semiconductor package and method of manufacturing the same
US7501697B2 (en) Integrated circuit package system
US8487426B2 (en) Semiconductor package with embedded die and manufacturing methods thereof
EP2551904A1 (en) Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof
US9349666B1 (en) Integrated circuit packaging system with package stacking
US8125092B2 (en) Semiconductor device packages and assemblies
TW201041103A (en) Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
US8367473B2 (en) Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US20090243069A1 (en) Integrated circuit package system with redistribution
US20120086117A1 (en) Package with embedded chip and method of fabricating the same
US9202742B1 (en) Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof
SG185201A1 (en) Integrated circuit packaging system withrouted circuit lead array and method ofmanufacture thereof
KR100910233B1 (en) Stacked wafer level package
US9299650B1 (en) Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
US9693455B1 (en) Integrated circuit packaging system with plated copper posts and method of manufacture thereof
US9054098B2 (en) Integrated circuit packaging system with redistribution layer and method of manufacture thereof
US20130249073A1 (en) Integrated circuit packaging system with support structure and method of manufacture thereof
US9305809B1 (en) Integrated circuit packaging system with coreless substrate and method of manufacture thereof
US10784224B2 (en) Semiconductor devices with underfill control features, and associated systems and methods
US8134227B2 (en) Stacked integrated circuit package system with conductive spacer
EP2613349B1 (en) Semiconductor package with improved thermal properties
US9673171B1 (en) Integrated circuit packaging system with coreless substrate and method of manufacture thereof
US9147662B1 (en) Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: STATS CHIPPAC LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHI, HEEJO;LEE, HEESOO;KWON, OMIN;REEL/FRAME:032541/0661

Effective date: 20140326

AS Assignment

Owner name: STATS CHIPPAC PTE. LTD., SINGAPORE

Free format text: CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LTD.;REEL/FRAME:039439/0430

Effective date: 20160329

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4