CN103270586B - 具有含多个垂直嵌入管芯的衬底的多芯片封装以及形成所述封装的工艺 - Google Patents
具有含多个垂直嵌入管芯的衬底的多芯片封装以及形成所述封装的工艺 Download PDFInfo
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- CN103270586B CN103270586B CN201180062444.2A CN201180062444A CN103270586B CN 103270586 B CN103270586 B CN 103270586B CN 201180062444 A CN201180062444 A CN 201180062444A CN 103270586 B CN103270586 B CN 103270586B
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Abstract
一种包括衬底的装置,所述衬底具有含多个触点焊盘的焊接区侧以及与焊接区层相对的管芯侧。所述装置包括第一管芯和第二管芯,其中第一管芯和第二管芯嵌入衬底内,使得第二管芯位于第一管芯与衬底的焊接区侧之间。
Description
技术领域
公开的实施例涉及半导体微电子封装以及形成方法。
背景技术
当前的消费电子产品市场经常要求需要极为复杂电路的综合功能。对例如晶体管之类的越来越小的基本结构单元的缩放已经在实现了单个管芯上的更复杂电路与前进的每一代的结合。另一方面,尽管通常将缩放视为减小尺寸,但为了计算系统中的高级功能和功率,越来越多地将多个封装管芯耦合到一起。此外,实际上可以增大特定半导体封装的尺寸,以便在单个半导体封装内包括多个管芯。
然而,在尝试耦合多个封装管芯的时候可能引起结构问题。例如,用于半导体封装中的部件之间的热膨胀系数(CTE)的差异的影响在将封装管芯添加到一起时可能导致有害的缺陷。类似地,作为执行用于单个封装内多于一个管芯的半导体管芯封装工艺的结果,用于单个半导体封装内的部件之间的热膨胀系数(CTE)的差异的影响能够导致有害的缺陷。
半导体封装用于保护集成电路(IC)芯片或管芯,并且还为管芯提供至外部电路的电气接口。随着对较小的电子器件的需求不断增大,半导体封装被设计为更紧凑并且必须支持更大的电路密度。例如,现在一些半导体封装使用无核衬底。此外,对较高性能器件的要求导致了对改善的半导体封装的需要,所述改善的半导体封装实现了混合工艺管芯堆叠或者提供了封装堆叠能力,同时保持了薄的封装轮廓和低的整体翘曲,以与随后的组装工艺兼容。
附图说明
为了理解获得实施例的方式,将通过参考附图来表现以下简要描述的多个实施例的更具体说明。这些附图描绘了实施例,所述实施例不一定是按照比例绘制的并且也不应认为在范围中受到限制。通过使用附图,将借助额外的特征和细节来说明和解释一些实施例,在附图中:
图1A和1B示出了根据本发明实施例的具有嵌入衬底并垂直设置于其中的多个管芯的多芯片封装(MCP)。
图2A-2L示出了根据本发明实施例的形成具有嵌入衬底并垂直设置于其中的多个管芯的多芯片封装(MCP)的方法。
图3显示了根据本发明实施例的计算机系统。
图4示出了根据本发明实施例的具有嵌入衬底并垂直设置于其中的多于两个管芯的多芯片封装。
图5示出了根据本发明另一实施例的具有嵌入衬底并垂直设置于其中的两个管芯的多芯片封装。
具体实施方式
描述了具有多个垂直嵌入管芯的多芯片封装(MCP)及其制造方法。现在将参考附图,其中对于相似的结构提供相似后缀的附图标记。为了更清楚地示出多个实施例的结构,本文所包括的附图是集成电路结构的图解表示。因此,例如在显微照片中的制造的集成电路结构的实际外观可能显得有所不同,但仍包含所示实施例所要求的结构。此外,附图可以仅显示用于理解所示实施例有用的结构。可以不包括本领域中已知的其它结构,以保持附图的清楚。另外,在本说明书中,阐述了多个特定细节,以便提供对本发明实施例的透彻的理解。在其他情况下,没有具体详细阐述公知的半导体处理和封装技术,以避免不必要地混淆本发明的实施例。
本发明的实施例包括具有衬底的多芯片封装,所述衬底具有嵌入其中的多个垂直设置的管芯。衬底包括焊接区侧和管芯侧。将第一管芯和第二管芯嵌入衬底内,使得第二管芯位于第一管芯与衬底的焊接区侧之间。封装衬底包括多个布线层、绝缘层和过孔,以用于在衬底内生成互连结构,所述互连结构提供了在第一管芯与第二管芯之间的电连接。在本发明的实施例中,至少一个布线层位于第一管芯与第二管芯之间。可以用无凸起内建层(BBUL)工艺来形成根据本发明实施例的具有含垂直设置并嵌入其中的管芯的衬底的多芯片封装。在本发明的实施例中,第一管芯附着至临时载体,在第一管芯上构造绝缘层和布线层,并所述绝缘层和布线层围绕第一管芯将第一管芯嵌入其中。第二管芯随后附着至绝缘层与附加绝缘层中的一个,围绕第二管芯构造布线层,从而也将第二管芯嵌入衬底内。通过这种方式,第一和第二管芯都嵌入衬底,并在衬底内形成电互连(衬底布线),其电耦合第一和第二管芯。随后可以去除载体以生成无核衬底。
本发明的实施例实现了多芯片封装的形成,所述多芯片封装具有薄的封装结构和小的覆盖区,从而节省了器件母板上宝贵的空间。另外,本发明的实施例在不使用层叠封装(POP)技术的情况下实现了两个管芯的电互连,所述层叠封装(POP)技术需要表面安装技术(SMT),所述表面安装技术(SMT)容易受到由于衬底翘曲导致的可靠性问题的影响。另外,在本发明的实施例中,低温无凸起内建层(BBUL)工艺用于形成衬底,以便减小或消除所嵌入的管芯与衬底之间的热膨胀系数(CTE)不匹配的影响,从而能够制造极为平坦的多芯片封装。
图1A是具有衬底102的半导体封装100的横截面的图示,所述衬底102具有含嵌入其中的多个垂直设置的管芯。在本发明的实施例中,衬底102是无核衬底。衬底102具有管芯侧120和与管芯侧相对的焊接区侧122。封装100包含第一管芯104和第二管芯106。第一管芯104具有有源面108和与有源面108相对的背面110。类似地,第二管芯106具有有源面112和与有源面112相对的背面114。可以由任何公知的半导体材料来形成第一管芯和第二管芯,所述公知的半导体材料例如但不限于硅(Si)、锗化硅(SiGe)、锗(Ge)以及任何III-V族半导体,例如砷化镓(GaAs)和锑化铟(InSb)。有源面108和112包括多个半导体器件,例如但不限于晶体管、电容器和电阻器,通过管芯互连结构将其一起互连到功能电路中,从而形成集成电路。如本领域中公知的,管芯互连结构可以包任意数量的多金属化层,例如M1-M11,其数量和厚度可以根据给定应用用途而变化。第一级金属化层(M1)与有源面的半导体器件接触,而最后级的金属化层(例如,M11)包括连接至外界的电触点。第一管芯104被示出为具有电触点116,第二管芯被示出为具有电触点118。在本发明的实施例中,第一管芯104的有源面108和第二管芯106的有源面112朝向形成于衬底102上的多个外部导电触点140,或者与其面向相同方向,如图1A所示。也就是说,第一管芯104和第二管芯106以“朝下”配置设置在衬底102中。
第一管芯104具有第一覆盖区或表面积105,第二管芯106具有第二覆盖区或表面积107。在本发明的实施例中,第一管芯104的覆盖区比第二管芯106的覆盖区大。第二管芯106嵌入到衬底102内,并且位于第一管芯104与衬底102的焊接区侧122之间。通过这种方式,第一管芯104与第二管芯106垂直设置在衬底102内。在本发明的实施例中,第二管芯106的覆盖区107的至少一部分位于第一管芯104的覆盖区105内。在一个实施例中,如图1A所示,第二管芯106的整个覆盖区107都位于第一管芯104的覆盖区105内。在本发明的实施例中,第一管芯104是存储器件,例如但不限于静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、非易失性存储器(NVM),第二管芯106是逻辑器件,例如但不限于微处理器和数字信号处理器。
焊接区侧122包括多个导电触点焊盘和/或布线迹线,多个外部导电触点140连接至所述多个导电触点焊盘和/或布线迹线。外部导电触点140提供封装100至其他器件的电连接。衬底102包括多个布线层、绝缘层和过孔,它们共同生成衬底互连结构。衬底互连结构提供了第一管芯104与第二管芯106之间的电连接,并且还提供了第一与第二管芯至形成于焊接侧122上的外部电触点140的电连接。
衬底互连结构提供了第一管芯104至第二管芯106的直接电连接,使得可以直接在第一管芯和第二管芯之间传递信号。衬底互连结构还可以包括第二管芯106与外部导电触点140之间的电连接。在本发明的一些实施例中,衬底互连结构还提供第一管芯104与外部电触点140之间的电连接。在其他实施例中,在外部导电触点140与第一管芯104之间没有电连接。也就是说,在本发明的实施例中,至第一管芯104的所有外部连接都通过第二管芯106。在特定实施例中,除了电源和接地信号以外,至第一管芯104的所有电信号都由第二管芯106提供。
在本发明的实施例中,如图1A所示,衬底102包括第一绝缘层130。第一管芯104嵌入到第一绝缘层130内。也就是说,第一管芯的有源面108和侧壁101与绝缘层130接触。包括多条导电迹线的第一布线层150设置在第一绝缘层130上。多个导电过孔160位于第一绝缘层130中,并且将第一布线层150的导电迹线电连接至第一管芯104的电触点116。第一布线层150中的一条或多条导电迹线151将信号从第一管芯104的覆盖区105向衬底102的边缘传送出去。第二绝缘层132设置在第一绝缘层130上并且在第一布线层150上,如图1A所示。第一布线层150嵌入到第一绝缘层130与第二绝缘层132之间。第二管芯106的背面114设置在第二绝缘层132上。第三绝缘层134设置在第二绝缘层132上,并且在第二管芯106上及周围,如图1A所示。第二管芯106嵌入到第三绝缘层134内,并且完全封闭和嵌入到第二绝缘层132与第三绝缘层134之间。
包括多条导电迹线的第二布线层152设置在第三绝缘层134上。在本发明的实施例中,第二布线层152的一条或多条导电迹线153将信号从衬底102的边缘发送至第二管芯106的覆盖区107内,以提供至第二管芯106的电连接。在第二布线层152的导电迹线与第二管芯106的电触点118之间的第三绝缘层134中形成多个导电过孔162,以将第二布线层152的迹线电连接至第二管芯上的电触点118。另外,穿过第二绝缘层132和第三绝缘层134形成多个导电过孔164,以将第二布线层152的迹线电连接至第一布线层150的迹线,如图1A所示。
在本发明的实施例中,导电过孔164的直径大于导电过孔162的直径。应该理解,导电过孔164比导电过孔162更深地延伸到衬底中。在本发明的实施例中,过孔164具有100-150μm之间的直径,而过孔162具有30-50μm之间的直径。因此,通过增大导电过孔164的直径,减小了导电过孔164的纵横比(高度:宽度),实现了导电过孔的可靠填充。应该理解,尽管将过孔164示出为由导电膜完全填充,但可以以如下方式形成过孔164:仅有过孔164的侧壁具有形成于其中的导电膜,而中心保持未填充。随后绝缘层的形成可以用于填充过孔的未填充体积。例如参见图2J。
第四绝缘层136设置在第三绝缘层134上,并且在第二布线层152的迹线上及周围。在本发明的实施例中,仅提供两个布线层150和152,一个布线层(150)用于提供导电迹线,以将信号从第一管芯104的覆盖区105发送出去,一个布线层152用于提供导电迹线,以将信号发送至第二管芯106的覆盖区107内。如果布线层152是衬底的最后布线层,就可以在第四绝缘层136中形成多个键合焊盘开口,以定义第二布线层的迹线153上的键合焊盘,随后于此形成外部电触点140。
然而,如果想要的话,可以根据特定布线需求而包括额外的布线层、绝缘层和过孔。例如,包括多条导电迹线的第三布线层154可以设置在第四绝缘层136上。可以穿过第四绝缘层136形成多个导电过孔166,以提供第二布线层152的导电迹线与第三布线层154的导电迹线之间的电连接。可以在第四绝缘层136上和第三布线层154的导电迹线上及其周围形成第五绝缘层138。
再进一步地,第四布线层156可以设置在第五绝缘层138上。如果第四布线层156是最后的布线层,它就可以包括多个布线层/导电触点焊盘157,电触点140耦合至所述多个布线层/导电触点焊盘157。第四布线层156还可以包括布线迹线157,以重新分布触点焊盘的位置。穿过第五布线层138形成多个过孔168,以将第四布线层156的迹线/触点焊盘电耦合到第三布线层154的迹线。诸如焊料掩模层的最后的第六绝缘层139可以形成于第五绝缘层138上,并且在第四布线层156上及其周围。在焊料掩模层139中形成开口,以使得外部电触点140能够附着至布线层156的触点焊盘。
在本发明的实施例中,封装100可以包括管芯附着膜(DAF)124,例如附着至第一管芯104的背面110的环氧基管芯键合膜(DBF)。在其它实施例中,去除管芯附着膜(DAF)124,以使得能够接触第一管芯104的背面110。不认为DAF124是衬底102的部分。另外,在本发明的实施例中,衬底102可以是无核衬底,因为它由内建层工艺形成于载体上,其中最终从衬底102去除了载体。再进一步地,可以将衬底102认为是无核衬底,因为它不包括诸如纤维增强玻璃环氧树脂的厚的核。
如图1A所示,衬底102包括至少一个布线层150,其位于第一管芯104与第二管芯106之间。另外,在本发明的实施例中,衬底102包括至少一条导电迹线,例如导电迹线151,其具有位于第一管芯104的覆盖区105与第二管芯106的覆盖区107之间的一部分,以及延伸至第二管芯106的覆盖区107外的一部分。另外,尽管图1A中仅示出了形成于第一管芯104与第二管芯106之间的单个布线层132,但本领域普通技术人员应该意识到,两个或更多个布线层可以位于第一管芯104与第二管芯106之间。另外,尽管示出了三个布线层形成于外部触点140与第二管芯106之间,但应该理解,这仅是本发明实施例的举例说明,取决于必要的布线需求,在第二管芯106与外部触点140之间可以形成更多或更少的布线层。
在本发明的实施例中,外部导电触点140是以阵列方式布置的焊球,以提供球栅阵列。然而,外部导电触点140不是必须采取球的形式,可以具有其它形状或结构,例如但不限于柱、凸起、焊盘和管脚。外部触点140实现了半导体封装100至基础衬底170的电连接和通信。例如,当半导体封装100是计算机或诸如智能电话或手持阅读器的手持设备的一部分时,基础衬底170是母板。在其它实施例中,基础衬底170可以是另一半导体封装,以便生产层叠封装(POP)器件。
图1B是图1A中所示封装衬底100的图示,进一步描绘了可以包括在根据本发明实施例的衬底102中的特定电连接。在本发明的实施例中,衬底102包括至少一个电连接182,其提供第一管芯104与第二管芯106之间的直接电连接,其中电连接182没有电连接至外部触点140。这种连接对于仅在第一管芯104与第二管芯106之间传送的信号是有用的。例如,当第一管芯104是存储器件并且第二管芯106是逻辑器件时,可以通过诸如电连接182的直接电连接在第一管芯104与半导体管芯106之间传递诸如地址信号、数据信号、写使能信号和读使能信号的信号。另外,在本发明的实施例中,封装衬底102可以包括一个或多个电连接184,其将第一管芯104和第二管芯106二者电连接至外部导电触点140。通过这种方式,将通过电触点140提供给封装100的信号提供给第一管芯和第二管芯二者。这种信号的示例可以是电源信号和接地信号,例如VCC和VSS。在本发明的另一实施例中,封装衬底102包括一个或多个电连接186,其在不将信号直接提供给第一管芯104的情况下,提供在外部触点140与第二管芯106之间的直接电连接。例如,当第二管芯106是诸如微处理器的逻辑器件时,可以由多个电连接186将指令仅提供给第二管芯106。另外,尽管图1B中未示出,但衬底102可以提供在第一管芯104与外部电触点140之间的一个或多个电连接,以便能够将信号直接提供至第一管芯104而不提供至第二管芯106。本发明的实施例包括封装衬底102,其可以包含上述的全部或部分电连接,例如电连接182、184和186。
具有含多个垂直嵌入管芯的衬底的半导体封装100包括完全嵌入并包围的第二管芯106。本公开中使用的“完全嵌入并包围的”意味着第二管芯106的所有表面都与衬底102的绝缘膜接触。半导体封装100还包括完全嵌入的第一管芯104。本公开中使用的“完全嵌入的”意味着第一管芯104的有源面108和整个侧壁都与衬底102的绝缘膜接触。然而,第一管芯104没有“被包围”,因为第一管芯104的背面110没有与衬底102的绝缘膜接触。本文描述了第一管芯104的“完全嵌入的”两个实施例。在第一实施例中,如图1A所示,有第一管芯的一个表面(例如,背面110)从衬底102的管芯侧的整体平坦表面突出,例如图1A中所示的从衬底102的表面109突出。在实施例中,没有第一管芯104的表面从衬底102的管芯从的整体平坦表面突出,例如不从衬底102的表面109突出。
与以上定义的“完全嵌入并包围的”和“完全嵌入的”形成对照,“部分嵌入的”管芯是具有整个表面但仅有一部分侧壁与衬底102的绝缘膜接触的管芯。进一步相对照地,“非嵌入的”管芯是有最多一个表面且没有侧壁的一部分与衬底的封装膜接触。
图2A-2L示出了根据本发明实施例的制造具有嵌入衬底内的多个管芯的半导体封装的方法。提供载体201。载体201具有蚀刻停止层202。可以蚀刻诸如铜箔的第二层206,以在管芯安装表面204周围生成凹陷或空腔205。在本发明的实施例中,载体201不包括第二层206,以至于在载体201中没有形成凹陷或空腔。
图2B示出了根据本发明实施例的在具有嵌入衬底内的多个管芯的封装的制造的进一步处理期间的截面图。在处理期间,可以使载体201与相同的结构201’配对,以便构造用于处理用途的背对背载体210。结果,有效地使处理生产量加倍。在对载体201和201’的处理的描述可以由对载体201的处理所划的附图标记来指代,但应该理解,在载体201’上复制相同的处理和结构。载体210包括附着释放层212、212’和粘合剂214。在载体210的每一个末端处提供切割区216,以用于如进一步示出的分离处理。背对背载体210可以形成更大面板的一部分,所述更大面板具有多个相同的区域,它们具有背对背载体210的横截面,以实现批量处理。在实施例中,该面板具有大约1000个管芯放置于此的空腔205。
图2C是根据本发明实施例的在进一步处理后的图2B所示的背对背载体210的截面图。通过将第一管芯222放置在蚀刻停止层204上来进一步处理背对背载体210。第一管芯222具有与背面226相对的有源面224。有源面224包括多个触点焊盘225,以用于构成到第一管芯222的电接触。第一管芯222具有第一覆盖区229。在实施例中,第一管芯222的背面226利用诸如环氧树脂基材料或管芯键合膜(DBF)的附着层228附着至蚀刻停止层202。在本发明的实施例中,将要嵌入衬底内的两个管芯中具有较大覆盖区的管芯是所附着的第一管芯(即,是第一管芯222)。附着较大的管芯提供了与载体201较大的表面积接触,这有助于在构建处理中避免翘曲并保持平面性。在可替换实施例中,两个管芯中较小的一个管芯是第一管芯。图2C还示出了第一管芯222’添加到载体201’上,以生成装置220。
图2D是根据本发明实施例的在进一步处理后的装置220的截面图。已经处理装置220以接收第一绝缘膜232。在本发明的实施例中,通过将绝缘膜层压到载体201和第一管芯222上来形成第一绝缘膜232。在将膜层压到载体210和第一管芯222上之后,使其在适合温度固化,例如在约180℃处固化。在本发明的实施例中,第一绝缘膜232是Ajinomoto构建膜(ABF)。在本发明的实施例中,当载体201包括形成空腔205和蚀刻停止层202的第二层206时,第一绝缘层232被形成与第二绝缘层和蚀刻停止层直接接触。绝缘层232形成于第一管芯222的有源面224以及侧壁223上并与其直接接触。通过这种方式,管芯222嵌入到绝缘层232内。作为层压的替换,可以通过旋涂并固化绝缘膜来形成绝缘层232。类似地,可以在管芯222’上及周围形成第一绝缘膜232’,以产生图2D所示的装置230。
图2E是根据本发明实施例的在进一步处理后的图2D所示装置230的图示。穿过第一绝缘层232形成多个过孔242,以露出第一管芯222的电触点225。在本发明的实施例中,通过激光钻孔来形成过孔242。可以使用二氧化碳(CO2)气体激光束、紫外线(UV)激光束或准分子激光束来完成激光钻孔。在本发明的实施例中,形成具有30-50微米之间的直径的过孔开口242。与现有技术的钻孔工艺相比,根据实施例的激光钻孔允许更高的连接密度,以实现小的过孔尺寸和间距,并通过这种方式以低成本导致了改善的设计和可缩放的小型化。另外,激光钻孔实现了高对准精度(例如,10到15微米)和生产量(约2000个过孔/秒),以及各种可能的过孔尺寸(诸如在30微米到约300微米之间)和低成本(每1000个过孔约2分)。高对准精度和小过孔尺寸的组合使得低至60微米的过孔间距成为可能,这些间距比用于含核的封装上使用的约400微米的典型镀通孔间距小得多。在绝缘层232’中类似地形成过孔开口242’,以提供如图2E所示的装置240。
图2F是根据本发明实施例的在进一步处理后的图2E所示装置240的图示。如图2F所示,以诸如铜的导电材料填充过孔开口242,以形成多个导电过孔252,其电连接至第一管芯222的触点焊盘225。另外,在第一绝缘层232上形成包括诸如铜迹线的多条导电迹线256的第一布线层254,其与导电过孔252接触,如图2F所示。在本发明的实施例中,形成至少一条导电迹线256,其电耦合到触点225并且朝向衬底的边缘延伸至第一管芯222的覆盖区229之外。
在本发明的实施例中,利用半加成处理(SAP),在形成第一布线层254的导电迹线256同时填充过孔242以形成导电过孔252。在半加成处理中,在绝缘层232的表面之上以及过孔开口242中以及过孔开口242的侧壁上形成诸如无镀覆铜种子层的无镀覆种子层,具有例如小于1微米的厚度。随后在无镀覆种子层上沉积光致抗蚀剂层,暴露于光并显影,从而形成抗蚀图,留下对应于希望获得导电迹线256的图案的未遮蔽区域。随后通过例如利用作为种子层的无镀覆铜镀覆膜的铜层的电解电镀形成导电迹线256和导电过孔252。继续进行电镀,直至完全填充过孔252并形成达到预期厚度的第一导电迹线256,例如2-20微米。随后去除光致抗蚀剂掩模,并将快速接触蚀刻用于去除剩余的种子层。
上述SAP工艺可以用于填充过孔并在小于100℃的温度并且通常在50-80℃之间,形成导电迹线。使用半加成方案实现了形成具有精细线和间隔特征的薄导电迹线,例如小于30微米的线和空间特征。利用半加成处理(SAP)填充过孔252并形成第一布线层254允许在不使用高温处理的情况下将第一管芯222电连接至封装衬底,高温处理例如是热压键合或使用无铅焊料的表面贴装技术,其通常在诸如使用倒装芯片键合和引线键合的其他封装技术中用于将管芯电连接至封装衬底。通过使用诸如在小于100℃处理的低温处理将第一管芯222电连接至衬底,衬底和管芯没有受到高温,由于第一管芯222与装置240的层之间的CTE不匹配,高温会导致封装翘曲。类似的处理可以用于形成导电过孔252’和布线层254’,以提供如图2F所示的装置250。
图2G示出了根据本发明实施例的在进一步处理后的图2F的装置250。进一步处理装置250以包括第二绝缘层261和第二管芯262,其具有有源面264和相对的背面266。第二管芯262的有源面264包括多个电触点265,用于提供到第二管芯262的电连接。第二绝缘层261形成于第一布线层254的迹线256之上以及第一绝缘层232上,如图2F所示。第二管芯262的背面266附着至第二绝缘层261。
在本发明的实施例中,利用第二绝缘层261的胶粘性将第二管芯262的背面266附着至第二绝缘层261。例如,在本发明的实施例中,将诸如ABF的绝缘膜层压到布线层254和第一绝缘层之上,随后在例如70℃的温度仅部分固化绝缘膜,以保留绝缘膜的胶粘性。随后借助固定第二管芯262的部分固化的绝缘膜的胶粘性将第二管芯262放置到部分固化的绝缘膜上。在固定第二管芯262后,可以例如通过加热到约180℃的温度来完全固化部分固化的绝缘层,以形成第二绝缘层261。通过这种方式,无需粘合剂或管芯附着膜来将第二管芯262固定到第二绝缘层261。管芯附着膜的去除减小了附着的第二管芯的高度,从而有助于减小第二管芯262的外形,并实现了更为平坦地形成随后的构建层。
在实施例中,设置第二管芯262使得第二管芯262的覆盖区269的至少一部分位于第一管芯222的覆盖区229内。在本发明的实施例中,第二管芯262具有覆盖区269,其小于第一管芯222的覆盖区269,第二管芯262位于绝缘层261上,使得第二管芯262的整个覆盖区269都位于第一管芯222的覆盖区229内,如图2G所示。在本发明的实施例中,第二管芯262是逻辑器件,例如由Intel公司制造的微处理器或数字信号处理器。
接下来,如图2G所示,在第二绝缘层261和第二管芯262的有源面264上形成第三绝缘层268。第二管芯完全嵌入到第三绝缘层268和第二绝缘层261中,并由其围绕,如图2G所示。在本发明的实施例中,通过将绝缘膜层压到第二绝缘膜261和第二管芯262上,并如上所述地固化层压的膜来形成第三绝缘层268。在本发明的实施例中,第二管芯262是薄的管芯,例如减薄到具有50-150微米之间的厚度的管芯。提供薄的管芯262是有益的,使得不必为了完全密封第二管芯262而将绝缘层268形成得过厚。在实施例中,将第三绝缘层268形成为比第二管芯的厚度要厚大约20-30微米的厚度,以便提供第二管芯与随后形成的布线层的充分隔离。应该理解,如果第二管芯262过厚,那么第三绝缘层268就必须形成得较厚,使得难以构造到第一布线层254的导电迹线256的可靠过孔连接。可以将第二管芯262’类似地安装到形成于第二管芯262’上方的第二绝缘层258’和第三绝缘层268’上,以生成如图2G所示的装置260。
图2H是根据本发明实施例的在进一步处理后的图2G所示装置260的图示说明。穿过绝缘层268形成了多个过孔开口272,以露出第二管芯262的电触点265,如图2H所示。在实施例中,过孔开口272具有30-50μm之间的直径。另外,穿过第三绝缘层268和第二绝缘层258形成了多个过孔开口274,以露出第一布线层254的导电迹线256的部分。在实施例中,过孔开口274的直径比过孔开口272的直径大,例如其直径在100-150微米之间。在实施例中,过孔开口274的直径至少是过孔开口272的直径的两倍。应该理解,在实施例中,过孔开口274的直径至少部分上由导电迹线254上方的第二绝缘层261与绝缘层268的厚度的组合来确定,以便形成具有可制造的纵横比(高度:宽度)的过孔开口274。在本发明的实施例中,过孔开口274的直径大于过孔开口272的直径,在本发明的实施例中,形成过孔开口274,其具有使得过孔开口具有约2:1或更小的纵横比的直径。在本发明的实施例中,利用上述激光昝孔工艺形成过孔开口272和274.。可以通过类似的方式在绝缘层268’和258”中形成过孔开口272’和274’。以生成如图2H所示的装置270。
图2I是根据本发明实施例的在进一步处理后的图2H所示装置270的图示说明。以诸如铜的导电材料填充过孔开口272,以便形成与第二管芯262的触点焊盘265接触的导电过孔282。另外,以诸如铜的导电材料填充过孔开口274,以提供与第一布线层254的导电迹线256接触的多个导电过孔284。
另外,进一步处理装置270以包括第二布线层286,其具有多条导电迹线288。第二布线层286设置在第三绝缘层268上,如图2H所示。在本发明的实施例中,形成与导电过孔282和导电过孔284都接触的至少一条导电迹线288。在本发明的实施例中,使用上述的半加成处理(SAP)来同时填充过孔282和过孔284并且形成布线层286。
在本发明的实施例中,将半加成处理设计为产生导电层,其厚到足以完全填充小过孔272,以形成完全填充的导电过孔282,但其厚度不足以完全填充大过孔开口274。在此情况下,在过孔274的侧壁上将保形地形成镀膜,形成具有未填充的中心部分285的“杯”形导电过孔284。使用半加成处理实现了将第二管芯262电耦合到衬底的布线层,而无需使用通常用于将管芯电连接至封装衬底的高温焊接键合处理。可以类似地形成导电过孔282’和284’及第二布线层286,以生成如图2I所示的装置280。
图2J是根据实施例的在进一步处理后的图2I的装置280的图示说明。在第二布线层286和第三绝缘层268上形成第四绝缘层292。在本发明的实施例中,通过将绝缘膜层压到第三绝缘层268和第二布线层286上来形成第四绝缘层292。在本发明的实施例中,第四绝缘层292突出至过孔284的未填充的中心部分285中,如图2J所示。可以类似地提供第四绝缘层292’,以产生图2J中所示的装置290。如果第二布线层286是最后的布线层,就可以通过形成开口绝缘层292来完成衬底的制造,以在布线层286中定义外部电触点可以形成至此的接触区或焊盘。
然而,如果需要额外的布线功能,就可以如上所述地连同互连过孔一起形成一个或多个额外的布线层和绝缘层。例如,根据本发明的实施例,可以进一步处理图2J的装置290,以形成额外的布线层和绝缘层。例如,可以在第四绝缘层292上形成具有多条迹线的第三布线层295,可以在第三布线层295和第二布线层286的迹线之间形成多个导电触点296。另外,可以在第三布线层295之上形成第五绝缘层296。可以在第五绝缘层296和穿过绝缘层296形成的多个导电过孔298上形成具有多条导电迹线的第四布线层297,以将第四布线层297的迹线电耦合到第三布线层295,如图2K所示。如果第四布线层297是最后的布线层,就可以在第四布线层297和第五绝缘层296上形成最后的绝缘层299。随后穿过最后的绝缘层298形成多个开口,以露出用于在其上定义触点焊盘的第四布线层297的导电迹线的部分。可以为装置290提供类似的处理,以产生图2K中所示的装置294。
图2L是在进一步处理厚的图2K的装置295的横截面图。通过去除在切割区216(图2B)的边缘部分材料以及附着释放层212和蚀刻停止层204,分离地绘制了背对背装置。示出了制造的多芯片封装400。可以提供诸如导电凸起410之类的多个外部电触点,以用于与基础衬底(图1A)的电通信。外部电触点410设置在最后的布线层297的触点焊盘上。
尽管相对于具有含两个嵌入管芯的衬底102的多芯片封装描述了本发明,但如有需要,衬底可以包括三个或更多个嵌入管芯。例如,在本发明的实施例中,如图4所示,可以通过在额外的嵌入绝缘层480中嵌入第三管芯470来形成具有含三个嵌入管芯的衬底460的多芯片封装450,嵌入绝缘层480形成于第一绝缘层130之上。如图4所示,具有多条导电迹线的额外的布线层492和额外的绝缘层490可以设置在额外的嵌入绝缘层480与第三绝缘层130之间。可以在第三管芯470的电触点与额外的布线层492之间形成多个导电过孔494,以将第三管芯470电连接至衬底460。另外,可以在额外的绝缘层490和第一绝缘层130中形成多个大导电过孔496,图4中显示其中的一个,以将第一布线层150的迹线电连接至额外的布线层492的迹线。可以使用大导电过孔164和496,以及布线层492、150和152及小过孔162和494,在第三管芯470与第二管芯106之间形成多个直接电连接。可以在衬底460中形成内部电连接,以将第三管芯470连接至第二管芯106或第一管芯105中的任意一个,或者连接至第一管芯104与第二管芯106二者,以及在第三管芯470与外部导电触点140之间通过电连接。如有需要,可以类似地嵌入额外的管芯,例如第四、第五和第六管芯。
另外,在本发明的另一实施例中,可以通过在衬底102中相邻于第一管芯104设置第三管芯560来形成具有含三个嵌入管芯的衬底502的多芯片封装500,如图5所示。过孔580可以包括在第一绝缘层130中,以提供第一布线层150与第三管芯560之间的电连接,从而将第三管芯560电耦合到衬底502。通过这种方式,第三管芯560连同第一管芯104一起嵌入到绝缘层130中,如图5所示。第一布线层150、过孔160和过孔580可以用于提供在第一管芯104与第三管芯560之间的一个或多个直接电连接570,如图5所示。另外,第一布线层150和第二布线层152及过孔164、162和580可以用于提供在第二管芯106与第三管芯560之间的一个或多个直接电连接,如图5所示。
可以以相对于图2A-2L所述的方式来制造多芯片封装450和500。
图3示出了根据本发明实施例的计算机系统。系统300包括处理器310、存储器设备320、存储器控制器330、图形控制器340、输入和输出(I/O)控制器350、显示器352、键盘354、指示设备356和外围设备358,在一些实施例中,它们全部通过总线360可通信地彼此耦合,处理器310可以是通用处理器或专用集成电路(ASIC)。I/O控制器350可以包括通信模块,以用于有线或无线通信。存储器设备320可以是动态随机存取存储器(DRAM)设备、静态随机存取存储器(SRAM)设备、闪存设备或这些存储器设备的组合。因此,在一些实施例中,系统300中的存储器设备320不必包括DRAM设备。
系统300中所示的一个或多个部件可以包括于和/或可以包括一个或多个集成电路封装,例如图1A的封装结构100。例如,处理器310或存储器设备320,或者至少一部分I/O控制器350,或者这些部件的组合可以包括在集成电路封装中,其包括在各个实施例所述结构的至少一个实施例中。
这些元件执行本领域公知的常规的功能。具体地,存储器设备320可以在一些情况下用于提供方法的可执行指令的长期存储,该方法用于形成根据本发明实施例的封装结构,在其它实施例中,可以用于在短期基础上存储方法的可执行指令,该方法用于在处理器310的执行期间形成根据本发明实施例的封装结构。另外,指令可以存储在机器可访问介质中,或者与之相关联,该机器可访问介质与系统可通信地耦合,所述机器可访问介质例如是光盘只读存储器(CD-ROM)、数字多用途盘(DVD)和软盘、载波和/或例如其它传播信号。在实施例中,存储器设备320可以为处理器310提供用于执行的可执行指令。
系统300可以包括计算机(例如,台式机、膝上型电脑、手持设备、服务器、Web设备、路由器等)、无线通信设备(例如,移动电话、无绳电话、寻呼机、个人数字助理等)、与计算机相关的外围设备(例如,打印机、扫描仪、监视器等)、娱乐设备(例如,电视机、收音机、立体声系统、磁带和光盘播放器、磁带录像机、可携式摄像机、数码相机、MP3(运动图像专家组,音频第3层)播放器、电子游戏、手表等)等。
因此,描述了具有含嵌入其中的多个垂直设置的管芯的衬底的多芯片封装及其制造方法。
Claims (16)
1.一种半导体装置,包括:
衬底,具有管芯侧和与所述管芯侧相对的焊接区侧,所述焊接区侧具有多个触点焊盘;
第一管芯,具有第一有源面和与所述有源面相对的背面;
第一绝缘层,其中所述第一管芯嵌入所述第一绝缘层内;
第一过孔,位于所述第一绝缘层中并且与所述第一管芯的所述有源面电接触;
第一布线层,具有第一导电迹线并且位于所述第一绝缘层上,其中所述第一导电迹线与所述第一过孔接触;
第二管芯,具有有源面和与所述有源面相对的背面;并且
其中,所述第一管芯和所述第二管芯嵌入到所述衬底中,使得所述第二管芯位于所述第一管芯和所述衬底的所述焊接区侧之间,并且其中所述第一管芯的所述有源面和所述第二管芯的所述有源面朝向所述衬底的所述焊接区侧,其中所述衬底包括至少一个电连接,其提供所述第一管芯与所述第二管芯之间的直接电连接,其中所述电连接没有电连接至外部触点,并且其中在所述第一管芯与所述第二管芯之间的所述电连接不包括直径大于150微米的垂直连接。
2.根据权利要求1所述的装置,其中所述第一管芯具有第一覆盖区,并且其中所述第二管芯具有第二覆盖区,并且其中所述第一管芯的所述第一覆盖区的至少一部分位于所述第二管芯的所述第二覆盖区内。
3.根据权利要求2所述的装置,其中所述第一覆盖区大于所述第二覆盖区。
4.根据权利要求3所述的装置,其中所述第二管芯的所述覆盖区完全位于所述第一管芯的所述第一覆盖区内。
5.根据权利要求1所述的装置,其中所述第一管芯通过完全嵌入所述衬底内的电连接而连接至所述第二管芯。
6.根据权利要求2所述的装置,其中所述第一管芯通过嵌入所述衬底内的电连接而连接至所述焊接区侧中的一个触点焊盘。
7.根据权利要求2所述的装置,包括嵌入所述第一管芯与所述第二管芯之间的所述衬底中的第一布线层。
8.根据权利要求1所述的装置,其中所述第二管芯嵌入所述衬底的第二绝缘层中,并且其中所述第二绝缘层中的第二导电过孔接触所述第二管芯的所述有源面。
9.根据权利要求8所述的装置,进一步包括:
第三绝缘层,设置在所述第一绝缘层与所述第二绝缘层之间;以及
第一布线层,包括嵌入所述第三绝缘层内的多条第一迹线,并且其中所述第一布线层的所述第一迹线中的一条第一迹线形成于所述第一管芯与所述第二管芯之间。
10.根据权利要求9所述的装置,进一步包括位于所述第二管芯与所述多个触点焊盘之间的第四绝缘层,其中所述第四绝缘层具有第二布线层,所述第二布线层包括嵌入其中的多条第二迹线。
11.根据权利要求10所述的装置,进一步包括位于所述第二布线层与所述第二管芯之间的所述第四绝缘层中的第一多个过孔,所述第一多个过孔具有第一直径;以及
第二多个过孔,所述第二多个过孔位于所述第三绝缘层与所述第二绝缘层中并且在所述第一布线层与所述第二布线层之间,所述第二多个过孔具有第二直径,其中所述第二直径大于所述第一直径。
12.一种多芯片封装,包括:
第一管芯,具有与背面相对的有源面;
第一绝缘层,其中所述第一管芯嵌入所述第一绝缘层内;
第一过孔,位于所述第一绝缘层中并且与所述第一管芯的所述有源面电接触;
第一布线层,具有第一导电迹线并且位于所述第一绝缘层上,其中所述第一导电迹线与所述第一过孔接触;
第二绝缘层,位于所述第一布线层和所述第一绝缘层上;
第二管芯,具有与背面相对的有源面,其中所述第二管芯的所述背面在所述第二绝缘层上;
第三绝缘层,位于所述第二管芯的所述有源面和所述第二绝缘层上;
第二导电过孔,位于所述第三绝缘层中并且与所述第二管芯的所述有源面接触;
第三导电过孔,位于所述第三绝缘层和所述第二绝缘层中,并且与所述第一布线层的所述第一导电迹线接触;
第二布线层,具有第二导电迹线并且位于所述第三绝缘层上,其中所述第二导电迹线与所述第二导电过孔和所述第三导电过孔接触;以及
第四绝缘层,位于所述第三绝缘层和所述第二布线层上,
其中在所述第一管芯与所述第二管芯之间提供直接电连接,其中所述电连接没有电连接至外部触点,并且其中在所述第一管芯与所述第二管芯之间的所述电连接不包括直径大于150微米的垂直连接。
13.根据权利要求12所述的多芯片封装,还包括位于所述第一管芯的所述背面上的绝缘膜。
14.根据权利要求12所述的多芯片封装,其中所述第一管芯具有第一覆盖区并且所述第二管芯具有第二覆盖区,并且其中所述第一管芯被定位成使得所述第一管芯的所述覆盖区至少部分位于所述第二管芯的所述覆盖区内。
15.根据权利要求12所述的多芯片封装,其中所述第二导电过孔具有第一直径并且所述第三导电过孔具有第二直径,其中所述第二直径大于所述第一直径。
16.根据权利要求12所述的多芯片封装,还包括多个外部电触点。
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US12/976,903 | 2010-12-22 | ||
US12/976,903 US8736065B2 (en) | 2010-12-22 | 2010-12-22 | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same |
PCT/US2011/061623 WO2012087474A2 (en) | 2010-12-22 | 2011-11-21 | A multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same |
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Also Published As
Publication number | Publication date |
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TWI482257B (zh) | 2015-04-21 |
DE112011104502B4 (de) | 2021-08-19 |
WO2012087474A2 (en) | 2012-06-28 |
US9559088B2 (en) | 2017-01-31 |
US20120161331A1 (en) | 2012-06-28 |
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US20140248742A1 (en) | 2014-09-04 |
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US8736065B2 (en) | 2014-05-27 |
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GB2501019A (en) | 2013-10-09 |
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