US20140159250A1 - Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility - Google Patents
Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility Download PDFInfo
- Publication number
- US20140159250A1 US20140159250A1 US13/976,394 US201113976394A US2014159250A1 US 20140159250 A1 US20140159250 A1 US 20140159250A1 US 201113976394 A US201113976394 A US 201113976394A US 2014159250 A1 US2014159250 A1 US 2014159250A1
- Authority
- US
- United States
- Prior art keywords
- die
- conductive material
- carrier
- layer
- contact points
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
Definitions
- BBUL Bumpless Build-Up Layer
- POP package-on-package
- a BBUL package typically consists of a dielectric material, possibly of a number of films, separating conductive lines or traces of a material such as copper.
- the package is also typically considerably larger than the die. Accordingly, when combined with a rigid die, the combination including a significantly larger package can experience warpage. Any such warpage may be acceptable in those instances where the combination of die and package constitute a complete structure.
- FIG. 1 shows a cross-sectional view one embodiment of a portion of a microelectronic package including a non-through silicon via die embedded in a build-up carrier.
- FIG. 2 shows a cross-sectional view another embodiment of a portion of a microelectronic package including a through silicon via die embedded in a build-up carrier.
- FIG. 3 shows a cross-sectional exploded side view of a sacrificial substrate with sacrificial copper foils attached to opposite sides thereof
- FIG. 4 show the structure of FIG. 3 following the introduction of contacts on the copper foils and a dielectric layer over the contacts in a process of forming one portion of the carrier.
- FIG. 5 shows the structure of FIG. 4 following the patterning of conductive vias to contact points and a first conductive layer or line on the dielectric layer in a process of forming one portion of a carrier.
- FIG. 6 shows the structure of FIG. 5 following the attachment of die patterning of alternating layers to opposite sides of the structure.
- FIG. 7 shows the structure of FIG. 6 following the introduction of a dielectric layer over the die, the formation of vias in the dielectric layer and the introduction of a conductive material in the vias and the patterning of a conductive layer or line on the dielectric.
- FIG. 8 shows the structure of FIG. 7 following the introduction of successive layers of a dielectric material and patterned the conductive material in a process of forming a second portion of the carrier.
- FIG. 9 shows the isolation of one package from the structure of FIG. 8 and the connection of at least one secondary device to the package.
- FIG. 10 illustrates a schematic illustration of a computing device.
- FIG. 1 shows a cross-sectional view of a microelectronic package according to one embodiment.
- microelectronic package 100 utilizes bumpless build-up layer (BBUL) technology.
- Microelectronic package 100 includes carrier 120 and die 110 , such as a microprocessor die, embedded in carrier 120 device side down (as viewed).
- Carrier 120 includes portion 1200 A encompassing die 110 and extending from a device side of die 110 and portion 1200 B opposite portion 1200 A.
- die 110 is a silicon die or the like having a thickness of approximately 150 micrometers ( ⁇ m). In another example, die 110 can be a silicon die or the like that has a thickness less than 150 ⁇ m such as 50 ⁇ m to 150 ⁇ m. It is appreciated that other thicknesses for die 110 are possible.
- portion 1200 A of carrier 120 includes multiple build-up layers including dielectric layers 130 of, for example, ABF and conductive layers 140 of, for example, copper or a copper alloy (connected with conductive vias or the like) that provide connectivity to the die (power, ground, input/output, etc.) through contacts 145 .
- Die 110 and portion 1200 A of carrier 120 are in direct physical contact with each other (e.g., there are no solder bumps connecting die 110 to carrier 120 ).
- Die 110 is directly connected to contacts or conductive vias of portion 1200 A of carrier 120 at its device side.
- Surface 155 of portion 1200 A opposite die 110 , portion 1200 of carrier 120 includes contacts 145 .
- contacts 145 are suitable for a surface mount packaging implementation (e.g., a ball grid array).
- one of dielectric layers 130 surrounds the lateral side walls of die 110 .
- adhesive layer 150 Overlying a back side of die 110 of microelectronic package 100 in FIG. 1 is adhesive layer 150 of, for example, a die backside film (DBF) polymer, epoxy based adhesive with or without fillers. Overlying adhesive layer 150 and on portion 1200 A of carrier 120 is portion 1200 B of carrier 120 . Portion 1200 B includes additional build-up layers including dielectric layers 160 and conductive layers 170 . Dielectric layers 160 (e.g., two or more) may be of a material similar to a material for dielectric layers 130 (e.g., ABF) or a different material.
- Conductive layers 170 e.g., one or more
- Conductive layers 170 are, for example, a copper or copper alloy material. Conductive layers 170 are connected with conductive vias or the like to one or more conductive layers 140 of portion 1200 A of carrier 120 .
- FIG. 1 also shows contacts 180 on exposed surface 165 of second portion 1200 B of carrier 120 .
- Contacts 180 are connected to conductive layers of carrier 120 , e.g., conductive layers of portion 1200 A of carrier 120 .
- Contacts 180 provide an additional routing opportunity (additional to contacts 145 on portion 1200 A of carrier 120 ) to route signals to or from microelectronic package 100 .
- Contacts 180 may extend over an entire package surface of microelectronic package 100 or some lesser portion of the surface.
- Contacts 180 allow additional interconnect points for the package as well as contact points for a second device, such as a memory device or microprocessor (possibly encompassed in a package, e.g., package-on-package (“POP”)) to be electrically connected to microelectronic package 100 .
- a second device such as a memory device or microprocessor (possibly encompassed in a package, e.g., package-on-package (“POP”)) to be electrically connected to microelectronic package 100 .
- POP package-on-package
- portion 1200 B of carrier 120 provides warpage management to the package as the presence of one or more conductive layers and dielectric layers will tend to stiffen the package and inhibit warpage. Further, die 110 will experience reduced stress since it is embedded in carrier 120 .
- FIG. 2 shows another embodiment of a microelectronic package that includes a die having through silicon vias (TSVs).
- FIG. 2 shows microelectronic package 200 including carrier 220 having die 210 embedded therein. Die 210 is embedded device side down (as viewed).
- Carrier 220 includes portion 2200 A encompassing die 210 and extending from a device side of die 210 and portion 2200 B opposite portion 2200 A.
- Portion 2200 A of carrier 220 includes a number of conductive layers or levels of, for example, copper or a copper alloy, disposed therein and separated by dielectric or insulating layers 230 such as layers of ABF film.
- the one or more conductive layers are connected to contacts 245 on a surface of portion 2200 B opposite die 110 . Contacts 245 are suitably, in one embodiment, for a surface mount packaging implementation.
- portion 2200 B of carrier 220 Overlying die 210 as viewed is portion 2200 B of carrier 220 .
- Portion 2200 B includes one or more layers of conductive layers 270 or levels (e.g., Cu or a Cu alloy) separated from die 210 (a back side of die 210 ) and from one another by dielectric or insulating material 260 (e.g., ABF).
- conductive layers 270 or levels e.g., Cu or a Cu alloy
- die 210 includes through silicon vias (TSVs) 215 extending from a device side through a die culminating in contacts 275 on a back side surface of die 210 .
- TSVs through silicon vias
- FIG. 2 shows that one or more conductive layers 270 are conductively connected with contacts 275 to route signals to/from die 210 .
- FIG. 2 shows solder connections 274 to contacts 275 and patterned conductive layer or line 270 .
- an adhesive such as DBF that surrounds the solder connections.
- FIG. 2 also shows contacts 280 exposed on a surface of portion 220 B.
- Contacts 280 are electrically connected to respective conductive layers in carrier 220 , e.g., in portion 2200 B on a back side of die 210 .
- Contacts 280 include contacts connected to contacts 275 (by conductive layer/via routing from contacts 275 directly to contact 280 ).
- Other of contacts 275 are connected to conductive layers 270 that are connected to conductive layers 240 in portion 2200 A of carrier 220 that extend from a device side of die 210 .
- Such conductive vias and possible contacts provide an additional interconnect points for the package as well as contacts points for another die or other device to be connected to die 210 .
- the embodiments of a microelectronic package described above with respect to FIG. 1 and FIG. 2 integrate one or more additional routing layers and BBUL architecture.
- the one or more additional routing layers enables dual side connectivity allowing for stacking of one or more devices on the package or package-on-package (POP) configurations.
- POP package-on-package
- the integration enables increased warpage control, especially for large surface area (e.g., on the order of 17 ⁇ 17 mm 2 ) and ultrathin (e.g., less than 150 ⁇ m) dies (both TSV and non-TSV dies) where warpage might be more likely.
- the integration of one or more additional routing layers still further provides warpage control solutions to a package-on-package (POP) BBUL package (e.g., non-TSV die, see FIG. 1 ) with improved warpage control due to the presence of the one or more routing layers on the die back side.
- POP package-on-package
- BBUL package e.g., non-TSV die, see FIG. 1
- warpage control solutions are presented that enable both POP and wide I/O stacking (device directly to die).
- FIGS. 3-9 describe one embodiment for forming a microelectronic package, such as microelectronic package 200 ( FIG. 2 ) with a TSV die.
- FIG. 3 shows an exploded cross-sectional side view of a portion of sacrificial substrate 310 of, for example, a prepeg material including opposing layers of copper foils 315 A and 315 B that are separated from sacrificial substrate 310 by shorter copper foil layers 320 A and 320 B, respectively. Copper foils 315 A and 315 B tend to stick to the shorter foils based on vacuum.
- FIG. 4 shows the structure of FIG. 3 following the introduction and patterning of contacts on copper foil 315 A and copper foil 315 B, respectively.
- FIG. 4 shows contacts 322 A and 322 B formed on copper foil 315 A and 315 B, respectively.
- contacts 325 A and 325 B include a first layer adjacent copper foil 315 A and copper foil 315 B, respectively, of a gold-nickel alloy and a second layer overlying a second layer of copper or a copper alloy overlying the gold-nickel alloy.
- Contacts 325 A and 325 B may be formed by deposition (e.g., plating, a sputter deposition, etc.) and patterning at a desired location for possible electrical contact with a secondary device or package.
- FIG. 4 also shows the structure following the introduction of dielectric layer 324 A and dielectric layer 324 B on opposite sides of the structure.
- dielectric layer 324 A and dielectric layer 324 B are each an ABF dielectric possibly including a filler that have been described for use in forming a BBUL package.
- One method of introduction of an ABF material is as a film that is laid on the contacts and copper foils.
- FIG. 5 shows the structure of FIG. 4 following the patterning of vias through dielectric layer 324 A and dielectric layer 324 B to contacts 322 A and 322 B and the formation of conductive vias and a conductive layer or line on each of dielectric layer 324 A and dielectric layer 324 B.
- Contacts 322 A/ 322 B may be exposed and conductive vias formed thereto (through dielectric layer 324 / 324 B).
- patterning vias in a material such as ABF such patterning may be done by, for example, a drilling process.
- electrical conductor (e.g., copper metal) patterning may be done in order to fill the vias and pattern conductive layer or line 326 A and 326 B on dielectric layer 324 A and dielectric layer 324 B, respectively, for example, using an electroless seed layer followed by a dry film resist (DFR) patterning and plating. The DFR may then be stripped followed by a flash etch to remove any unwanted electroless seed layer. It is appreciated that other methods are also suitable.
- FIG. 5 shows vias 325 A and 325 B filled with conductive material and represented as conductive vias including conductive vias to contact points 327 A and 327 B, respectively, that will be connected to through silicon vias (TSVs) of respective die that are subsequently connected to the structure.
- TSVs through silicon vias
- FIG. 6 shows the structure of FIG. 5 following the mounting of die 340 A and die 340 B on opposite sides of the structure.
- die 340 A and die 340 B are TSV die.
- die 340 A is connected by adhesive 350 A
- die 340 B is connected by adhesive 350 B.
- a suitable adhesive material for 350 A and adhesive 350 B is DBF.
- Die 340 A and die 340 B are positioned device side up (device side facing away from each copper foil).
- FIG. 6 shows each die 340 A and die 340 B having through substrate vias 385 A and 385 V, respectively, from a device side to a back side of the die.
- Vias 385 A and vias 385 B are connected to contacts 327 A and contacts 327 B through, for example, solder connections 352 A and 352 B.
- FIG. 6 shows that conductive pillars 345 A and 345 B are connected to the contact points die 340 A and die 340 B, respectively. Pillars 345 A and pillars 345 B may be fabricated at the die fabrication stage.
- FIG. 7 shows the structure of FIG. 6 following the introduction of a dielectric layer on each side of the structure.
- FIG. 7 shows dielectric layer 360 A and dielectric layer 360 B each of, for example, an ABF material introduced as a film.
- FIG. 7 also shows the patterning of a conductive line or layer 375 A and conductive line or layer 375 B on dielectric layer 360 A and dielectric layer 360 B, respectively, and conductive vias 365 A and 365 B formed through the respective dielectric layers to conductive layer 326 A and conductive layer 326 B.
- Conductive vias are also formed to pillars 345 A and pillars 345 B to contact points on a device side of die 340 A and die 340 Ab.
- a suitable material for patterned conductive line or layer 375 A/ 375 B and for conductive vias 365 A/ 365 B is copper deposited, for example, by an electroless process.
- FIG. 8 shows the structure of FIG. 7 following the patterning of additional levels of conductive lines 392 A/ 392 B, 394 A/ 394 B, and 396 A/ 396 B (e.g., three additional levels separated from one another by dielectric layers 391 A/ 391 B, 393 A/ 393 B, 395 A/ 395 B, and 397 A/ 397 B (e.g., ABF film)).
- a typical BBUL package may have four to six levels of conductive lines or traces connected to one another or die 340 A/die 340 B by conductive vias.
- a top level is patterned with contacts that are suitable, for example, for a surface mount packaging implementation (e.g., a ball grid array).
- FIG. 9 shows a portion of the structure of FIG. 8 following the separation of the structure into two individual package portions by removal of sacrificial substrate 310 and copper foils 315 A and 315 B.
- FIG. 9 shows a portion of a free standing microelectronic package that has a TSV die connected at a device side to a first portion of a build-up carrier including a number of alternating layers of electrically conductive material (four levels of conductive traces) and dielectric or insulating material.
- Contact points of die 340 A are, for example, pillars fabricated at the die fabrication process and are connected to the conductive material of the build-up carrier.
- the package also includes contact points 325 A extending to surface 400 A for electrical connection to a one or more conductive layers or lines to be formed as part of a second portion of the carrier.
- die 340 A as a TSV die, includes conductive vias 385 A extending from a device die to a backside of the die.
- FIG. 9 shows the structure following the connection of a secondary device or package 400 to the now formed microelectronic package (e.g., to die 340 A in the now formed package).
- FIG. 9 shows secondary device 410 that is, for example, a memory or a logic die electrically connected to die 340 A through contacts 322 A on a backside surface of the package.
- FIG. 9 also shows that additional device 420 , such as a package, can be connected to the formed microelectronic package through contacts 322 a A.
- a memory package may be aligned over the formed package as connected to contact 425 A.
- FIGS. 3-9 a process of forming a microelectronic package including a TSV die was described. It is appreciated that many of the same process operations may be utilized in a microelectronic package with a non-TSV die. One difference is that with a non-TSV die, the back side of the die does not need to be accessed and no conductive vias are formed to the back side of the die.
- FIG. 10 illustrates a computing device 500 in accordance with one implementation.
- Computing device 500 houses board 502 .
- Board 502 may include a number of components, including but not limited to processor 504 and at least one communication chip 506 .
- Processor 504 is physically and electrically coupled to board 502 .
- the at least one communication chip 506 is also physically and electrically coupled to board 502 .
- communication chip 506 is part of processor 504 .
- computing device 500 may include other components that may or may not be physically and electrically coupled to board 502 .
- these other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
- volatile memory e.g., DRAM
- non-volatile memory e.g., ROM
- flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna
- Communication chip 506 enables wireless communications for the transfer of data to and from computing device 500 .
- wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
- Communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
- Computing device 500 may include a plurality of communication chips 506 .
- a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
- Processor 504 of computing device 500 includes an integrated circuit die packaged within processor 504 .
- the package formed in accordance with embodiment described above utilizes BBUL technology with carrier encapsulating a TSV or non-TSV die that inhibits package warpage and provides one or more routing layers on a back side of the carrier.
- the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
- Communication chip 506 also includes an integrated circuit die packaged within communication chip 506 .
- package is based on BBUL technology and incorporates a primary core surrounding a TSV or non-TSV integrated circuit die that inhibit package warpage.
- Such packaging will enable stacking of various devices, including but not limited to, a microprocessor chip (die) with a memory die with a graphics die with a chip set with GPS.
- another component housed within computing device 600 may contain a microelectronic package incorporates a primary core surrounding a TSV or non-TSV integrated circuit die that inhibits package warpage.
- computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
- computing device 500 may be any other electronic device that processes data.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
- 1. Field
- Packaging for microelectronic devices.
- 2. Description of Related Art
- Microelectronic packaging technology, including methods to mechanically and electrically attach a silicon die (e.g., a microprocessor) to a substrate or other carrier continues to be refined and improved. Bumpless Build-Up Layer (BBUL) technology is one approach to a packaging architecture. Among its advantages, BBUL eliminates the need for assembly, eliminates prior solder ball interconnections (e.g., flip-chip interconnections), reduces stress on low-k interlayer dielectric of dies due to die-to-substrate coefficient of thermal expansion (CTE mismatch), and reduces package inductance through elimination of core and flip-chip interconnect for improved input/output (I/O) and power delivery performance.
- With shrinking electronic device sizes and increasing functionality, integrated circuit packages will need to occupy less space. One way to conserve space is to combine a device or package on top of a package (e.g., package-on-package (POP)). Such combination will require increased connectivity through, for example, routing layers with the die and the package.
- One issue that arises with a package, such as a BBUL, is warpage. A BBUL package typically consists of a dielectric material, possibly of a number of films, separating conductive lines or traces of a material such as copper. The package is also typically considerably larger than the die. Accordingly, when combined with a rigid die, the combination including a significantly larger package can experience warpage. Any such warpage may be acceptable in those instances where the combination of die and package constitute a complete structure.
-
FIG. 1 shows a cross-sectional view one embodiment of a portion of a microelectronic package including a non-through silicon via die embedded in a build-up carrier. -
FIG. 2 shows a cross-sectional view another embodiment of a portion of a microelectronic package including a through silicon via die embedded in a build-up carrier. -
FIG. 3 shows a cross-sectional exploded side view of a sacrificial substrate with sacrificial copper foils attached to opposite sides thereof -
FIG. 4 show the structure ofFIG. 3 following the introduction of contacts on the copper foils and a dielectric layer over the contacts in a process of forming one portion of the carrier. -
FIG. 5 shows the structure ofFIG. 4 following the patterning of conductive vias to contact points and a first conductive layer or line on the dielectric layer in a process of forming one portion of a carrier. -
FIG. 6 shows the structure ofFIG. 5 following the attachment of die patterning of alternating layers to opposite sides of the structure. -
FIG. 7 shows the structure ofFIG. 6 following the introduction of a dielectric layer over the die, the formation of vias in the dielectric layer and the introduction of a conductive material in the vias and the patterning of a conductive layer or line on the dielectric. -
FIG. 8 shows the structure ofFIG. 7 following the introduction of successive layers of a dielectric material and patterned the conductive material in a process of forming a second portion of the carrier. -
FIG. 9 shows the isolation of one package from the structure ofFIG. 8 and the connection of at least one secondary device to the package. -
FIG. 10 illustrates a schematic illustration of a computing device. -
FIG. 1 shows a cross-sectional view of a microelectronic package according to one embodiment. As illustrated inFIG. 1 ,microelectronic package 100 utilizes bumpless build-up layer (BBUL) technology.Microelectronic package 100 includescarrier 120 and die 110, such as a microprocessor die, embedded incarrier 120 device side down (as viewed).Carrier 120 includesportion 1200A encompassing die 110 and extending from a device side of die 110 andportion 1200Bopposite portion 1200A. - In one embodiment, die 110 is a silicon die or the like having a thickness of approximately 150 micrometers (μm). In another example, die 110 can be a silicon die or the like that has a thickness less than 150 μm such as 50 μm to 150 μm. It is appreciated that other thicknesses for die 110 are possible. Referring to
FIG. 1 ,portion 1200A ofcarrier 120 includes multiple build-up layers includingdielectric layers 130 of, for example, ABF andconductive layers 140 of, for example, copper or a copper alloy (connected with conductive vias or the like) that provide connectivity to the die (power, ground, input/output, etc.) throughcontacts 145. Die 110 andportion 1200A ofcarrier 120 are in direct physical contact with each other (e.g., there are no solder bumps connecting die 110 to carrier 120). Die 110 is directly connected to contacts or conductive vias ofportion 1200A ofcarrier 120 at its device side.Surface 155 ofportion 1200A opposite die 110, portion 1200 ofcarrier 120 includescontacts 145. In one embodiment,contacts 145 are suitable for a surface mount packaging implementation (e.g., a ball grid array). As shown inFIG. 1 , one ofdielectric layers 130 surrounds the lateral side walls of die 110. - Overlying a back side of die 110 of
microelectronic package 100 inFIG. 1 isadhesive layer 150 of, for example, a die backside film (DBF) polymer, epoxy based adhesive with or without fillers. Overlyingadhesive layer 150 and onportion 1200A ofcarrier 120 isportion 1200B ofcarrier 120.Portion 1200B includes additional build-up layers includingdielectric layers 160 andconductive layers 170. Dielectric layers 160 (e.g., two or more) may be of a material similar to a material for dielectric layers 130 (e.g., ABF) or a different material. Conductive layers 170 (e.g., one or more) are, for example, a copper or copper alloy material.Conductive layers 170 are connected with conductive vias or the like to one or moreconductive layers 140 ofportion 1200A ofcarrier 120. -
FIG. 1 also showscontacts 180 on exposedsurface 165 ofsecond portion 1200B ofcarrier 120.Contacts 180 are connected to conductive layers ofcarrier 120, e.g., conductive layers ofportion 1200A ofcarrier 120.Contacts 180 provide an additional routing opportunity (additional to contacts 145 onportion 1200A of carrier 120) to route signals to or frommicroelectronic package 100.Contacts 180 may extend over an entire package surface ofmicroelectronic package 100 or some lesser portion of the surface.Contacts 180 allow additional interconnect points for the package as well as contact points for a second device, such as a memory device or microprocessor (possibly encompassed in a package, e.g., package-on-package (“POP”)) to be electrically connected tomicroelectronic package 100. - In addition to providing an additional routing opportunity, the presence of
portion 1200B ofcarrier 120 provides warpage management to the package as the presence of one or more conductive layers and dielectric layers will tend to stiffen the package and inhibit warpage. Further, die 110 will experience reduced stress since it is embedded incarrier 120. -
FIG. 2 shows another embodiment of a microelectronic package that includes a die having through silicon vias (TSVs).FIG. 2 shows microelectronic package 200 includingcarrier 220 having die 210 embedded therein. Die 210 is embedded device side down (as viewed). Carrier 220 includesportion 2200A encompassing die 210 and extending from a device side of die 210 andportion 2200Bopposite portion 2200A.Portion 2200A ofcarrier 220 includes a number of conductive layers or levels of, for example, copper or a copper alloy, disposed therein and separated by dielectric orinsulating layers 230 such as layers of ABF film. The one or more conductive layers are connected tocontacts 245 on a surface ofportion 2200B oppositedie 110.Contacts 245 are suitably, in one embodiment, for a surface mount packaging implementation. - Overlying die 210 as viewed is
portion 2200B ofcarrier 220.Portion 2200B includes one or more layers ofconductive layers 270 or levels (e.g., Cu or a Cu alloy) separated from die 210 (a back side of die 210) and from one another by dielectric or insulating material 260 (e.g., ABF). - In the embodiment shown in
FIG. 2 , die 210 includes through silicon vias (TSVs) 215 extending from a device side through a die culminating incontacts 275 on a back side surface of die 210.FIG. 2 shows that one or moreconductive layers 270 are conductively connected withcontacts 275 to route signals to/from die 210.FIG. 2 shows solder connections 274 tocontacts 275 and patterned conductive layer orline 270. Overlying a back side ofdie 240 is an adhesive such as DBF that surrounds the solder connections. -
FIG. 2 also showscontacts 280 exposed on a surface of portion 220B.Contacts 280 are electrically connected to respective conductive layers incarrier 220, e.g., inportion 2200B on a back side of die 210.Contacts 280 include contacts connected to contacts 275 (by conductive layer/via routing fromcontacts 275 directly to contact 280). Other ofcontacts 275 are connected toconductive layers 270 that are connected toconductive layers 240 inportion 2200A ofcarrier 220 that extend from a device side of die 210. Such conductive vias and possible contacts provide an additional interconnect points for the package as well as contacts points for another die or other device to be connected to die 210. - The embodiments of a microelectronic package described above with respect to
FIG. 1 andFIG. 2 integrate one or more additional routing layers and BBUL architecture. The one or more additional routing layers enables dual side connectivity allowing for stacking of one or more devices on the package or package-on-package (POP) configurations. Furthermore, since virtually the entire surface of a package is available for conductive contacts to the package interconnects or the die, the possibilities for positioning of a secondary device or package or multiple devices or package on the packages described with reference toFIG. 1 andFIG. 2 are increased. In addition, the integration enables increased warpage control, especially for large surface area (e.g., on the order of 17×17 mm2) and ultrathin (e.g., less than 150 μm) dies (both TSV and non-TSV dies) where warpage might be more likely. The integration of one or more additional routing layers still further provides warpage control solutions to a package-on-package (POP) BBUL package (e.g., non-TSV die, seeFIG. 1 ) with improved warpage control due to the presence of the one or more routing layers on the die back side. For TSV dies, warpage control solutions are presented that enable both POP and wide I/O stacking (device directly to die). -
FIGS. 3-9 describe one embodiment for forming a microelectronic package, such as microelectronic package 200 (FIG. 2 ) with a TSV die. Referring toFIG. 3 ,FIG. 3 shows an exploded cross-sectional side view of a portion ofsacrificial substrate 310 of, for example, a prepeg material including opposing layers of copper foils 315A and 315B that are separated fromsacrificial substrate 310 by shorter copper foil layers 320A and 320B, respectively. Copper foils 315A and 315B tend to stick to the shorter foils based on vacuum. -
FIG. 4 shows the structure ofFIG. 3 following the introduction and patterning of contacts oncopper foil 315A andcopper foil 315B, respectively.FIG. 4 showscontacts copper foil contacts adjacent copper foil 315A andcopper foil 315B, respectively, of a gold-nickel alloy and a second layer overlying a second layer of copper or a copper alloy overlying the gold-nickel alloy.Contacts -
FIG. 4 also shows the structure following the introduction ofdielectric layer 324A anddielectric layer 324B on opposite sides of the structure. In one embodiment,dielectric layer 324A anddielectric layer 324B are each an ABF dielectric possibly including a filler that have been described for use in forming a BBUL package. One method of introduction of an ABF material is as a film that is laid on the contacts and copper foils. -
FIG. 5 shows the structure ofFIG. 4 following the patterning of vias throughdielectric layer 324A anddielectric layer 324B tocontacts dielectric layer 324A anddielectric layer 324B.Contacts 322A/322B may be exposed and conductive vias formed thereto (through dielectric layer 324/324B). With regard to patterning vias in a material such as ABF, such patterning may be done by, for example, a drilling process. Once the vias are formed, electrical conductor (e.g., copper metal) patterning may be done in order to fill the vias and pattern conductive layer orline dielectric layer 324A anddielectric layer 324B, respectively, for example, using an electroless seed layer followed by a dry film resist (DFR) patterning and plating. The DFR may then be stripped followed by a flash etch to remove any unwanted electroless seed layer. It is appreciated that other methods are also suitable.FIG. 5 shows vias 325A and 325B filled with conductive material and represented as conductive vias including conductive vias to contactpoints -
FIG. 6 shows the structure ofFIG. 5 following the mounting ofdie 340A and die 340B on opposite sides of the structure. In this embodiment, die 340A and die 340B are TSV die. As shown inFIG. 6 , die 340A is connected by adhesive 350A and die 340B is connected by adhesive 350B. A suitable adhesive material for 350A and adhesive 350B is DBF.Die 340A and die 340B are positioned device side up (device side facing away from each copper foil).FIG. 6 shows each die 340A and die 340B having throughsubstrate vias 385A and 385V, respectively, from a device side to a back side of the die. Vias 385A and vias 385B are connected tocontacts 327A andcontacts 327B through, for example,solder connections FIG. 6 shows thatconductive pillars Pillars 345A andpillars 345B may be fabricated at the die fabrication stage. -
FIG. 7 shows the structure ofFIG. 6 following the introduction of a dielectric layer on each side of the structure.FIG. 7 showsdielectric layer 360A anddielectric layer 360B each of, for example, an ABF material introduced as a film.FIG. 7 also shows the patterning of a conductive line orlayer 375A and conductive line orlayer 375B ondielectric layer 360A anddielectric layer 360B, respectively, andconductive vias conductive layer 326A andconductive layer 326B. Conductive vias are also formed topillars 345A andpillars 345B to contact points on a device side ofdie 340A and die 340Ab. A suitable material for patterned conductive line orlayer 375A/375B and forconductive vias 365A/365B is copper deposited, for example, by an electroless process. -
FIG. 8 shows the structure ofFIG. 7 following the patterning of additional levels ofconductive lines 392A/392B, 394A/394B, and 396A/396B (e.g., three additional levels separated from one another bydielectric layers 391A/391B, 393A/393B, 395A/395B, and 397A/397B (e.g., ABF film)). A typical BBUL package may have four to six levels of conductive lines or traces connected to one another or die 340A/die 340B by conductive vias. A top level is patterned with contacts that are suitable, for example, for a surface mount packaging implementation (e.g., a ball grid array). -
FIG. 9 shows a portion of the structure ofFIG. 8 following the separation of the structure into two individual package portions by removal ofsacrificial substrate 310 and copper foils 315A and 315B. By removing the individual packages fromsacrificial substrate 310,FIG. 9 shows a portion of a free standing microelectronic package that has a TSV die connected at a device side to a first portion of a build-up carrier including a number of alternating layers of electrically conductive material (four levels of conductive traces) and dielectric or insulating material. Contact points ofdie 340A are, for example, pillars fabricated at the die fabrication process and are connected to the conductive material of the build-up carrier. The package also includescontact points 325A extending to surface 400A for electrical connection to a one or more conductive layers or lines to be formed as part of a second portion of the carrier. Further, die 340A, as a TSV die, includesconductive vias 385A extending from a device die to a backside of the die. -
FIG. 9 shows the structure following the connection of a secondary device or package 400 to the now formed microelectronic package (e.g., to die 340A in the now formed package).FIG. 9 showssecondary device 410 that is, for example, a memory or a logic die electrically connected to die 340A throughcontacts 322A on a backside surface of the package.FIG. 9 also shows thatadditional device 420, such as a package, can be connected to the formed microelectronic package through contacts 322 aA. Representatively, a memory package may be aligned over the formed package as connected to contact 425A. - In
FIGS. 3-9 , a process of forming a microelectronic package including a TSV die was described. It is appreciated that many of the same process operations may be utilized in a microelectronic package with a non-TSV die. One difference is that with a non-TSV die, the back side of the die does not need to be accessed and no conductive vias are formed to the back side of the die. -
FIG. 10 illustrates acomputing device 500 in accordance with one implementation.Computing device 500houses board 502.Board 502 may include a number of components, including but not limited toprocessor 504 and at least onecommunication chip 506.Processor 504 is physically and electrically coupled toboard 502. In some implementations the at least onecommunication chip 506 is also physically and electrically coupled toboard 502. In further implementations,communication chip 506 is part ofprocessor 504. - Depending on its applications,
computing device 500 may include other components that may or may not be physically and electrically coupled toboard 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). -
Communication chip 506 enables wireless communications for the transfer of data to and fromcomputing device 500. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.Communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.Computing device 500 may include a plurality ofcommunication chips 506. For instance, afirst communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and asecond communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. -
Processor 504 ofcomputing device 500 includes an integrated circuit die packaged withinprocessor 504. In some implementations, the package formed in accordance with embodiment described above utilizes BBUL technology with carrier encapsulating a TSV or non-TSV die that inhibits package warpage and provides one or more routing layers on a back side of the carrier. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. -
Communication chip 506 also includes an integrated circuit die packaged withincommunication chip 506. In accordance with another implementation, package is based on BBUL technology and incorporates a primary core surrounding a TSV or non-TSV integrated circuit die that inhibit package warpage. Such packaging will enable stacking of various devices, including but not limited to, a microprocessor chip (die) with a memory die with a graphics die with a chip set with GPS. - In further implementations, another component housed within computing device 600 may contain a microelectronic package incorporates a primary core surrounding a TSV or non-TSV integrated circuit die that inhibits package warpage.
- In various implementations,
computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations,computing device 500 may be any other electronic device that processes data. - In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the invention but to illustrate it. The scope of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.
- It should also be appreciated that reference throughout this specification to “one embodiment”, “an embodiment”, “one or more embodiments”, or “different embodiments”, for example, means that a particular feature may be included in the practice of the invention. Similarly, it should be appreciated that in the description various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects may lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.
Claims (18)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2011/068277 WO2013101242A1 (en) | 2011-12-31 | 2011-12-31 | Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2011/068277 A-371-Of-International WO2013101242A1 (en) | 2011-12-31 | 2011-12-31 | Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/629,350 Continuation US9691728B2 (en) | 2011-12-31 | 2015-02-23 | BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140159250A1 true US20140159250A1 (en) | 2014-06-12 |
Family
ID=48698474
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/976,394 Abandoned US20140159250A1 (en) | 2011-12-31 | 2011-12-31 | Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility |
US14/629,350 Active US9691728B2 (en) | 2011-12-31 | 2015-02-23 | BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/629,350 Active US9691728B2 (en) | 2011-12-31 | 2015-02-23 | BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility |
Country Status (2)
Country | Link |
---|---|
US (2) | US20140159250A1 (en) |
WO (1) | WO2013101242A1 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130201631A1 (en) * | 2012-02-08 | 2013-08-08 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
US20140264830A1 (en) * | 2013-03-13 | 2014-09-18 | Weng Hong Teh | Bumpless build-up layer (bbul) semiconductor package with ultra-thin dielectric layer |
US20140262468A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method for an Improved Interconnect Structure |
US9230726B1 (en) | 2015-02-20 | 2016-01-05 | Crane Electronics, Inc. | Transformer-based power converters with 3D printed microchannel heat sink |
WO2017111792A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Fabrication and use of through silicon vias on double sided interconnect device |
WO2019132956A1 (en) * | 2017-12-29 | 2019-07-04 | Intel Corporation | Microelectronic assemblies |
US11324254B2 (en) | 2014-10-22 | 2022-05-10 | Nicoventures Trading Limited | Inhalator and cartridge thereof |
US11511056B2 (en) | 2015-10-02 | 2022-11-29 | Nicoventures Trading Limited | Apparatus for generating an inhalable medium |
US11672276B2 (en) | 2016-11-02 | 2023-06-13 | British American Tobacco (Investments) Limited | Aerosol provision article |
US11865246B2 (en) | 2015-02-27 | 2024-01-09 | Nicoventures Trading Limited | Apparatus for generating an inhalable medium |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6260806B2 (en) | 2013-09-27 | 2018-01-17 | インテル・コーポレーション | Double-sided die package |
WO2015195083A1 (en) * | 2014-06-16 | 2015-12-23 | Intel Corporation | Silicon die with integrated high voltage devices |
US20180005944A1 (en) * | 2016-07-02 | 2018-01-04 | Intel Corporation | Substrate with sub-interconnect layer |
US10515929B2 (en) | 2018-04-09 | 2019-12-24 | International Business Machines Corporation | Carrier and integrated memory |
US10431563B1 (en) | 2018-04-09 | 2019-10-01 | International Business Machines Corporation | Carrier and integrated memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080116565A1 (en) * | 2006-11-21 | 2008-05-22 | Phoenix Precision Technology Corporation | Circuit board structure with embedded semiconductor chip and method for fabricating the same |
US20090224378A1 (en) * | 2008-03-04 | 2009-09-10 | Advanced Semiconductor Engineering, Inc. | Package structure with embedded die and method of fabricating the same |
US20130069239A1 (en) * | 2011-09-16 | 2013-03-21 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stacked Semiconductor Die and Conductive Interconnect Structure Through an Encapsulant |
US20130075924A1 (en) * | 2011-09-23 | 2013-03-28 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG120123A1 (en) * | 2003-09-30 | 2006-03-28 | Micron Technology Inc | Castellated chip-scale packages and methods for fabricating the same |
US20070090517A1 (en) * | 2005-10-05 | 2007-04-26 | Moon Sung-Won | Stacked die package with thermally conductive block embedded in substrate |
TWI443789B (en) * | 2008-07-04 | 2014-07-01 | Unimicron Technology Corp | Substrate having semiconductor chip embedded therein and fabrication method thereof |
JP5460388B2 (en) * | 2010-03-10 | 2014-04-02 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
US8558392B2 (en) * | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
US20110316140A1 (en) * | 2010-06-29 | 2011-12-29 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
US8343810B2 (en) * | 2010-08-16 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers |
US8736065B2 (en) * | 2010-12-22 | 2014-05-27 | Intel Corporation | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same |
-
2011
- 2011-12-31 US US13/976,394 patent/US20140159250A1/en not_active Abandoned
- 2011-12-31 WO PCT/US2011/068277 patent/WO2013101242A1/en active Application Filing
-
2015
- 2015-02-23 US US14/629,350 patent/US9691728B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080116565A1 (en) * | 2006-11-21 | 2008-05-22 | Phoenix Precision Technology Corporation | Circuit board structure with embedded semiconductor chip and method for fabricating the same |
US20090224378A1 (en) * | 2008-03-04 | 2009-09-10 | Advanced Semiconductor Engineering, Inc. | Package structure with embedded die and method of fabricating the same |
US20130069239A1 (en) * | 2011-09-16 | 2013-03-21 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stacked Semiconductor Die and Conductive Interconnect Structure Through an Encapsulant |
US20130075924A1 (en) * | 2011-09-23 | 2013-03-28 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9888568B2 (en) * | 2012-02-08 | 2018-02-06 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
US11172572B2 (en) | 2012-02-08 | 2021-11-09 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
US20130201631A1 (en) * | 2012-02-08 | 2013-08-08 | Crane Electronics, Inc. | Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module |
US20140262468A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method for an Improved Interconnect Structure |
US10312204B2 (en) | 2013-03-12 | 2019-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
US9275925B2 (en) * | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
US9633870B2 (en) | 2013-03-12 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
US10043770B2 (en) | 2013-03-12 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
US9520350B2 (en) * | 2013-03-13 | 2016-12-13 | Intel Corporation | Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer |
US20140264830A1 (en) * | 2013-03-13 | 2014-09-18 | Weng Hong Teh | Bumpless build-up layer (bbul) semiconductor package with ultra-thin dielectric layer |
US11324254B2 (en) | 2014-10-22 | 2022-05-10 | Nicoventures Trading Limited | Inhalator and cartridge thereof |
US9230726B1 (en) | 2015-02-20 | 2016-01-05 | Crane Electronics, Inc. | Transformer-based power converters with 3D printed microchannel heat sink |
US11865246B2 (en) | 2015-02-27 | 2024-01-09 | Nicoventures Trading Limited | Apparatus for generating an inhalable medium |
US11511056B2 (en) | 2015-10-02 | 2022-11-29 | Nicoventures Trading Limited | Apparatus for generating an inhalable medium |
WO2017111792A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Fabrication and use of through silicon vias on double sided interconnect device |
US11251156B2 (en) | 2015-12-23 | 2022-02-15 | Intel Corporation | Fabrication and use of through silicon vias on double sided interconnect device |
US11594524B2 (en) | 2015-12-23 | 2023-02-28 | Intel Corporation | Fabrication and use of through silicon vias on double sided interconnect device |
US11672276B2 (en) | 2016-11-02 | 2023-06-13 | British American Tobacco (Investments) Limited | Aerosol provision article |
WO2019132956A1 (en) * | 2017-12-29 | 2019-07-04 | Intel Corporation | Microelectronic assemblies |
US11769751B2 (en) | 2017-12-29 | 2023-09-26 | Intel Corporation | Microelectronic assemblies |
Also Published As
Publication number | Publication date |
---|---|
US9691728B2 (en) | 2017-06-27 |
WO2013101242A1 (en) | 2013-07-04 |
US20150171044A1 (en) | 2015-06-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9691728B2 (en) | BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility | |
US9812422B2 (en) | Embedded die-down package-on-package device | |
US20180145014A1 (en) | High density second level interconnection for bumpless build up layer (bbul) packaging technology | |
TWI692048B (en) | Backside drill embedded die substrate | |
US9159714B2 (en) | Package on wide I/O silicon | |
US9601421B2 (en) | BBUL material integration in-plane with embedded die for warpage control | |
TWI482257B (en) | A multi-chip package having a substrate with a plurality of vertically embedded die and a process forming the same | |
US9842832B2 (en) | High density interconnection of microelectronic devices | |
EP3772098A1 (en) | Multi-die ultrafine pitch patch architecture and method of making | |
TW201624650A (en) | Integrated circuit die having backside passive components and methods associated therewith | |
US20130313727A1 (en) | Multi-stacked bbul package | |
US11688665B2 (en) | Thermal management solutions for stacked integrated circuit devices | |
US20190385931A1 (en) | Thermal management solutions for stacked integrated circuit devices | |
US11482472B2 (en) | Thermal management solutions for stacked integrated circuit devices | |
US11417586B2 (en) | Thermal management solutions for substrates in integrated circuit packages | |
US9708178B2 (en) | Integration of laminate MEMS in BBUL coreless package | |
US10541200B2 (en) | Over-molded IC packages with embedded voltage reference plane and heater spreader | |
KR20210018039A (en) | Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making | |
US20230187424A1 (en) | Fan-out semiconductor package | |
US20230207471A1 (en) | Composite ic die package including an electro-thermo-mechanical die (etmd) with through substrate vias | |
US11621208B2 (en) | Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices | |
US11823972B2 (en) | Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NICKERSON, ROBERT M.;TAO, MIN;GUZEK, JOHN S.;REEL/FRAME:027800/0501 Effective date: 20120206 |
|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NICKERSON, ROBERT M.;TAO, MIN;GUZEK, JOHN S.;REEL/FRAME:030811/0170 Effective date: 20120206 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |