JP4271590B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4271590B2 JP4271590B2 JP2004011666A JP2004011666A JP4271590B2 JP 4271590 B2 JP4271590 B2 JP 4271590B2 JP 2004011666 A JP2004011666 A JP 2004011666A JP 2004011666 A JP2004011666 A JP 2004011666A JP 4271590 B2 JP4271590 B2 JP 4271590B2
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- via hole
- semiconductor element
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- conductor
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Description
また、絶縁性基材の他方の面は、半導体素子(チップ)の電極端子が形成されている側と反対側の面に対応する部分において突出しており、言い換えると、チップの周囲の領域における絶縁性基材の厚さは相対的に薄く形成されているので、当該領域に形成されるビアホール(第1のビアホール)の深さを減らすことができる。つまり、当該ビアホールの形成に使用するレーザの照射時間を短縮できるため、当該ビアホールの径を更に小さくすることができ、パッケージ(半導体装置)の更なる小型化に寄与する。
また、導体の充填と配線層の接続に関連して以下の利点がある。すなわち、第1のビアホールに充填される導体と、第2のビアホールを充填して半導体素子の電極端子に接続され、かつ、導体の他端に接続される配線層とは別々に設けられている(つまり、プロセス的に別工程で充填されている)ので、半導体素子と配線層との接続信頼性を確保できると共に、絶縁性基材に、好適に第1のビアホールを充填する導体を設けることができる。一般に、深さと開口径の異なるビアホールを同時に充填することは、めっき条件等の設定が非常に困難である。特に、開口径が小さく、接続信頼性が要求される半導体素子と接続されるビアホール(本発明における「第2のビアホール」に相当)と、絶縁性基材を貫通するため、このビアホールと比較して深く、かつ開口径が大きいビアホール(本発明における「第1のビアホール」に相当)を、同一のめっき条件で充填することは、実際上不可能に近い。このため、本発明では、上記のように深さと開口径の異なる第1のビアホールと第2のビアホールとに、それぞれ導体と配線層とを別々に設けている。
また、導体22の充填と配線層24の接続に関連して以下の利点がある。すなわち、ビアホールVH1に充填される導体22と、ビアホールVH2を充填して半導体チップ30の電極端子31に接続され、かつ、導体22の他端に接続される配線層24とは別々に設けられている(つまり、図2(f)、図3(b)に示すように別工程で充填されている)ので、チップ30と配線層24との接続信頼性を確保することができ、また、絶縁性基材21に、好適にビアホールVH1を充填する導体22を設けることができる。一般に、深さと開口径の異なるビアホールを同時に充填することは、めっき条件等の設定が非常に困難である。特に、開口径が小さく、接続信頼性が要求される半導体素子と接続されるビアホール(本実施形態における「ビアホールVH2」に相当)と、絶縁性基材を貫通するため、このビアホールと比較して深く、かつ開口径が大きいビアホール(本実施形態における「ビアホールVH1」に相当)を、同一のめっき条件で充填することは、実際上不可能に近い。かかる不都合に対処するため、本実施形態では、上記のように深さと開口径の異なるビアホールVH1とビアホールVH2とに、それぞれ導体22と配線層24とを別々に設けている。
20,20a,20b…配線基板(パッケージ)、
21,21a,21b…絶縁性基材(樹脂層)、
22,22a,22b…導体(Cu等)、
23,23b…パッド部、
24…配線層(Cu等のパターン)、
24P…パッド部、
25…保護膜(ソルダレジスト層)、
26,26b…外部接続端子(はんだバンプ)、
27…導電性基材(銅箔)、
30…半導体素子(チップ)、
31…電極端子、
32…絶縁層(NCP、NCF等)、
40,40a,40b…積層構造の半導体装置、
41…アンダーフィル樹脂、
MR…半導体素子搭載領域、
RP1,RP2…凹部、
VH1,VH2…ビアホール。
Claims (5)
- 絶縁性基材を有する配線基板と、電極端子が前記絶縁性基材の一方の面側に向くように該絶縁性基材内に埋設された少なくとも1個の半導体素子とを備え、
前記半導体素子の周囲の領域において前記絶縁性基材を一方の面から他方の面にかけて貫通する第1のビアホールが形成されるとともに該第1のビアホールに導体が充填され、該導体の一端は、導電性材料からなる第1のパッド部を介して前記絶縁性基材の他方の面側に露出しており、
さらに前記半導体素子が埋設されている領域において前記絶縁性基材の一方の面から前記半導体素子の電極端子に達する第2のビアホールが形成され、前記絶縁性基材の一方の面に、前記第2のビアホールを充填して前記半導体素子の電極端子に接続され、かつ、前記導体の他端に接続される配線層が形成され、該配線層の前記導体の他端に対応する部分に画定される第2のパッド部を露出させて前記配線層及び前記絶縁性基材を覆う保護膜が形成されており、
さらに前記絶縁性基材は、前記半導体素子の電極端子が形成されている側と反対側の面が前記絶縁性基材の他方の面よりも突出するように形成されていることを特徴とする半導体装置。 - 前記第1のパッド部及び第2のパッド部の少なくとも一方に外部接続端子が接合されていることを特徴とする請求項1に記載の半導体装置。
- 請求項2に記載の半導体装置を複数重ね合わせ、隣接する2つの半導体装置間を前記外部接続端子を介して接続したことを特徴とする半導体装置。
- 導電性基材の一方の面の半導体素子搭載領域の周囲の特定の位置に、導電性材料からなる第1のパッド部を形成し、該半導体素子搭載領域の部分に凹部を形成する工程と、
前記半導体素子搭載領域に、電極端子が前記導電性基材と反対側に向くように半導体素子を搭載する工程と、
前記半導体素子を埋め込むように前記導電性基材上に絶縁性基材を形成する工程と、
前記絶縁性基材に、前記第1のパッド部に達するように第1のビアホールを形成する工程と、
前記第1のビアホールに導体を充填する工程と、
前記絶縁性基材の前記半導体素子が埋設されている領域に、前記半導体素子の電極端子に達するように第2のビアホールを形成する工程と、
前記絶縁性基材上に、前記第2のビアホールを充填して前記半導体素子の電極端子に接続され、かつ、前記導体に接続されるように配線層を形成する工程と、
前記配線層の前記導体に対応する部分に画定される第2のパッド部が露出するように前記配線層及び前記絶縁性基材を覆って保護膜を形成する工程と、
前記導電性基材を除去する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記保護膜を形成する工程と前記導電性基材を除去する工程との間に、前記配線層の第2のパッド部に外部接続端子を接合する工程を含むことを特徴とする請求項4に記載の半導体装置の製造方法。
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Families Citing this family (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7208825B2 (en) * | 2003-01-22 | 2007-04-24 | Siliconware Precision Industries Co., Ltd. | Stacked semiconductor packages |
US7371676B2 (en) * | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
US7393770B2 (en) * | 2005-05-19 | 2008-07-01 | Micron Technology, Inc. | Backside method for fabricating semiconductor components with conductive interconnects |
JP4146864B2 (ja) * | 2005-05-31 | 2008-09-10 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体装置及び半導体装置の製造方法 |
US7588992B2 (en) * | 2005-06-14 | 2009-09-15 | Intel Corporation | Integrated thin-film capacitor with etch-stop layer, process of making same, and packages containing same |
US20060289976A1 (en) * | 2005-06-23 | 2006-12-28 | Intel Corporation | Pre-patterned thin film capacitor and method for embedding same in a package substrate |
JP4551321B2 (ja) | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
US7307348B2 (en) | 2005-12-07 | 2007-12-11 | Micron Technology, Inc. | Semiconductor components having through wire interconnects (TWI) |
US7659612B2 (en) | 2006-04-24 | 2010-02-09 | Micron Technology, Inc. | Semiconductor components having encapsulated through wire interconnects (TWI) |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
JP2008159820A (ja) * | 2006-12-22 | 2008-07-10 | Tdk Corp | 電子部品の一括実装方法、及び電子部品内蔵基板の製造方法 |
US7423335B2 (en) | 2006-12-29 | 2008-09-09 | Advanced Chip Engineering Technology Inc. | Sensor module package structure and method of the same |
US8049323B2 (en) * | 2007-02-16 | 2011-11-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip holder with wafer level redistribution layer |
US20090057903A1 (en) * | 2007-03-29 | 2009-03-05 | Yoshio Okayama | Semiconductor module, method for manufacturing semiconductor modules, semiconductor apparatus, method for manufacturing semiconductor apparatuses, and portable device |
US7863088B2 (en) * | 2007-05-16 | 2011-01-04 | Infineon Technologies Ag | Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound |
DE102007022959B4 (de) * | 2007-05-16 | 2012-04-19 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleitervorrichtungen |
JP5496445B2 (ja) * | 2007-06-08 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR100914977B1 (ko) | 2007-06-18 | 2009-09-02 | 주식회사 하이닉스반도체 | 스택 패키지의 제조 방법 |
KR100909322B1 (ko) * | 2007-07-02 | 2009-07-24 | 주식회사 네패스 | 초박형 반도체 패키지 및 그 제조방법 |
KR100905785B1 (ko) * | 2007-07-27 | 2009-07-02 | 주식회사 하이닉스반도체 | 반도체 패키지, 이를 갖는 적층 웨이퍼 레벨 패키지 및적층 웨이퍼 레벨 패키지의 제조 방법 |
KR100885924B1 (ko) * | 2007-08-10 | 2009-02-26 | 삼성전자주식회사 | 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 |
DE102008036561B4 (de) | 2007-08-10 | 2019-02-07 | Samsung Electronics Co., Ltd. | Halbleiterbauelementpackung, Herstellungsverfahren und System |
US8281337B2 (en) * | 2007-12-14 | 2012-10-02 | At&T Intellectual Property I, L.P. | System and method to display media content and an interactive display |
US7851246B2 (en) | 2007-12-27 | 2010-12-14 | Stats Chippac, Ltd. | Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device |
JP2009302427A (ja) * | 2008-06-17 | 2009-12-24 | Shinko Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
TWI392073B (zh) * | 2008-06-17 | 2013-04-01 | Unimicron Technology Corp | 嵌埋有半導體元件之封裝基板之製法 |
KR100996914B1 (ko) * | 2008-06-19 | 2010-11-26 | 삼성전기주식회사 | 칩 내장 인쇄회로기판 및 그 제조방법 |
US7888184B2 (en) * | 2008-06-20 | 2011-02-15 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof |
US8183677B2 (en) * | 2008-11-26 | 2012-05-22 | Infineon Technologies Ag | Device including a semiconductor chip |
JP5179391B2 (ja) * | 2009-01-23 | 2013-04-10 | 新光電気工業株式会社 | 半導体装置の製造方法および半導体装置 |
JP5188426B2 (ja) * | 2009-03-13 | 2013-04-24 | 新光電気工業株式会社 | 半導体装置及びその製造方法、電子装置 |
JP5589314B2 (ja) * | 2009-06-25 | 2014-09-17 | 株式会社リコー | 電子部品モジュールの製造方法 |
TWI528514B (zh) * | 2009-08-20 | 2016-04-01 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
TWI501376B (zh) * | 2009-10-07 | 2015-09-21 | Xintec Inc | 晶片封裝體及其製造方法 |
US8901724B2 (en) * | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8241956B2 (en) * | 2010-03-08 | 2012-08-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming wafer level multi-row etched lead package |
US8338231B2 (en) * | 2010-03-29 | 2012-12-25 | Infineon Technologies Ag | Encapsulated semiconductor chip with external contact pads and manufacturing method thereof |
US8319318B2 (en) * | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8618652B2 (en) * | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
TWI508245B (zh) * | 2010-10-06 | 2015-11-11 | 矽品精密工業股份有限公司 | 嵌埋晶片之封裝件及其製法 |
KR101718011B1 (ko) * | 2010-11-01 | 2017-03-21 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US20120139095A1 (en) * | 2010-12-03 | 2012-06-07 | Manusharow Mathew J | Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same |
US8508037B2 (en) * | 2010-12-07 | 2013-08-13 | Intel Corporation | Bumpless build-up layer and laminated core hybrid structures and methods of assembling same |
US8445990B2 (en) * | 2010-12-10 | 2013-05-21 | Stats Chippac, Ltd. | Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor die |
JP2012146963A (ja) * | 2010-12-20 | 2012-08-02 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法及び半導体パッケージ |
US8421245B2 (en) * | 2010-12-22 | 2013-04-16 | Intel Corporation | Substrate with embedded stacked through-silicon via die |
US8288209B1 (en) * | 2011-06-03 | 2012-10-16 | Stats Chippac, Ltd. | Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die |
DE102011083223B4 (de) * | 2011-09-22 | 2019-08-22 | Infineon Technologies Ag | Leistungshalbleitermodul mit integrierter Dickschichtleiterplatte |
WO2013089754A1 (en) * | 2011-12-15 | 2013-06-20 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages |
US9583365B2 (en) * | 2012-05-25 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming interconnects for three dimensional integrated circuit |
US9059157B2 (en) * | 2012-06-04 | 2015-06-16 | Stats Chippac Ltd. | Integrated circuit packaging system with substrate and method of manufacture thereof |
US9773719B2 (en) | 2012-11-26 | 2017-09-26 | Infineon Technologies Dresden Gmbh | Semiconductor packages and methods of fabrication thereof |
KR102107038B1 (ko) * | 2012-12-11 | 2020-05-07 | 삼성전기주식회사 | 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법 |
US9368438B2 (en) * | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
US9455218B2 (en) * | 2013-03-28 | 2016-09-27 | Intel Corporation | Embedded die-down package-on-package device |
US9000599B2 (en) | 2013-05-13 | 2015-04-07 | Intel Corporation | Multichip integration with through silicon via (TSV) die embedded in package |
GB2524791B (en) * | 2014-04-02 | 2018-10-03 | At & S Austria Tech & Systemtechnik Ag | Placement of component in circuit board intermediate product by flowable adhesive layer on carrier substrate |
JP6417142B2 (ja) * | 2014-07-23 | 2018-10-31 | 株式会社ジェイデバイス | 半導体装置及びその製造方法 |
TWI542263B (zh) * | 2014-07-31 | 2016-07-11 | 恆勁科技股份有限公司 | 中介基板及其製法 |
US10177115B2 (en) | 2014-09-05 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming |
TWI582861B (zh) * | 2014-09-12 | 2017-05-11 | 矽品精密工業股份有限公司 | 嵌埋元件之封裝結構及其製法 |
US9941219B2 (en) | 2014-09-19 | 2018-04-10 | Intel Corporation | Control of warpage using ABF GC cavity for embedded die package |
CN104576579B (zh) * | 2015-01-27 | 2017-12-15 | 江阴长电先进封装有限公司 | 一种三维叠层封装结构及其封装方法 |
US10504736B2 (en) | 2015-09-30 | 2019-12-10 | Texas Instruments Incorporated | Plating interconnect for silicon chip |
US10707171B2 (en) | 2015-12-22 | 2020-07-07 | Intel Corporation | Ultra small molded module integrated with die by module-on-wafer assembly |
TWM524553U (zh) * | 2016-03-21 | 2016-06-21 | Team Expert Man Consulting Service Ltd | 半導體封裝結構 |
US10985098B2 (en) * | 2016-04-25 | 2021-04-20 | Kyocera Corporation | Electronic component mounting substrate, electronic device, and electronic module |
US10811182B2 (en) * | 2016-10-28 | 2020-10-20 | Samsung Electro-Mechanics Co., Ltd. | Inductor and method of manufacturing the same |
JP7024269B2 (ja) * | 2017-09-12 | 2022-02-24 | 富士電機株式会社 | 半導体装置、半導体装置の積層体、及び、半導体装置の積層体の搬送方法 |
US20190326159A1 (en) * | 2018-04-20 | 2019-10-24 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same utilizing localized soi formation |
DE102018122515B4 (de) | 2018-09-14 | 2020-03-26 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiteroxid- oder Glas-basierten Verbindungskörpers mit Verdrahtungsstruktur |
US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US20200235066A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11923313B2 (en) | 2019-01-23 | 2024-03-05 | Qorvo Us, Inc. | RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same |
US20200235040A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
IT201900006736A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di fabbricazione di package |
IT201900006740A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di strutturazione di substrati |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6400573B1 (en) * | 1993-02-09 | 2002-06-04 | Texas Instruments Incorporated | Multi-chip integrated circuit module |
US6451624B1 (en) * | 1998-06-05 | 2002-09-17 | Micron Technology, Inc. | Stackable semiconductor package having conductive layer and insulating layers and method of fabrication |
JP3764587B2 (ja) * | 1998-06-30 | 2006-04-12 | 富士通株式会社 | 半導体装置の製造方法 |
JP3833859B2 (ja) * | 1999-10-14 | 2006-10-18 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3813402B2 (ja) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP3772066B2 (ja) * | 2000-03-09 | 2006-05-10 | 沖電気工業株式会社 | 半導体装置 |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
TW511405B (en) * | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
JP4240899B2 (ja) * | 2001-03-26 | 2009-03-18 | Necエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2003049184A1 (en) * | 2001-12-07 | 2003-06-12 | Fujitsu Limited | Semiconductor device and method for manufacturing the same |
TW577160B (en) * | 2002-02-04 | 2004-02-21 | Casio Computer Co Ltd | Semiconductor device and manufacturing method thereof |
JP4135390B2 (ja) * | 2002-04-19 | 2008-08-20 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP4243117B2 (ja) * | 2002-08-27 | 2009-03-25 | 新光電気工業株式会社 | 半導体パッケージとその製造方法および半導体装置 |
JP2004140037A (ja) * | 2002-10-15 | 2004-05-13 | Oki Electric Ind Co Ltd | 半導体装置、及びその製造方法 |
US7141874B2 (en) * | 2003-05-14 | 2006-11-28 | Matsushita Electric Industrial Co., Ltd. | Electronic component packaging structure and method for producing the same |
KR100510556B1 (ko) * | 2003-11-11 | 2005-08-26 | 삼성전자주식회사 | 초박형 반도체 패키지 및 그 제조방법 |
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