TWI528514B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TWI528514B
TWI528514B TW098145455A TW98145455A TWI528514B TW I528514 B TWI528514 B TW I528514B TW 098145455 A TW098145455 A TW 098145455A TW 98145455 A TW98145455 A TW 98145455A TW I528514 B TWI528514 B TW I528514B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor wafer
chip package
carrier substrate
layout
Prior art date
Application number
TW098145455A
Other languages
English (en)
Other versions
TW201108366A (en
Inventor
張恕銘
周正德
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201108366A publication Critical patent/TW201108366A/zh
Application granted granted Critical
Publication of TWI528514B publication Critical patent/TWI528514B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝，特別是有關於一種扇出式(fan-out)晶片封裝體及其製造方法。
隨著電子或光電產品諸如數位相機、具有影像拍攝功能的手機、條碼掃瞄器(bar code reader)以及監視器需求的增加，半導體技術發展的相當快速，且半導體晶片的尺寸有微縮化(miniaturization)的趨勢，而其功能也變得更為複雜。
大多數的半導體晶片通常為了效能上的需求而置放於一密封的封裝體，其有助於操作上的穩定性。然而，由於先進的半導體晶片必須在更小的面積內提供更多的輸入/輸出(I/O)導電墊，因而增加半導體封裝的困難度，使其良率降低。尤其是在晶圓級封裝(wafer level chip scale package,WLCSP)的應用上，當半導體晶片尺寸越來越小時，封裝體的凸塊球距(pitch)以及尺寸會限制位於半導體晶片表面的I/O導電墊數量而妨礙半導體晶片效能的提升。
因此，有必要尋求一種新的封裝體結構，其能夠解決上述的問題。
有鑑於此，本發明一實施例提供一種晶片封裝體，包括：一承載基板以及設置於一承載基板上的至少一半導體晶片。半導體晶片具有複數導電墊，而複數第一重佈局層位於半導體晶片上且電性連接於導電墊。一單層絕緣結構覆蓋承載基板及半導體晶片，且具有複數開口以露出第一重佈局層。複數第二重佈局層設置於單層絕緣結構上，並電性連接至第一重佈局層。一保護層設置於單層絕緣結構上並覆蓋第二重佈局層，具有複數開口以暴露出第二重佈局層。複數導電凸塊對應設置於保護層的開口內而電性連接至第二重佈局層。
本發明另一實施例提供一種晶片封裝體之製造方法，包括：提供至少一半導體晶片於一承載基板上，其中半導體晶片具有複數導電墊；於半導體晶片上形成與導電墊電性連接的複數第一重佈局層；在承載基板上形成一單層絕緣結構，並覆蓋半導體晶片，且跨於第一重佈局層上；定義單層絕緣結構以形成複數第一開口，暴露出第一重佈局層；在單層絕緣結構上形成複數第二重佈局層，使第二重佈局層經由第一開口而電性連接至第一重佈局層；在單層絕緣結構上形成一第一保護層，並覆蓋第二重佈局層；定義第一保護層以形成複數第二開口，暴露出第二重佈局層；以及在第二開口內對應形成複數導電凸塊，使導電凸塊經由第二開口而電性連接至第二重佈局層。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明所提供的實施例僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。在圖式或描述中，相似或相同部份的元件係使用相同或相似的符號表示。再者，圖式中元件的形狀或厚度可擴大，以簡化或是方便標示。此外，未繪示或描述之元件，可以是具有各種熟習該項技藝者所知的形式。
請參照第1G圖，其繪示出根據本發明實施例之晶片封裝體10剖面示意圖。在本發明之封裝體實施例中，其係可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical Systems,MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(physical sensor)。特別是可選擇使用晶圓級封裝製程對影像感測器、發光二極體、太陽能電池、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件、壓力感測器(pressure sensors)、或噴墨頭(ink printer heads)等半導體晶片進行封裝。
上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離的半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之封裝體。
在本實施例中，晶片封裝體10包括：一承載基板200以及至少一半導體晶片100，晶片100可經由一黏著層204而設置於承載基板200上。承載基板200，例如由一空白的矽晶圓(raw silicon wafer)或其他不含電路的半導體基板切割而成。此處，為簡化圖式及說明，僅以單一半導體晶片100表示之。在本實施例中，鄰近半導體晶片100的承載基板200上可具有一防滑結構202，用以作為晶片固定裝置(shifting stopper)。再者，半導體晶片100具有一晶片保護層(passivation)(未繪示)，其包括多個開口以露出複數導電墊100a，用以將半導體晶片100內的電路(未繪示)電性連接至外部電路(未繪示)。此處，為簡化圖式及說明，僅以二個不相鄰的導電墊100a表示之。在一實施例中，兩相鄰的導電墊之間的間隔(space)在15至25微米(μm)的範圍。
此外，在一選擇性的步驟中，可考慮額外形成一保護層102於半導體晶片100之晶片保護層上，以重新形成露出複數導電墊100a的多個開口102a，藉此可調整晶片保護層的開口形狀和尺寸，以符合本實施例之晶圓級封裝所需的規格。例如由氧化矽、氮化矽、或其組合所構成，或是選擇高分子材料，例如，聚醯亞胺樹脂(polyimide)或是苯環丁烯(butylcyclobutene:BCB,道氏化學公司)，上述重新形成之開口102a可以局部露出下方對應的導電墊100a，但尺寸已較晶片保護層的開口為小。以下實施例係以開口102a為例，但並不以此為限。複數扇入式(fan-in)重佈局層206設置於半導體晶片上，其經由保護層102內的開口102a而與對應的導電墊100a電性連接。
一單層絕緣結構208設置於承載基板200上，並覆蓋半導體晶片100、防滑結構202且跨於重佈局層206上，其中單層絕緣結構208具有複數開口208a以局部露出下方對應的重佈局層206。複數重佈局層210設置於單層絕緣結構208上，並經由單層絕緣結構208內的開口208a而與對應的重佈局層206電性連接。不同於扇入式重佈局層206，重佈局層210進一步向外延伸至半導體晶片100外側的單層絕緣結構208上而構成扇出式(fan-out)重佈局層210結構。
一保護層212，例如一防焊層(solder mask)，設置於單層絕緣結構208上並覆蓋重佈局層210，其中保護層212具有複數開口212a以局部露出下方對應的重佈局層210。複數導電凸塊214對應設置於開口212a內，並經由開口212a而電性連接至對應的重佈局層210。
以下配合第1A至1G圖說明根據本發明實施例之晶片封裝體10之製造方法。請參照第1A圖，提供一承載基板200，例如一空白的矽晶圓(raw silicon wafer)或其他不含電路的半導體基板，其上具有複數晶片承載區(未繪示)，用以對應放置複數半導體晶片。複數防滑結構對應設置於鄰近晶片承載區的承載基板200上。此處，為簡化圖式及說明，僅以一晶片承載區及與其相鄰的一防滑結構202表示之。防滑結構202可包括金屬材料或絕緣材料。前者可藉由電鍍製程而形成，而後者則可藉由微影製程或其他習知沉積製程而形成。
第2A至2C圖係繪示出根據本發明不同實施例之防滑結構，其中相同於第1A圖的部件係使用相同的標號並省略其說明。在一實施例中，如第2A圖所示，防滑結構202可為一環形物且環繞晶片承載區(如虛線區所示)，用以在後續接合晶片時，作為晶片對準標記及/或晶片固定裝置。在另一實施例中，防滑結構202可為複數島狀物且環繞晶片承載區，防滑結構202包括至少二個島狀物，分別鄰近於晶片承載區的二個對邊或二個鄰邊。舉例而言，如第2B圖所示，防滑結構202的島狀物具有矩形的上視輪廓且鄰近於晶片承載區的所有邊緣。在另一實施例中，防滑結構202包括至少二個島狀物，且分別鄰近於晶片承載區的二個對角。舉例而言，如第2C圖所示，防滑結構202的島狀物具有L形的上視輪廓且鄰近於晶片承載區的四個角落。
接下來，提供複數半導體晶片，用以在後續步驟中設置於承載基板200上對應的晶片承載區。此處，為簡化圖式及說明，僅以一半導體晶片100表示之，如第1B圖所示。半導體晶片100本身係覆蓋有一晶片保護層(未繪示)，其具有複數個開口以暴露出複數導電墊100a，用以將半導體晶片100內的積體電路(未繪示)電性連接至外部電路(未繪示)。此處，為簡化圖式及說明，僅以二個不相鄰的導電墊100a表示之。需注意的是相鄰的導電墊之間的間隔在15至25微米(μm)的範圍。
在一實施例中，可以額外增加一道重新定義開口的步驟，例如於晶片上方再另外覆蓋一層保護層102，例如由氧化矽、氮化矽、或其組合所構成，或是由高分子材料構成，接著定義出複數開口102a以局部露出下方對應的導電墊100a。在本實施例中，開口102a的尺寸及形狀可以配合晶圓級封裝所需規格，例如藉由調整開口102a的尺寸來縮小晶片保護層開口的尺寸，擴大兩開口的間距。
請參照第1C圖，半導體晶片100透過防滑結構202作為對準標記，並藉由一黏著層204設置於承載基板200上對應的晶片承載區(如第2A、2B或2C圖的虛線區所示)，其中由於黏著層在硬化之前可能使晶片發生偏移，進而使後續製程發生對位偏差，因此藉由圍繞晶片的防滑結構202，例如形成鄰近於或稍微接觸半導體晶片100之防滑結構202，其中，由於黏著材料受到晶片與防滑結構202兩者之緊迫，而使黏著材料之流動受到侷限，因此晶片的位移量控制在可容許誤差之內。在另一實施例中，亦可透過防滑結構202作為對準標記，以使晶片精準地設置於承載基板200上。在本實施例中，黏著層204可包括：導電銀膠、晶片貼膜(DAF:Die attach film)、或是環氧樹脂層。接著，複數重佈局層206形成於保護層102上，其中重佈局層206經由保護層102的開口102a而電性連接至對應的導電墊100a。重佈局層206可包括鋁、銅、或其他習知導線材料並藉由習知沉積技術所形成，例如電鍍、無電鍍、或物理氣相沉積。在本實施例中，重佈局層206係於半導體晶片100放置於承載基板200之後，形成於該半導體晶片上。在另一實施例中，重佈局層206亦可於半導體晶片100放置於承載基板200之前，先形成於半導體晶片100上。在一實施例中，重佈局層206並不會延伸超出至晶片外。
請參照第1D圖，在承載基板200上形成一單層絕緣結構208，並覆蓋半導體晶片100。單層絕緣結構208可包括環氧樹脂材料、聚醯亞胺樹脂(polyimide)或是苯環丁烯(butylcyclobutene:BCB,道氏化學公司)，並藉由習知技術所形成，例如貼合或塗佈。接著，藉由習知微影及蝕刻技術在單層絕緣結構208內形成複數開口208a，以局部露出下方對應的重佈局層206。
請參照第1E圖，在單層絕緣結構208上形成複數扇出(fan-out)重佈局層210，其中重佈局層210經由單層絕緣結構208的開口208a而電性連接至對應的重佈局層206。同樣地，重佈局層210可包括鋁、銅、或其他習知導線材料並藉由習知沉積技術所形成，例如電鍍、無電鍍或物理氣相沉積。再者，重佈局層210可向外延伸至半導體晶片100外側的單層絕緣結構208上。
請參照第1F圖，在單層絕緣結構208上形成一保護層212，例如一防焊層，並覆蓋重佈局層210。接著，藉由習知微影及蝕刻製程，在保護層212內形成複數開口212a以局部露出下方對應的重佈局層210。
請參照第1G圖，在保護層212的開口212a內對應形成複數導電凸塊214，使導電凸塊214經由開口212a而電性連接至對應的重佈局層210。之後，切割由矽晶圓構成的承載基底200及其上方的單層絕緣結構208，以形成獨立的晶片封裝體10。
根據上述之一實施例中，由於半導體晶片100係設置於承載基底200上，因此導電凸塊214除了可設置於半導體晶片100正上方之外，亦可透過扇出式重佈局層210形成於半導體晶片100外側的承載基底200上方。亦即，晶片封裝體10的終端接觸區(即，導電凸塊214所設置之處)無須侷限於半導體晶片100正上方，因而可增加終端接觸區的數量，以因應高效能的晶片封裝需求。再另一實施例中，承載基底200上圍繞晶片的防滑結構202，可使半導體晶片100於固定在承載基底200上時可能發生之偏移受到有效控制，以維持或改善晶片封裝體的良率。此外，於另一實施例中，採用單層絕緣結構208可同時作為兩半導體晶片100之間的填充物以及覆蓋重佈局層206的保護層，可簡化製程步驟並降低製造成本。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶片封裝體
100‧‧‧半導體晶片
100a‧‧‧導電墊
102、212‧‧‧保護層
102a、208a、212a‧‧‧開口
200‧‧‧承載基底
202‧‧‧防滑結構
204‧‧‧黏著層
206、210‧‧‧重佈局層
208‧‧‧單層絕緣結構
214‧‧‧導電凸塊
第1A至1G圖係繪示出根據本發明實施例之晶片封裝體之製造方法剖面示意圖；及第2A至2C圖係繪示出根據本發明不同實施例之防滑結構。
10．．．晶片封裝體
100．．．半導體晶片
100a．．．導電墊
102、212．．．保護層
102a、208a、212a．．．開口
200．．．承載基底
202．．．防滑結構
204．．．黏著層
206、210．．．重佈局層
208．．．單層絕緣結構
214．．．導電凸塊

Claims (19)

  1. 一種晶片封裝體，包括：一承載基板；至少一半導體晶片，設置於該承載基板上，其中該半導體晶片具有複數導電墊；複數第一重佈局層，包含一第一部分與一第二部分，對應設置於該半導體晶片上並與該等導電墊電性連接；一單層絕緣結構，設置於該承載基板上，該單層絕緣結構直接接觸承載基板，並覆蓋該半導體晶片，且跨於該等第一重佈局層上，且該單層絕緣結構覆蓋該等第一重佈局層的該第一部分，其中該單層絕緣結構具有複數第一開口以暴露出該等第一重佈局層的該第二部分；複數第二重佈局層，設置於該單層絕緣結構上，並經由該等第一開口而電性連接至該等第一重佈局層；一第一保護層，設置於該單層絕緣結構上並覆蓋該等第二重佈局層，其中該第一保護層具有複數第二開口以暴露出該等第二重佈局層；以及複數導電凸塊，對應設置於該等第二開口內，並經由該等第二開口而電性連接至該等第二重佈局層。
  2. 如申請專利範圍第1項所述之晶片封裝體，更包括一防滑結構，設置於該承載基板上且圍繞該半導體晶片。
  3. 如申請專利範圍第2項所述之晶片封裝體，其中該防滑結構包括至少二個島狀物，分別鄰近於或接觸該半導體晶片的二個對角、二個對邊或二個鄰邊。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該防滑結構之島狀物具有L型之上視輪廓且鄰近於該半導體晶片之角落。
  5. 如申請專利範圍第2項至第4項任一項所述之晶片封裝體，其中該防滑結構包括金屬材料或絕緣材料。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中該等第一重佈局層為扇入型重佈局層，且該等第二重佈局層為扇出型重佈局層。
  7. 如申請專利範圍第6項所述之晶片封裝體，更包括一第二保護層，設置於該半導體晶片與該等第一重佈局層之間，其中該第二保護層具有複數第三開口，暴露出該等導電墊，且該等第一重佈局層經由該等第三開口而電性連接至該等導電墊。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該承載基板為一空白矽基底。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該單層絕緣結構包括環氧樹脂材料、聚醯亞胺樹脂或苯環丁烯。
  10. 一種晶片封裝體之製造方法，包括：提供至少一半導體晶片於一承載基板上，其中該半導體晶片具有複數導電墊；於該半導體晶片上形成與該等導電墊電性連接的複數第一重佈局層，該等第一重佈局層包含一第一部分與一第二部分；在該承載基板上形成一單層絕緣結構，該單層絕緣 結構直接接觸承載基板，並覆蓋該半導體晶片，且跨於該等第一重佈局層上，且該單層絕緣結構覆蓋該等第一重佈局層的該第一部分；定義該單層絕緣結構以形成複數第一開口，暴露出該等第一重佈局層的該第二部分；在該單層絕緣結構上形成複數第二重佈局層，使該等第二重佈局層經由該等第一開口而電性連接至該等第一重佈局層；在該單層絕緣結構上形成一第一保護層，並覆蓋該等第二重佈局層；定義該第一保護層以形成複數第二開口，暴露出該等第二重佈局層；以及在該等第二開口內對應形成複數導電凸塊，使該等導電凸塊經由該等第二開口而電性連接至該等第二重佈局層。
  11. 如申請專利範圍第10項所述之晶片封裝體之製造方法，更包括在該承載基板上形成一防滑結構，且該防滑結構圍繞該半導體晶片。
  12. 如申請專利範圍第11項所述之晶片封裝體之製造方法，其中該防滑結構包括至少二個島狀物，分別鄰近於或接觸該半導體晶片的二個對角、二個對邊或二個鄰邊。
  13. 如申請專利範圍第12項所述之晶片封裝體之製造方法，其中該防滑結構之島狀物具有L型之上視輪廓且鄰近於該半導體晶片之角落。
  14. 如申請專利範圍第11項至第13項任一項所述之晶片封裝體之製造方法，其中該防滑結構包括金屬材料或絕緣材料。
  15. 如申請專利範圍第14項所述之晶片封裝體之製造方法，其中該等第一重佈局層為扇入型重佈局層，且該等第二重佈局層為扇出型重佈局層。
  16. 如申請專利範圍第15項所述之晶片封裝體之製造方法，更包括：在該半導體晶片與該等第一重佈局層之間形成一第二保護層；定義該第二保護層以形成複數第三開口，以暴露出該等導電墊，且該等第一重佈局層經由該等第三開口而電性連接至該等導電墊。
  17. 如申請專利範圍第10項所述之晶片封裝體之製造方法，其中該承載基板為一空白晶圓。
  18. 如申請專利範圍第10項所述之晶片封裝體之製造方法，其中該單層絕緣結構包括環氧樹脂材料、聚醯亞胺樹脂或苯環丁烯。
  19. 如申請專利範圍第16項所述之晶片封裝體之製造方法，其中該第一重佈局層係於該半導體晶片提供於該承載基板上之前，形成於該半導體晶片上。
TW098145455A 2009-08-20 2009-12-29 晶片封裝體及其製造方法 TWI528514B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23556709P 2009-08-20 2009-08-20

Publications (2)

Publication Number Publication Date
TW201108366A TW201108366A (en) 2011-03-01
TWI528514B true TWI528514B (zh) 2016-04-01

Family

ID=43604655

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098145455A TWI528514B (zh) 2009-08-20 2009-12-29 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (1) US8633582B2 (zh)
CN (1) CN101996958B (zh)
TW (1) TWI528514B (zh)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8604600B2 (en) * 2011-12-30 2013-12-10 Deca Technologies Inc. Fully molded fan-out
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US8922021B2 (en) 2011-12-30 2014-12-30 Deca Technologies Inc. Die up fully molded fan-out wafer level packaging
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US8288203B2 (en) * 2011-02-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump
US9117682B2 (en) 2011-10-11 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and structures thereof
CN102522342A (zh) * 2011-12-27 2012-06-27 日月光半导体制造股份有限公司 半导体结构及其制造方法
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
WO2013102146A1 (en) 2011-12-30 2013-07-04 Deca Technologies, Inc. Die up fully molded fan-out wafer level packaging
CN103679108B (zh) 2012-09-10 2018-12-11 霍尼韦尔国际公司 具有多个图像传感器的光学标记读取装置
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9236320B2 (en) * 2013-06-28 2016-01-12 Xintec Inc. Chip package
DE102013113191A1 (de) * 2013-11-28 2015-05-28 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung optoelektronischer Bauelemente für die Kapselung von Schichten
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
TWI597786B (zh) * 2013-12-19 2017-09-01 矽品精密工業股份有限公司 半導體封裝結構及其製法
CN103745937B (zh) * 2014-02-08 2016-06-01 华进半导体封装先导技术研发中心有限公司 扇出型圆片级封装的制作工艺
US9263302B2 (en) 2014-02-21 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure for packaging and a method of forming
US9230936B2 (en) * 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
CN106233460A (zh) * 2014-03-10 2016-12-14 德卡技术股份有限公司 包括加厚的再分布层的半导体器件及其制造方法
US9318429B2 (en) 2014-03-31 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated structure in wafer level package
CN105304507B (zh) * 2015-11-06 2018-07-31 通富微电子股份有限公司 扇出晶圆级封装方法
CN105390471B (zh) * 2015-11-06 2018-06-12 通富微电子股份有限公司 扇出晶圆级封装结构
KR102508551B1 (ko) * 2015-12-11 2023-03-13 에스케이하이닉스 주식회사 웨이퍼 레벨 패키지 및 제조 방법
DE102016103324A1 (de) * 2016-02-25 2017-08-31 Osram Opto Semiconductors Gmbh Videowand-Modul und Verfahren zum Herstellen eines Videowand-Moduls
US9899342B2 (en) * 2016-03-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, redistribution circuit structure, and method of fabricating the same
US10170341B1 (en) * 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
DE102017126028B4 (de) 2017-06-30 2020-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gehäuse und Herstellungsverfahren mit einem Trennfilm als Isolierfilm
TWI655697B (zh) * 2017-07-26 2019-04-01 台星科股份有限公司 晶圓級尺寸封裝結構保護的電極層後製作的封裝方法
EP3557608A1 (en) * 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects
CN111430313A (zh) * 2020-05-11 2020-07-17 上海天马微电子有限公司 半导体封装及其制作方法
CN113707566A (zh) * 2021-08-16 2021-11-26 矽磐微电子(重庆)有限公司 半导体结构的制造方法及半导体结构
CN114551257B (zh) * 2022-02-21 2023-09-22 江苏卓胜微电子股份有限公司 扇出型晶圆级封装方法及封装结构
CN114551258A (zh) * 2022-02-21 2022-05-27 江苏卓胜微电子股份有限公司 扇出型晶圆级封装方法及封装结构

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US6400573B1 (en) * 1993-02-09 2002-06-04 Texas Instruments Incorporated Multi-chip integrated circuit module
US20010018800A1 (en) * 1999-09-17 2001-09-06 George Tzanavaras Method for forming interconnects
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
KR20080031522A (ko) * 2000-02-25 2008-04-08 이비덴 가부시키가이샤 다층프린트배선판 및 다층프린트배선판의 제조방법
JP3772066B2 (ja) * 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
SG99939A1 (en) * 2000-08-11 2003-11-27 Casio Computer Co Ltd Semiconductor device
US6423570B1 (en) * 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6841413B2 (en) * 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
US6709897B2 (en) * 2002-01-15 2004-03-23 Unimicron Technology Corp. Method of forming IC package having upward-facing chip cavity
TW557521B (en) * 2002-01-16 2003-10-11 Via Tech Inc Integrated circuit package and its manufacturing process
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
TW550800B (en) * 2002-05-27 2003-09-01 Via Tech Inc Integrated circuit package without solder mask and method for the same
US6972964B2 (en) * 2002-06-27 2005-12-06 Via Technologies Inc. Module board having embedded chips and components and method of forming the same
TW554500B (en) * 2002-07-09 2003-09-21 Via Tech Inc Flip-chip package structure and the processing method thereof
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
CA2464078C (en) * 2002-08-09 2010-01-26 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
JP2004140037A (ja) * 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
US6872589B2 (en) * 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same
JP3891123B2 (ja) * 2003-02-06 2007-03-14 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、及び半導体装置の製造方法
JP4016340B2 (ja) * 2003-06-13 2007-12-05 ソニー株式会社 半導体装置及びその実装構造、並びにその製造方法
TWI221327B (en) * 2003-08-08 2004-09-21 Via Tech Inc Multi-chip package and process for forming the same
US7514767B2 (en) * 2003-12-03 2009-04-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7459781B2 (en) * 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
TWI225670B (en) * 2003-12-09 2004-12-21 Advanced Semiconductor Eng Packaging method of multi-chip module
JP4271590B2 (ja) * 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
JP2005332896A (ja) * 2004-05-19 2005-12-02 Oki Electric Ind Co Ltd 半導体装置、チップサイズパッケージ、半導体装置の製造方法、及びチップサイズパッケージの製造方法
US7444735B2 (en) * 2004-06-15 2008-11-04 Chartered Semiconductor Manufacturing Ltd. Process for manufacturing an integrated circuit system
TWI237885B (en) * 2004-10-22 2005-08-11 Phoenix Prec Technology Corp Semiconductor device having carrier embedded with chip and method for fabricating the same
US7238602B2 (en) * 2004-10-26 2007-07-03 Advanced Chip Engineering Technology Inc. Chip-size package structure and method of the same
US7547969B2 (en) * 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US7253528B2 (en) * 2005-02-01 2007-08-07 Avago Technologies General Ip Pte. Ltd. Trace design to minimize electromigration damage to solder bumps
US7973398B2 (en) * 2005-05-12 2011-07-05 Unimicron Technology Corp. Embedded chip package structure with chip support protruding section
TW200642015A (en) * 2005-05-25 2006-12-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and fabrication method thereof
JP4395775B2 (ja) * 2005-10-05 2010-01-13 ソニー株式会社 半導体装置及びその製造方法
US7397121B2 (en) * 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
TWI279897B (en) * 2005-12-23 2007-04-21 Phoenix Prec Technology Corp Embedded semiconductor chip structure and method for fabricating the same
TWI310968B (en) * 2006-02-09 2009-06-11 Phoenix Prec Technology Corp Electrically connecting structure of circuit board with semiconductor chip embedded therein
TWI301663B (en) * 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof
US7588951B2 (en) * 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US7453148B2 (en) * 2006-12-20 2008-11-18 Advanced Chip Engineering Technology Inc. Structure of dielectric layers in built-up layers of wafer level package
CN101236943B (zh) * 2007-02-01 2010-04-21 日月光半导体制造股份有限公司 内埋芯片的散热型无芯板薄型基板及其制造方法
US20080191297A1 (en) * 2007-02-12 2008-08-14 Advanced Chip Engineering Technology Inc. Wafer level image sensor package with die receiving cavity and method of the same
US20080217761A1 (en) * 2007-03-08 2008-09-11 Advanced Chip Engineering Technology Inc. Structure of semiconductor device package and method of the same
TWI351743B (en) * 2007-03-09 2011-11-01 Unimicron Technology Corp Chip carrier structure having semiconductor chip e
US8384199B2 (en) * 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
KR100905785B1 (ko) * 2007-07-27 2009-07-02 주식회사 하이닉스반도체 반도체 패키지, 이를 갖는 적층 웨이퍼 레벨 패키지 및적층 웨이퍼 레벨 패키지의 제조 방법
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI345276B (en) * 2007-12-20 2011-07-11 Chipmos Technologies Inc Dice rearrangement package structure using layout process to form a compliant configuration
TWI368304B (en) * 2007-12-28 2012-07-11 Unimicron Technology Corp Package substrate having embedded semiconductor element and fabrication method thereof
TW200930173A (en) * 2007-12-31 2009-07-01 Phoenix Prec Technology Corp Package substrate having embedded semiconductor element and fabrication method thereof
US8084302B2 (en) * 2008-03-07 2011-12-27 Stats Chippac, Ltd. Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
US8659154B2 (en) * 2008-03-14 2014-02-25 Infineon Technologies Ag Semiconductor device including adhesive covered element
KR101517598B1 (ko) * 2008-07-21 2015-05-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8129835B2 (en) * 2009-09-04 2012-03-06 Unimicron Technology Corp. Package substrate having semiconductor component embedded therein and fabrication method thereof
TWI501376B (zh) * 2009-10-07 2015-09-21 Xintec Inc 晶片封裝體及其製造方法

Also Published As

Publication number Publication date
TW201108366A (en) 2011-03-01
CN101996958A (zh) 2011-03-30
US8633582B2 (en) 2014-01-21
US20110042796A1 (en) 2011-02-24
CN101996958B (zh) 2012-08-15

Similar Documents

Publication Publication Date Title
TWI528514B (zh) 晶片封裝體及其製造方法
TWI501376B (zh) 晶片封裝體及其製造方法
TWI515838B (zh) 電子元件封裝體及其製造方法
US8728871B2 (en) Method for fabricating electronic device package
US8502393B2 (en) Chip package and method for forming the same
US8410614B2 (en) Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same
CN111883481A (zh) 3d封装件结构及其形成方法
US9761510B2 (en) Chip package and method for forming the same
US8541877B2 (en) Electronic device package and method for fabricating the same
TWI624039B (zh) 晶片封裝體及其製造方法
JP5249080B2 (ja) 半導体装置
US20170207194A1 (en) Chip package and method for forming the same
TWI565011B (zh) 晶片側壁單離應力釋放之晶片尺寸封裝構造及其製造方法
TWI470708B (zh) 電子元件封裝體及其製作方法
TWI539568B (zh) 電子元件封裝體及其製造方法
US20230411301A1 (en) Electronic device and method of manufacturing the same
KR100969444B1 (ko) 패터닝된 수지봉합부를 갖는 웨이퍼 레벨 칩 스케일 패키지및 그 제조방법
TW202105657A (zh) 半導體裝置及製造半導體裝置的方法
US20100327426A1 (en) Semiconductor chip package and method of manufacturing the same
JP2010171311A (ja) 半導体装置およびその製造方法