TWI515838B - 電子元件封裝體及其製造方法 - Google Patents

電子元件封裝體及其製造方法 Download PDF

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Publication number
TWI515838B
TWI515838B TW100110324A TW100110324A TWI515838B TW I515838 B TWI515838 B TW I515838B TW 100110324 A TW100110324 A TW 100110324A TW 100110324 A TW100110324 A TW 100110324A TW I515838 B TWI515838 B TW I515838B
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Taiwan
Prior art keywords
protective layer
abutting portion
electronic component
component package
semiconductor wafer
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TW100110324A
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English (en)
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TW201133725A (en
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張恕銘
樓百堯
溫英男
劉建宏
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精材科技股份有限公司
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Publication of TW201133725A publication Critical patent/TW201133725A/zh
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Description

電子元件封裝體及其製造方法
本發明係有關於一種電子封裝，特別是有關於一種電子元件封裝體及其製造方法。
隨著電子或光電產品諸如數位相機、具有影像拍攝功能的手機、條碼掃瞄器(bar code reader)以及監視器需求的增加，半導體技術發展的相當快速，且半導體晶片的尺寸有微縮化(miniaturization)的趨勢，而其功能也變得更為複雜。
半導體晶片通常為了效能上的需求而置放於同一密封的封裝體，以助於操作上的穩定。再者，由於高效能或多功能的半導體晶片通常需要更多的輸入/輸出(I/O)導電墊結構，因此必須縮小電子元件封裝體中導電凸塊之間的間距，以在電子元件封裝體中增加導電凸塊數量。如此一來，半導體封裝的困難度會增加而使其良率降低。
因此，有必要尋求一種新的封裝體結構，其能夠解決上述的問題。
有鑑於此，本發明一實施例提供一種電子元件封裝體，包括：至少一半導體晶片，具有一第一表面及與其相對的一第二表面，其中至少一重佈線設置於半導體晶片的第一表面上，且電性連接於半導體晶片的至少一導電墊結構；至少一抵接部，設置於重佈線上並與其電性接觸；一鈍化保護層，覆蓋半導體晶片的第一表面，且環繞抵接部；以及一基板，貼附於半導體晶片的第二表面。
本發明另一實施例提供一種電子元件封裝體之製造方法，包括：提供至少一半導體晶片，其具有一第一表面及與其相對的一第二表面，其中半導體晶片內具有至少一接觸開口延伸至第一表面且具有至少一導電墊結構位於接觸開口底部；將半導體晶片的第二表面貼附於一基板；在半導體晶片的第一表面上形成至少一重佈線，且經由接觸開口而電性連接導電墊結構；在半導體晶片的第一表面上覆蓋一犧牲圖案層，其中犧牲圖案層具有一開口以局部露出重佈線；在開口內形成至少一抵接部，其中抵接部與露出的重佈線電性接觸；去除犧牲圖案層；以及在半導體晶片的第一表面上覆蓋一鈍化保護層，使鈍化保護層環繞抵接部。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明所提供的實施例僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。在圖式或描述中，相似或相同部份的元件係使用相同或相似的符號表示。再者，圖式中元件的形狀或厚度可擴大，以簡化或是方便標示。此外，未繪示或描述之元件，可以是具有各種熟習該項技藝者所知的形式。
第1I、2、3及4圖，其繪示出根據本發明不同實施例之電子元件封裝體剖面示意圖。在本發明之封裝體實施例中，其係可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical Systems,MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(physical sensor)。特別是可選擇使用晶圓級封裝製程對影像感測器、發光二極體、太陽能電池、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件、壓力感測器(pressure sensors)、或噴墨頭(ink printer heads)等半導體晶片進行封裝。
上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離的半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之封裝體。
請參照第1I圖，電子元件封裝體包括：至少一半導體晶片100，例如CMOS影像感測(CMOS image sensor,CIS)晶片、微機電系統(MEMS)、或其他習知的積體電路晶片。此處，半導體晶片100係以CMOS影像感測晶片作為範例說明。半導體晶片100具有一第一表面10及與其相對的一第二表面20。再者，半導體晶片100包括：一鈍化保護層102鄰近於第二表面20以及複數導電墊結構104設置於鈍化保護層102內。導電墊結構104透過內連接(interconnect)結構(未繪示)而與半導體晶片100內的電路(未繪示)電性連接。複數重佈線(RDL)110設置於半導體晶片100的第一表面10上，且電性連接至鈍化保護層102內對應的導電墊結構104。在一實施例中，重佈線110經由一絕緣層106，例如氧化矽層，而與半導體晶片100內的半導體基板絕緣。再者，重佈線110與導電墊結構104之間具有一晶種層108，其包括鈦、銅、或其合金。
至少一抵接部114設置於對應的重佈線110上且與其直接接觸。亦即，重佈線110與抵接部114之間不具有黏著層。在本實施例中，抵接部114具有單層結構，且作為半導體晶片100與外部電路(例如，印刷電路板(printed circuit board,PCB))的電性連接部。再者，抵接部114可由銅、鎳、金、或其組合或習知的焊料所構成。
一導電保護層116覆蓋重佈線110與抵接部114的表面，其可由鎳、金、或其合金所構成，用以防止重佈線110與抵接部114因環境因素而氧化的問題。
一鈍化保護層118，例如一感光防焊(solder mask)層，覆蓋半導體晶片100的第一表面10。鈍化保護層118具有複數開口118a，使鈍化保護層118經由開口118a而環繞抵接部114。特別的是表面覆蓋導電保護層116的抵接部114突出於鈍化保護層118的上表面，以作為導電凸塊(bump)。再者，表面覆蓋導電保護層116的抵接部114與鈍化保護層118的開口118a內壁之間具有一間隙，使鈍化保護層118不與表面覆蓋導電保護層116的抵接部114接觸。
一基板200貼附於半導體晶片100的第二表面20上。當基板200是用以承載半導體晶片100時可以選擇但不限於導熱基板，例如金屬基板、空白的矽基板(raw silicon substrate)或其他不含電路的半導體基板。當基板200係用以供光線進出時，則可選擇但不限於透光基板，例如玻璃、石英、塑膠、或蛋白石(opal)，其中濾光片及/或抗反射層可選擇形成於此透光基板上。在本實施例中，基板200為一透光基板且可經由圍堰結構(dam)或黏著材料層而貼附至半導體晶片100。此處，係以圍堰結構202作為範例說明。由圍堰結構202所構成的空腔(cavity)204通常會對應於半導體晶片100(如，CIS晶片)的感光區(未繪示)。
請參照第2圖，其繪示出根據本發明另一實施例之電子元件封裝體剖面示意圖，其中相同於第1I圖的部件係使用相同的標號並省略其相關說明。不同於第1I圖所示的實施例，抵接部114與重佈線110的表面並未覆蓋導電保護層116。因此，在本實施例中，抵接部114與重佈線110可選擇不易氧化的導電材料，例如含鎳、金、鈦或銅之可能組合之合金材料。
請參照第3圖，其繪示出根據本發明又另一實施例之電子元件封裝體剖面示意圖，其中相同於第1I圖的部件係使用相同的標號並省略其相關說明。在本實施例中，抵接部114與重佈線110的表面可覆蓋或不覆蓋導電保護層116(分別如第1I及2圖所示)。而不同於上述實施例之處在於鈍化保護層118局部覆蓋抵接部114或表面覆蓋導電保護層116的抵接部114的上表面。亦即，鈍化保護層118與抵接部114或表面覆蓋導電保護層116的抵接部114接觸。當半導體晶片100組裝於一外部電路(例如，PCB)時，抵接部114係透過PCB上的凸塊的電性接觸來進行半導體晶片10與PCB之間的電性連接。
請參照第4圖，其繪示出根據本發明又另一實施例之電子元件封裝體剖面示意圖，其中相同於第1I圖的部件係使用相同的標號並省略其相關說明。在本實施例中，抵接部114與重佈線110的表面可覆蓋或不覆蓋導電保護層116(分別如第1I及2圖所示)。不同於上述實施例，鈍化保護層118由非感光性防焊材料所構成。再者，鈍化保護層118的上表面不低於抵接部114或表面覆蓋導電保護層116的抵接部114的上表面。舉例而言，鈍化保護層118的上表面大體上切齊於抵接部114的上表面。再者，鈍化保護層118與抵接部114或表面覆蓋導電保護層116的抵接部114的側壁直接接觸，使兩者之間不具有空隙。
以下配合第1A至1I圖說明根據本發明實施例之電子元件封裝體之製造方法。請參照第1A圖，提供一半導體晶圓1000，包括複數半導體晶片區，例如CIS晶片區。此處，為簡化圖式，僅以單一半導體晶片區表示之。半導體晶圓1000具有一第一表面10及與其相對的一第二表面20。再者，每一半導體晶片區包括：一鈍化保護層102鄰近於第二表面20以及複數導電墊結構104設置於鈍化保護層102內。
再者，提供一基板2000，例如由玻璃、石英、塑膠、或蛋白石(opal)所構成的透光晶圓，其中濾光片及/或抗反射層可選擇形成於此透光晶圓上。將基板2000透過圍堰結構或黏著材料層而貼附於半導體晶圓1000的第二表面20上。在本實施例中，基板2000經由圍堰結構202而貼附至半導體晶圓1000。由圍堰結構202所構成的空腔204通常會對應於半導體晶片區(如，CIS晶片區)的感光區(未繪示)。
請參照第1B圖，將半導體晶圓1000蝕刻、銑削(milling)、磨削(grinding)、或研磨(polishing)至所需的厚度，例如100微米(μm)。之後，藉由習知微影即蝕刻技術，在半導體晶圓1000的每一半導體晶片區內形成複數接觸開口(via opening)100a，其對應於每一半導體晶片區的導電墊結構104。接觸開口100a自半導體晶圓1000的第一表面10往第二表面20延伸且露出導電墊結構104。
請參照第1C圖，可藉由化學氣相沉積(chemical vapor deposition,CVD)或其他適用的沉積技術，在半導體晶圓1000的第一表面10及每一接觸開口100a的內表面順應性形成一絕緣層106，例如氧化矽層，用以提供後續重佈局線與半導體晶圓1000之間的電性隔離。之後，去除接觸開口100a底部的絕緣層106，以露出導電墊結構104。在另一實施例中，如第1J圖所示，100a底部之絕緣層106可未完全被移除，但仍可露出導電墊結構104。第1C與1J圖所示之絕緣層106結構可選擇性地應用於本發明，為簡化說明，以下圖示採用第1C圖所揭示之絕緣層106結構描述。
請參照第1D圖，在絕緣層106的表面上順應性形成一晶種(seed)層108，使晶種層108經由接觸開口100a而與導電墊結構104作電性接觸。在一實施例中，晶種層108可由鈦、鈦化鎢、鉻、銅、或其合金所構成，用以加強後續重佈局線與導電墊結構104之間的附著性。之後，可藉由電鍍法，在晶種層108形成一導電層(未繪示)，其材質包括銅、鎳、金或其組合。接著，藉由微影及蝕刻製程以圖案化晶種層108上的導電層，以在半導體晶圓1000的第一表面10上形成複數重佈局線110。每一重佈局線110經由接觸開口100a內的晶種層108而與對應的導電墊結構104電性連接。
請參照第1E圖，在半導體晶圓1000的第一表面10上覆蓋一犧牲圖案層112，例如乾膜(dry film)或濕式光阻材料。在本實施例中，犧牲圖案層112具有複數開口112a，每一開口112a局部露出對應的重佈局線110。
請參照第1F圖，可藉由電鍍法，在每一開口112a內形成具有單層結構的抵接部114，使抵接部114與重佈局線110直接接觸。抵接部114的材質可包括銅、鎳、金、焊料或其組合。可以理解的是犧牲圖案層112的厚度取決於抵接部114的所需高度。在一實施例中，犧牲圖案層112的厚度約為50微米。
請參照第1G圖，去除犧牲圖案層112。接著，去除未被重佈局線110所覆蓋的晶種層108。之後，可藉由化學電鍍(electroless plating)，在重佈局線110及抵接部114的表面形成一導電保護層116，如第1H圖所示。在本實施例中，導電保護層116可由鎳、金、或其合金所構成。
請參照第1I圖，在半導體晶圓1000的第一表面10上形成一鈍化保護層118。鈍化保護層118具有複數開口118a，使鈍化保護層118環繞表面覆蓋有導電保護層116的抵接部114。在本實施例中，鈍化保護層118可由感光的防焊材料所構成。因此，在進行微影製程之後，表面覆蓋有導電保護層116的抵接部114突出於鈍化保護層118的上表面，以作為作為後續半導體晶片與外部電路(例如，PCB)的電性連接部，例如凸塊。再者，鈍化保護層118與表面覆蓋有導電保護層116的抵接部114之間具有一間隙，使鈍化保護層118不與表面覆蓋有導電保護層116的抵接部114接觸。之後，對貼附於基板2000的半導體晶圓100進行切割製程，以形成複數具有至少一半導體晶片100的電子元件封裝體。此處，為簡化圖式，僅以單一電子元件封裝體表示之。
需注意的是在一實施例中，在局部去除晶種層108之後(如第1G圖所示)，可省略形成導電保護層116(如第1H圖所示)的步驟，而依序進行鈍化保護層118的製作及切割製程，而完成電子元件封裝體(如第2圖所示)之製作。
在另一實施例中，當鈍化保護層118由感光的防焊材料所構成時，也可藉由微影製程，使鈍化保護層118覆蓋局部覆蓋抵接部114或是表面具有導電保護層116的抵接部114。之後，進行切割製程，而完成電子元件封裝體(如第3圖所示)之製作。
又另一實施例中，可在局部去除晶種層108之後(如第1G圖所示)，在半導體晶圓1000的第一表面10上形成一鈍化保護層118，使鈍化保護層118完全覆蓋重佈局線110及抵接部114或表面具有導電保護層116的重佈局線110及抵接部114。在此實施例中，鈍化保護層118由非感光的防焊材料所構成。接著，可對鈍化保護層118進行一研磨製程，例如化學機械研磨(chemical mechanical polishing,CMP)製程，直至露出抵接部114或表面具有導電保護層116的抵接部114。在此實施例中，鈍化保護層118的上表面不低於抵接部114或表面覆蓋導電保護層116的抵接部114的上表面。再者，鈍化保護層118與抵接部114或表面覆蓋導電保護層116的抵接部114的側壁直接接觸，使兩者之間不具有空隙。之後，進行切割製程，而完成電子元件封裝體(如第4圖所示)之製作。
根據上述實施例，由於半導體晶片中用於與外部電路電性連接的抵接部係形成於犧牲圖案層(例如，乾膜)的開口中，因此可在微影製程能力(process capability)容許之下，大幅縮小抵接部的間距，進而在一既定尺寸的電子元件封裝體中相對增加抵接部的數量。亦即，上述實施例可符合高效能或多功能的半導體晶片的需求。再者，抵接部可透過電鍍法直接形成於重佈局線上且在製作鈍化保護層之前形成，相較於習知技術中由印刷法(printing)所製作的導電凸塊而言，無需在導電凸塊與重佈局線之間額外製作底層凸塊金屬化(under-bump metallization,UBM)層。因此，可進一步降低電子元件封裝體之製作成本。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．第一表面
20．．．第二表面
100．．．半導體晶片
100a．．．接觸開口
106．．．絕緣層
108．．．晶種層
110．．．重佈局線
112．．．犧牲圖案層
112a、118a．．．開口
114．．．抵接部
116．．．導電保護層
200、2000．．．基板
102、118．．．鈍化保護層
104．．．導電墊結構
202．．．圍堰
204．．．空腔
1000．．．半導體晶圓
第1A至1I圖係繪示出根據本發明實施例之電子元件封裝體之製造方法剖面示意圖；
第1J圖係繪示出根據本發明另一實施例之電子元件封裝體中間製造階段中其中一剖面示意圖；及
第2至4圖係繪示出根據本發明不同實施例之電子元件封裝體剖面示意圖。
10．．．第一表面
20．．．第二表面
100．．．半導體晶片
100a．．．接觸開口
102、118．．．鈍化保護層
104．．．導電墊結構
106．．．絕緣層
108．．．晶種層
110．．．重佈局線
114．．．抵接部
116．．．導電保護層
118a．．．開口
200．．．基板
202．．．圍堰
204．．．空腔

Claims (18)

  1. 一種電子元件封裝體，包括：至少一半導體晶片，具有一第一表面及與其相對的一第二表面，其中至少一重佈線設置於該半導體晶片的該第一表面上，且電性連接於該半導體晶片的至少一導電墊結構；至少一抵接部，設置於該重佈線上並與其電性接觸，以作為一導電凸塊；一導電保護層，至少覆蓋該抵接部的上表面；一鈍化保護層，覆蓋該半導體晶片的該第一表面，且環繞該抵接部；以及一基板，貼附於該半導體晶片的該第二表面。
  2. 如申請專利範圍第1項所述之電子元件封裝體，其中該抵接部突出於該鈍化保護層的上表面，且該抵接部與該鈍化保護層之間具有一間隙。
  3. 如申請專利範圍第1項所述之電子元件封裝體，其中該鈍化保護層局部覆蓋該抵接部的上表面。
  4. 如申請專利範圍第1項所述之電子元件封裝體，其中該鈍化保護層的上表面不低於該抵接部的上表面，且該鈍化保護層與該抵接部的側壁直接接觸。
  5. 如申請專利範圍第1項所述之電子元件封裝體，其中該抵接部與該重佈線之材質相同。
  6. 如申請專利範圍第1項所述之電子元件封裝體，其中該導電保護層由鎳、金、或其合金所構成。
  7. 如申請專利範圍第1項所述之電子元件封裝體，更 包括一晶種層設置於該重佈線與該導電墊之間。
  8. 如申請專利範圍第1項所述之電子元件封裝體，其中該鈍化保護層由感光或非感光防焊材料所構成。
  9. 如申請專利範圍第1項所述之電子元件封裝體，其中該半導體晶片內具有至少一接觸開口延伸至該第一表面且該導電墊結構位於該接觸開口底部。
  10. 一種電子元件封裝體之製造方法，包括：提供至少一半導體晶片，其具有一第一表面及與其相對的一第二表面，其中該半導體晶片內具有至少一接觸開口延伸至該第一表面且具有至少一導電墊結構位於該接觸開口底部；將該半導體晶片的該第二表面貼附於一基板；在該半導體晶片的該第一表面上形成至少一重佈線，且經由該接觸開口而電性連接該導電墊結構；在該半導體晶片的該第一表面上覆蓋一犧牲圖案層，其中該犧牲圖案層具有一開口以局部露出該重佈線；在該開口內形成至少一抵接部，其中該抵接部與該露出的重佈線電性接觸，以作為一導電凸塊；去除該犧牲圖案層；於去除該犧牲圖案層之後，在該抵接部的上表面形成一導電保護層；以及在該半導體晶片的該第一表面上覆蓋一鈍化保護層，使該鈍化保護層環繞該抵接部。
  11. 如申請專利範圍第10項所述之電子元件封裝體之製造方法，其中該犧牲圖案層包括乾膜或濕式光阻材 料。
  12. 如申請專利範圍第10項所述之電子元件封裝體之製造方法，其中該抵接部與該重佈線之材質相同。
  13. 如申請專利範圍第10項所述之電子元件封裝體之製造方法，該抵接部突出於該鈍化保護層的上表面，且該抵接部與該鈍化保護層之間具有一間隙。
  14. 如申請專利範圍第10項所述之電子元件封裝體之製造方法，其中該鈍化保護層局部覆蓋該抵接部的上表面。
  15. 如申請專利範圍第10項所述之電子電子元件封裝體之製造方法，其中該鈍化保護層的上表面不低於該抵接部的上表面，且該鈍化保護層與該抵接部的側壁直接接觸。
  16. 如申請專利範圍第15項所述之電子元件封裝體之製造方法，其中該抵接部包括銅、鎳、金、焊料、或其組合且該抵接部係藉由電鍍法而形成的。
  17. 如申請專利範圍第16項所述之電子元件封裝體之製造方法，更包括在該重佈線與該導電墊結構之間形成一晶種層。
  18. 如申請專利範圍第10項所述之電子元件封裝體之製造方法，其中該鈍化保護層由感光或非感光防焊材料所構成。
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