TWI581325B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TWI581325B
TWI581325B TW104123721A TW104123721A TWI581325B TW I581325 B TWI581325 B TW I581325B TW 104123721 A TW104123721 A TW 104123721A TW 104123721 A TW104123721 A TW 104123721A TW I581325 B TWI581325 B TW I581325B
Authority
TW
Taiwan
Prior art keywords
chip package
pad
wafer
blocking member
insulating layer
Prior art date
Application number
TW104123721A
Other languages
English (en)
Other versions
TW201618176A (zh
Inventor
劉建宏
溫英男
李士儀
姚皓然
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201618176A publication Critical patent/TW201618176A/zh
Application granted granted Critical
Publication of TWI581325B publication Critical patent/TWI581325B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/2633Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02311Additive methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02371Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • H01L2224/06182On opposite sides of the body with specially adapted redistribution layers [RDL]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/14104Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/432Mechanical processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4502Disposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Description

晶片封裝體及其製造方法
本發明是有關一種晶片封裝體及其製造方法。
指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor)需利用平坦的感測面來偵測訊號。若感測面不平整,會影響感測裝置偵測時的準確度。舉例來說,當指頭按壓於指紋感測裝置的感測面時,若感測面不平整,將難以偵測到完整的指紋。
此外,上述的感測裝置在製作時,會先於晶圓中形成矽穿孔(Through Silicon Via;TSV),使焊墊從矽穿孔裸露。接著,會以化學氣相沉積法(Chemical Vapor Deposition;CVD)在焊墊上與矽穿孔的壁面上形成絕緣層。之後,還需透過圖案化製程於焊墊上的絕緣層形成開口。一般而言圖案化製程包含曝光、顯影與蝕刻製程。在後續製程中,重佈線層便可形成在絕緣層上並電性連接絕緣層開口中的焊墊。
然而,化學氣相沉積與圖案化製程均需耗費大量的製程時間與機台的成本。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式,一種晶片封裝體包含晶片、雷射阻擋件、絕緣層、重佈線層、阻隔層與導電結構。晶片具有焊墊、及相對的第一表面與第二表面。焊墊位於第一表面上。第二表面具有第一穿孔,使焊墊從第一穿孔裸露。雷射阻擋件位於焊墊上。絕緣層位於第二表面上與第一穿孔中。絕緣層具有相對第二表面的第三表面。絕緣層與焊墊共同具有第二穿孔,使雷射阻擋件從第二穿孔裸露。重佈線層位於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。阻隔層位於第三表面上與重佈線層上。阻隔層具有開口,使重佈線層從開口裸露。導電結構位於開口中的重佈線層上,使導電結構電性連接焊墊。
本發明之一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式,一種晶片封裝體的製造方法包含下列步驟。(a)提供晶圓與雷射阻擋件,其中晶圓具有焊墊、及相對的第一表面與第二表面,且焊墊位於第一表面,雷射阻擋件位於焊墊上。(b)暫時接合支撐件於晶圓的第一表面。(c)在晶圓之第二表面中形成第一穿孔,使焊墊從第一穿孔裸露。(d)形成絕緣層於晶圓之第二表面上與第一穿孔中,其中絕緣層具有相對第二表面的第三表面。(e)使用雷射貫穿絕緣層與焊墊以形成第二穿孔,其中雷射由雷射阻擋件阻 擋,且雷射阻擋件從第二穿孔裸露。(f)電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。
在本發明上述實施方式中,由於雷射阻擋件位於焊墊上,因此當雷射貫穿絕緣層與焊墊時,雷射可由雷射阻擋件阻擋,並於絕緣層與焊墊中形成裸露雷射阻擋件的第二穿孔。待第二穿孔形成後,便可電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。其中,第二穿孔的壁面包含焊墊的表面與絕緣層的表面,使得重佈線層可電性連接焊墊。本發明之晶片封裝體及其製造方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程,能節省製程的時間與機台的成本。此外,晶片的第一表面未經額外的加工,因此平坦性佳,可提升晶片封裝體偵測時的準確度。
100‧‧‧晶片封裝體
110‧‧‧晶片
110a‧‧‧晶圓
111‧‧‧第一表面
112‧‧‧焊墊
113‧‧‧第二表面
114‧‧‧第一穿孔
115‧‧‧表面
120‧‧‧雷射阻擋件
122‧‧‧凹面
140‧‧‧絕緣層
141‧‧‧第三表面
142‧‧‧表面
150‧‧‧第二穿孔
152‧‧‧壁面
160‧‧‧重佈線層
170‧‧‧阻隔層
172‧‧‧開口
180‧‧‧導電結構
190‧‧‧空穴
210‧‧‧支撐件
2-2‧‧‧線段
D1~D2‧‧‧孔徑
D3~D5‧‧‧厚度
L1‧‧‧線段
L2‧‧‧線段
S1~S6‧‧‧步驟
第1圖繪示根據本發明一實施方式之晶片封裝體的俯視圖。
第2圖繪示第1圖之晶片封裝體沿線段2-2的剖面圖。
第3圖繪示第2圖之晶片封裝體的局部放大圖。
第4圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。
第5圖繪示根據本發明一實施方式之晶圓與雷射阻擋件的剖面圖。
第6圖繪示第5圖之晶圓接合支撐件後的剖面圖。
第7圖繪示第6圖之晶圓形成第一穿孔後的剖面圖。
第8圖繪示第7圖之晶圓的第二表面上與第一穿孔中形成絕緣層後的剖面圖。
第9圖繪示第8圖之絕緣層與焊墊中形成第二穿孔後的剖面圖。
第10圖繪示第9圖之絕緣層的第三表面、第二穿孔的壁面與雷射阻擋件上形成重佈線層後的剖面圖。
第11圖繪示第10圖之絕緣層與重佈線層上形成阻隔層後的剖面圖。
第12圖繪示第11圖之重佈線層上形成導電結構後的剖面圖。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片封裝體100的俯視圖。第2圖繪示第1圖之晶片封裝體100沿線段2-2的剖面圖。同時參閱第1圖與第2圖,晶片封裝體100包含感測晶片110、雷射阻擋件120、絕緣層140、重佈線層 160(Redistribution Layer;RDL)、阻隔層170與導電結構180。晶片110具有焊墊112、及相對的第一表面111與第二表面113。第一表面111為感測面。焊墊112位於第一表面111上。第二表面113具有第一穿孔114,使焊墊112從第一穿孔114裸露。雷射阻擋件120位於焊墊112上。絕緣層140位於晶片110的第二表面113上與第一穿孔114中,且絕緣層140具有相對第二表面113的第三表面141。絕緣層140與焊墊112共同具有第二穿孔150,使雷射阻擋件120從第二穿孔150裸露。重佈線層160位於絕緣層140的第三表面141上、第二穿孔150的壁面上與第二穿孔150中的雷射阻擋件120上。阻隔層170位於絕緣層140的第三表面141上與重佈線層160上。阻隔層170具有開口172,使重佈線層160從阻隔層170的開口172裸露。導電結構180位於開口172中的重佈線層160上,使導電結構180藉由重佈線層160電性連接焊墊112。
在本實施方式中,晶片封裝體100可以為指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor),但並不用以限制本發明。晶片110的材質可以包含矽。雷射阻擋件120的材質可以包含金,例如為金球(gold ball)。重佈線層160的材質可以包含銅,可採用電鍍的方式形成。絕緣層140的材質可以包含環氧樹脂(epoxy)。
第3圖繪示第2圖之晶片封裝體100的局部放大圖。雷射阻擋件120具有朝向重佈線層160的凹面122。第二穿孔150可利用雷射貫穿絕緣層140與焊墊112而形成。藉由雷射的使用,第二穿孔150的孔徑D2可小於第一穿孔114的孔徑 D1,對於微小化設計有所助益。由於第二穿孔150由雷射形成,因此雷射阻擋件120具有朝向第二穿孔150的凹面122,且第二穿孔150的壁面152與雷射阻擋件120的凹面122均為粗糙面。第二穿孔150的壁面152包含焊墊112的表面115與絕緣層140的表面142。也就是說,壁面152為焊墊112與絕緣層140朝向第二穿孔150的表面。
由於雷射阻擋件120位於焊墊112上,因此當雷射貫穿絕緣層140與焊墊112時,雷射可由雷射阻擋件120阻擋,並於絕緣層140與焊墊112中形成裸露雷射阻擋件120的第二穿孔150。待第二穿孔150形成後,便可以化鍍加電鍍重佈線層160於絕緣層140的第三表面141上、第二穿孔150的壁面152上與第二穿孔150中的雷射阻擋件120上,使得重佈線層160可電性連接焊墊112。也就是說,重佈線層160可穿過焊墊112而延伸至雷射阻擋件120的凹面122,使得重佈線層160至少部分凸出於焊墊112,如第3圖所示。
此外,由於重佈線層160係以電鍍的方式形成,因此重佈線層160在絕緣層140之第三表面141上的厚度D3大於重佈線層160在第二穿孔150的壁面152上的厚度D4,且重佈線層160在第二穿孔150的壁面152上的厚度D4大於重佈線層160在雷射阻擋件120上的厚度D5。在本實施方式中,晶片封裝體100還具有空穴190,且空穴190位於阻隔層170與第二穿孔150中的重佈線層160之間。
在以下敘述中,將說明晶片封裝體100的製造方法。
第4圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。晶片封裝體的製造方法包含下列步驟。在步驟S1中,提供晶圓與雷射阻擋件,其中晶圓具有焊墊、及相對的第一表面與第二表面,且焊墊位於第一表面,雷射阻擋件位於焊墊上。接著在步驟S2中,暫時接合支撐件於晶圓的第一表面。之後在步驟S3中,在晶圓之第二表面中形成第一穿孔,使焊墊從第一穿孔裸露。接著在步驟S4中,形成絕緣層於晶圓之第二表面上與第一穿孔中,其中絕緣層具有相對第二表面的第三表面。之後在步驟S5中,使用雷射貫穿絕緣層與焊墊以形成第二穿孔,其中雷射由雷射阻擋件阻擋,且雷射阻擋件從第二穿孔裸露。最後在步驟S6中,電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。在以下敘述中,將說明上述步驟。
第5圖繪示根據本發明一實施方式之晶圓110a與雷射阻擋件120的剖面圖。晶圓110a意指切割後可形成複數個第2圖的晶片110的半導體基板。首先,可提供晶圓110a與雷射阻擋件120,其中晶圓110a具有焊墊112、及相對的第一表面111與第二表面113,且焊墊112位於第一表面111,雷射阻擋件120位於焊墊112上。在本實施方式中,可透過打一導線(例如金線)於晶圓110a之焊墊112上,接著切除部分導線,使晶圓110a之焊墊112上殘留另一部分導線而形成雷射阻擋件120。雷射阻擋件120例如為金球。
第6圖繪示第5圖之晶圓110a接合支撐件210後的剖面圖。同時參閱第5圖與第6圖,待第5圖的結構形成後,可 暫時接合支撐件210於晶圓110a的第一表面111。支撐件210可提供晶圓110a支撐力,防止晶圓110a在後續製程中因受力而破裂。待接合支撐件210於晶圓110a後,可研磨晶圓110a之第二表面113,以減薄晶圓110a的厚度。
第7圖繪示第6圖之晶圓110a形成第一穿孔114後的剖面圖。同時參閱第6圖與第7圖,接著,可在晶圓110a之第二表面113中形成第一穿孔114,使焊墊112從第一穿孔114裸露。在此步驟中,可採用蝕刻製程在晶圓110a中形成第一穿孔114,例如乾蝕刻製程。
第8圖繪示第7圖之晶圓110a的第二表面113上與第一穿孔114中形成絕緣層140後的剖面圖。同時參閱第7圖與第8圖,待第一穿孔114形成後,便可形成絕緣層140於晶圓110a之第二表面113上與第一穿孔114中,其中絕緣層140具有相對第二表面113的第三表面141。在此步驟中,絕緣層140可採用印刷的方式形成於晶圓110a之第二表面113上與第一穿孔114中。接著,設計者可依需求塗佈、壓印、製模或研磨絕緣層140之第三表面141,以減薄絕緣層140的厚度。
第9圖繪示第8圖之絕緣層140與焊墊112中形成第二穿孔150後的剖面圖。同時參閱第8圖與第9圖,待第8圖的結構形成後,可使用雷射貫穿絕緣層140與焊墊112以形成第二穿孔150。雷射可由焊墊112上的雷射阻擋件120阻擋,使雷射阻擋件120從第二穿孔150裸露。此外,雷射係對準第一穿孔114與雷射阻擋件120發射,因此第二穿孔150可由第一穿孔114環繞。
第10圖繪示第9圖之絕緣層140的第三表面141、第二穿孔150的壁面與雷射阻擋件120上形成重佈線層160後的剖面圖。同時參閱第9圖與第10圖,待第二穿孔150形成於絕緣層140與焊墊112中後,可電鍍重佈線層160於絕緣層140的第三表面141上、第二穿孔150的壁面上與第二穿孔150中的雷射阻擋件120上。
第11圖繪示第10圖之絕緣層140與重佈線層160上形成阻隔層170後的剖面圖。同時參閱第10圖與第11圖,待第10圖的結構形成後,可形成阻隔層170於絕緣層140的第三表面141上與重佈線層160上。接著,可圖案化阻隔層170以形成開口172,使部分的重佈線層160可從阻隔層170的開口172裸露。
第12圖繪示第11圖之重佈線層160上形成導電結構180後的剖面圖。同時參閱第11圖與第12圖,待阻隔層170的開口172形成後,可形成導電結構180於開口172中的重佈線層160上,使得導電結構180可透過重佈線層160電性連接焊墊112。在此步驟後,便可移除晶圓110a的第一表面111上的支撐件210。
最後,可沿線段L1、L2切割晶圓110a、絕緣層140與阻隔層170,以形成第2圖之晶片封裝體100。
本發明之晶片封裝體及其製造方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程,能節省製程的時間與機台的成本。此外,晶片的第一表面未經額外的加工,因此平坦性佳,可提升晶片封裝體偵測時的準確度。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片封裝體
110‧‧‧晶片
111‧‧‧第一表面
112‧‧‧焊墊
113‧‧‧第二表面
114‧‧‧第一穿孔
120‧‧‧雷射阻擋件
140‧‧‧絕緣層
141‧‧‧第三表面
150‧‧‧第二穿孔
160‧‧‧重佈線層
170‧‧‧阻隔層
172‧‧‧開口
180‧‧‧導電結構
190‧‧‧空穴

Claims (18)

  1. 一種晶片封裝體,包含:一晶片,具有一焊墊、及相對的一第一表面與一第二表面,其中該焊墊位於該第一表面上,該第二表面具有一第一穿孔,使該焊墊從該第一穿孔裸露;一雷射阻擋件,位於該焊墊上;一絕緣層,位於該第二表面上與該第一穿孔中,該絕緣層具有相對該第二表面的一第三表面,該絕緣層與該焊墊共同具有一第二穿孔,使該雷射阻擋件從該第二穿孔裸露;該雷射阻擋件具有朝向該第二穿孔的一凹面;一重佈線層,位於該第三表面上、該第二穿孔的一壁面上與該第二穿孔中的該雷射阻擋件上,其中該重佈線層穿過該焊墊而延伸至該雷射阻擋件的該凹面,使得該重佈線層至少部分凸出於該焊墊;一阻隔層,位於該第三表面上與該重佈線層上,該阻隔層具有一開口,使該重佈線層從該開口裸露;以及一導電結構,位於該開口中的該重佈線層上,使該導電結構電性連接該焊墊。
  2. 如請求項1所述之晶片封裝體,其中該雷射阻擋件的材質包含金。
  3. 如請求項1所述之晶片封裝體,其中該第二穿孔的孔徑小於該第一穿孔的孔徑。
  4. 如請求項1所述之晶片封裝體,具有一空穴,且該空穴位於該阻隔層與該第二穿孔中的該重佈線層之間。
  5. 如請求項1所述之晶片封裝體,其中該第二穿孔的該壁面為一粗糙面。
  6. 如請求項1所述之晶片封裝體,其中該雷射阻擋件的該凹面為一粗糙面。
  7. 如請求項1所述之晶片封裝體,其中該重佈線層在該絕緣層之該第三表面上的厚度大於該重佈線層在該第二穿孔的該壁面上的厚度。
  8. 如請求項1所述之晶片封裝體,其中該重佈線層在該第二穿孔的該壁面上的厚度大於該重佈線層在該雷射阻擋件上的厚度。
  9. 如請求項1所述之晶片封裝體,其中該絕緣層的材質包含環氧樹脂。
  10. 一種晶片封裝體的製造方法,包含:(a)提供一晶圓與一雷射阻擋件,其中該晶圓具有一焊墊、及相對的一第一表面與一第二表面,該焊墊位於該第一表面,該雷射阻擋件位於該焊墊上;(b)暫時接合一支撐件於該晶圓的該第一表面; (c)在該晶圓之該第二表面中形成一第一穿孔,使該焊墊從該第一穿孔裸露;(d)形成一絕緣層於該晶圓之該第二表面上與該第一穿孔中,其中該絕緣層具有相對該第二表面的一第三表面;(e)使用一雷射貫穿該絕緣層與該焊墊以形成一第二穿孔,其中該雷射由該雷射阻擋件阻擋,且該雷射阻擋件從該第二穿孔裸露,該雷射阻擋件具有朝向該第二穿孔的一凹面;以及(f)電鍍一重佈線層於該絕緣層的該第三表面上、該第二穿孔的一壁面上與該第二穿孔中的該雷射阻擋件上,其中該重佈線層穿過該焊墊而延伸至該雷射阻擋件的該凹面,使得該重佈線層至少部分凸出於該焊墊。
  11. 如請求項10所述之晶片封裝體的製造方法,更包含:形成一阻隔層於該絕緣層的該第三表面上與該重佈線層上;以及圖案化該阻隔層以形成一開口,使該重佈線層從該開口裸露。
  12. 如請求項11所述之晶片封裝體的製造方法,更包含:形成一導電結構於該開口中的該重佈線層上。
  13. 如請求項11所述之晶片封裝體的製造方法,更包含:切割該晶圓、該絕緣層與該阻隔層,以形成該晶片封裝體。
  14. 如請求項10所述之晶片封裝體的製造方法,更包含:打一導線於該晶圓之該焊墊上;以及切除部分該導線,使該晶圓之該焊墊上殘留另一部分該導線而形成該雷射阻擋件。
  15. 如請求項10所述之晶片封裝體的製造方法,更包含:研磨該晶圓之該第二表面。
  16. 如請求項10所述之晶片封裝體的製造方法,其中該步驟(d)包含:印刷該絕緣層於該晶圓之該第二表面上與該第一穿孔中。
  17. 如請求項10所述之晶片封裝體的製造方法,更包含:塗佈、壓印、製模或研磨該絕緣層之該第三表面。
  18. 如請求項10所述之晶片封裝體的製造方法,更包含:移除該晶圓的該第一表面上的該支撐件。
TW104123721A 2014-11-12 2015-07-22 晶片封裝體及其製造方法 TWI581325B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201462078876P 2014-11-12 2014-11-12

Publications (2)

Publication Number Publication Date
TW201618176A TW201618176A (zh) 2016-05-16
TWI581325B true TWI581325B (zh) 2017-05-01

Family

ID=55912834

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104123721A TWI581325B (zh) 2014-11-12 2015-07-22 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (2) US9543233B2 (zh)
CN (1) CN105590916B (zh)
TW (1) TWI581325B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
TWI603447B (zh) 2014-12-30 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI617992B (zh) * 2016-06-29 2018-03-11 關鍵禾芯科技股份有限公司 指紋辨識裝置及其製造方法
TWI623049B (zh) * 2016-11-04 2018-05-01 英屬開曼群島商鳳凰先驅股份有限公司 封裝基板及其製作方法
CN109087897A (zh) 2017-06-13 2018-12-25 精材科技股份有限公司 晶片封装体及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201349362A (zh) * 2012-05-18 2013-12-01 Xintec Inc 晶片封裝體及其形成方法
TW201428946A (zh) * 2013-01-10 2014-07-16 Xintec Inc 影像感測晶片封裝體及其製作方法
TW201432865A (zh) * 2013-02-08 2014-08-16 Xintec Inc 晶片封裝結構及其製作方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP2002111083A (ja) * 2000-09-29 2002-04-12 Aisin Seiki Co Ltd 熱電モジュール及びその製造方法
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
US8253230B2 (en) * 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP2009295676A (ja) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd 半導体装置及びその製造方法
US7800238B2 (en) * 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US8193632B2 (en) * 2008-08-06 2012-06-05 Industrial Technology Research Institute Three-dimensional conducting structure and method of fabricating the same
US8889548B2 (en) * 2008-09-30 2014-11-18 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
US8395267B2 (en) * 2008-10-30 2013-03-12 Nxp B.V. Through-substrate via and redistribution layer with metal paste
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
CN101807662B (zh) * 2009-02-18 2012-09-05 财团法人工业技术研究院 热电元件及其制作方法、芯片堆叠结构及芯片封装结构
CN101996978B (zh) * 2009-08-20 2014-04-09 精材科技股份有限公司 芯片封装体及其形成方法
JP5532394B2 (ja) * 2009-10-15 2014-06-25 セイコーエプソン株式会社 半導体装置及び回路基板並びに電子機器
US8471367B2 (en) * 2009-11-12 2013-06-25 Panasonic Corporation Semiconductor device and method for manufacturing semiconductor device
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8710680B2 (en) * 2010-03-26 2014-04-29 Shu-Ming Chang Electronic device package and fabrication method thereof
US8847380B2 (en) * 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) * 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
JP2012099548A (ja) * 2010-10-29 2012-05-24 Fujikura Ltd 貫通配線基板の製造方法及び貫通配線基板
US8736066B2 (en) * 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
TWI408837B (zh) * 2011-02-08 2013-09-11 Subtron Technology Co Ltd 封裝載板及其製作方法
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8900994B2 (en) * 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8894868B2 (en) * 2011-10-06 2014-11-25 Electro Scientific Industries, Inc. Substrate containing aperture and methods of forming the same
US8466062B2 (en) * 2011-11-02 2013-06-18 Globalfoundries Singapore Pte Ltd TSV backside processing using copper damascene interconnect technology
US8872196B2 (en) * 2011-12-19 2014-10-28 Xintec Inc. Chip package
US8796829B2 (en) * 2012-09-21 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
EP2772939B1 (en) * 2013-03-01 2016-10-19 Ams Ag Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation
US9093462B2 (en) * 2013-05-06 2015-07-28 Qualcomm Incorporated Electrostatic discharge diode
KR101514137B1 (ko) * 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
EP2871456B1 (en) * 2013-11-06 2018-10-10 Invensense, Inc. Pressure sensor and method for manufacturing a pressure sensor
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
TWI603447B (zh) * 2014-12-30 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201349362A (zh) * 2012-05-18 2013-12-01 Xintec Inc 晶片封裝體及其形成方法
TW201428946A (zh) * 2013-01-10 2014-07-16 Xintec Inc 影像感測晶片封裝體及其製作方法
TW201432865A (zh) * 2013-02-08 2014-08-16 Xintec Inc 晶片封裝結構及其製作方法

Also Published As

Publication number Publication date
US20170076981A1 (en) 2017-03-16
CN105590916A (zh) 2016-05-18
TW201618176A (zh) 2016-05-16
US9543233B2 (en) 2017-01-10
US20160133544A1 (en) 2016-05-12
CN105590916B (zh) 2018-07-31
US9768067B2 (en) 2017-09-19

Similar Documents

Publication Publication Date Title
TWI581325B (zh) 晶片封裝體及其製造方法
TWI534969B (zh) 晶片封裝體及其製造方法
US8018065B2 (en) Wafer-level integrated circuit package with top and bottom side electrical connections
TWI579995B (zh) 晶片封裝體及其製造方法
TWI459485B (zh) 晶片封裝體的形成方法
TWI512930B (zh) 晶片封裝體及其形成方法
TWI582918B (zh) 晶片封裝體及其製造方法
TWI628784B (zh) 應力釋放影像感測器封裝結構及方法
KR101177885B1 (ko) 웨이퍼 레벨 패키징 캡 및 그 제조방법
TWI604570B (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
JP6317475B2 (ja) ウェーハレベルパッケージングのためのダイシング方法、およびウェーハレベルパッケージングに適応したダイシング構造を有する半導体チップ
TWI591764B (zh) 晶片封裝體及其製造方法
US20150054108A1 (en) Wafer level packaging structure for image sensors and wafer level packaging method for image sensors
TW201535551A (zh) 晶片封裝體及其製造方法
US9496297B2 (en) Sensor package with cooling feature and method of making same
TWI540655B (zh) 半導體結構及其製造方法
US9129943B1 (en) Embedded component package and fabrication method
TWI603407B (zh) 晶片封裝體及其製造方法
TWI593069B (zh) 晶片封裝體及其製造方法
TWI607539B (zh) 晶片封裝體及其製造方法
TWI603447B (zh) 晶片封裝體及其製造方法
TWI564961B (zh) 半導體結構及其製造方法
TWI559411B (zh) 半導體裝置及半導體製程
JP6967962B2 (ja) 半導体装置および半導体装置の製造方法
JP7066403B2 (ja) 半導体装置および半導体装置の製造方法