CN102201383A - 电子元件封装体及其制造方法 - Google Patents

电子元件封装体及其制造方法 Download PDF

Info

Publication number
CN102201383A
CN102201383A CN201110073355XA CN201110073355A CN102201383A CN 102201383 A CN102201383 A CN 102201383A CN 201110073355X A CN201110073355X A CN 201110073355XA CN 201110073355 A CN201110073355 A CN 201110073355A CN 102201383 A CN102201383 A CN 102201383A
Authority
CN
China
Prior art keywords
protection layer
electronic component
semiconductor chip
component package
passivation protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201110073355XA
Other languages
English (en)
Other versions
CN102201383B (zh
Inventor
张恕铭
楼百尧
温英男
刘建宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN102201383A publication Critical patent/CN102201383A/zh
Application granted granted Critical
Publication of CN102201383B publication Critical patent/CN102201383B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开一种电子元件封装体及其制造方法，电子元件封装体包括：至少一半导体芯片、至少一抵接部、一钝化保护层以及一基板。半导体芯片具有一第一表面及与其相对的一第二表面，其中至少一重布线设置于半导体芯片的第一表面上，且电连接于半导体芯片的至少一导电垫结构。抵接部设置于重布线上并与其电性接触。钝化保护层覆盖半导体芯片的第一表面且环绕抵接部。基板贴附于半导体芯片的第二表面。本发明也揭示上述电子元件封装体的制造方法。

Description

电子元件封装体及其制造方法
技术领域
本发明涉及一种电子封装，特别是涉及一种电子元件封装体及其制造方法。
背景技术
随着电子或光电产品诸如数字相机、具有影像拍摄功能的手机、条码扫描器(bar code reader)以及监视器需求的增加，半导体技术发展的相当快速，且半导体芯片的尺寸有微缩化(miniaturization)的趋势，而其功能也变得更为复杂。
半导体芯片通常为了效能上的需求而置放于同一密封的封装体，以助于操作上的稳定。再者，由于高效能或多功能的半导体芯片通常需要更多的输入/输出(I/O)导电垫结构，因此必须缩小电子元件封装体中导电凸块之间的间距，以在电子元件封装体中增加导电凸块数量。如此一来，半导体封装的困难度会增加而使其良率降低。
因此，有必要寻求一种新的封装体结构，其能够解决上述的问题。
发明内容
有鉴于此，本发明一实施例提供一种电子元件封装体，包括：至少一半导体芯片，具有一第一表面及与其相对的一第二表面，其中至少一重布线设置于半导体芯片的第一表面上，且电连接于半导体芯片的至少一导电垫结构；至少一抵接部，设置于重布线上并与其电性接触；一钝化保护层，覆盖半导体芯片的第一表面，且环绕抵接部；以及一基板，贴附于半导体芯片的第二表面。
本发明另一实施例提供一种电子元件封装体的制造方法，包括：提供至少一半导体芯片，其具有一第一表面及与其相对的一第二表面，其中半导体芯片内具有至少一接触开口延伸至第一表面且具有至少一导电垫结构位于接触开口底部；将半导体芯片的第二表面贴附于一基板；在半导体芯片的第一表面上形成至少一重布线，且经由接触开口而电连接导电垫结构；在半导体芯片的第一表面上覆盖一牺牲图案层，其中牺牲图案层具有一开口以局部露出重布线；在开口内形成至少一抵接部，其中抵接部与露出的重布线电性接触；去除牺牲图案层；以及在半导体芯片的第一表面上覆盖一钝化保护层，使钝化保护层环绕抵接部。
附图说明
图1A至图1I是本发明实施例的电子元件封装体的制造方法剖面示意图；
图1J是本发明另一实施例的电子元件封装体中间制造阶段中其中一剖面示意图；及
图2至图4是本发明不同实施例的电子元件封装体剖面示意图。
主要元件符号说明
10～第一表面；
20～第二表面；
100～半导体芯片；
100a～接触开口；
106～绝缘层；
108～晶种层；
110～重布局线；
112～牺牲图案层；
112a、118a～开口；
114～抵接部；
116～导电保护层；
200、2000～基板；
102、118～钝化保护层；
104～导电垫结构；
202～围堰；
204～空腔；
1000～半导体晶片。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明所提供的实施例仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。在附图或描述中，相似或相同部分的元件是使用相同或相似的符号表示。再者，附图中元件的形状或厚度可扩大，以简化或是方便标示。此外，未绘示或描述的元件，可以是具有各种熟悉该项技术者所知的形式。
图1I、图2、图3及图4，其绘示出根据本发明不同实施例的电子元件封装体剖面示意图。在本发明的封装体实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical Systems，MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)。特别是可选择使用晶片级封装制作工艺对影像感测器、发光二极管、太阳能电池、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件、压力感测器(pressure sensors)、或喷墨头(ink printer heads)等半导体芯片进行封装。
上述晶片级封装制作工艺主要指在晶片阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体芯片重新分布在一承载晶片上，再进行封装制作工艺，也可称之为晶片级封装制作工艺。上述晶片级封装制作工艺也适用于以堆叠(stack)方式安排具有集成电路的多片晶片，以形成多层集成电路(multi-layer integrated circuit devices)的封装体。
请参照图1I，电子元件封装体包括：至少一半导体芯片100，例如CMOS影像感测(CMOS image sensor，CIS)芯片、微机电系统(MEMS)、或其他现有的集成电路芯片。此处，半导体芯片100以CMOS影像感测芯片作为范例说明。半导体芯片100具有一第一表面10及与其相对的一第二表面20。再者，半导体芯片100包括：一钝化保护层102邻近于第二表面20以及多个导电垫结构104设置于钝化保护层102内。导电垫结构104通过内连接(interconnect)结构(未绘示)而与半导体芯片100内的电路(未绘示)电连接。多个重布线(RDL)110设置于半导体芯片100的第一表面10上，且电连接至钝化保护层102内对应的导电垫结构104。在一实施例中，重布线110经由一绝缘层106，例如氧化硅层，而与半导体芯片100内的半导体基板绝缘。再者，重布线110与导电垫结构104之间具有一晶种层108，其包括钛、铜、或其合金。
至少一抵接部114设置于对应的重布线110上且与其直接接触。亦即，重布线110与抵接部114之间不具有粘着层。在本实施例中，抵接部114具有单层结构，且作为半导体芯片100与外部电路(例如，印刷电路板(printed circuit board，PCB))的电连接部。再者，抵接部114可由铜、镍、金、或其组合或现有的焊料所构成。
一导电保护层116覆盖重布线110与抵接部114的表面，其可由镍、金、或其合金所构成，用以防止重布线110与抵接部114因环境因素而氧化的问题。
一钝化保护层118，例如一感光防焊(solder mask)层，覆盖半导体芯片100的第一表面10。钝化保护层118具有多个开口118a，使钝化保护层118经由开口118a而环绕抵接部114。特别的是表面覆盖导电保护层116的抵接部114突出于钝化保护层118的上表面，以作为导电凸块(bump)。再者，表面覆盖导电保护层116的抵接部114与钝化保护层118的开口118a内壁之间具有一间隙，使钝化保护层118不与表面覆盖导电保护层116的抵接部114接触。
一基板200贴附于半导体芯片100的第二表面20上。当基板200是用以承载半导体芯片100时可以选择但不限于导热基板，例如金属基板、空白的硅基板(raw silicon substrate)或其他不含电路的半导体基板。当基板200用以供光线进出时，则可选择但不限于透光基板，例如玻璃、石英、塑胶、或蛋白石(opal)，其中滤光片及/或抗反射层可选择形成于此透光基板上。在本实施例中，基板200为一透光基板且可经由围堰结构(dam)或粘着材料层而贴附至半导体芯片100。此处，以围堰结构202作为范例说明。由围堰结构202所构成的空腔(cavity)204通常会对应于半导体芯片100(如，CIS芯片)的感光区(未绘示)。
请参照图2，其绘示出根据本发明另一实施例的电子元件封装体剖面示意图，其中相同于图1I的部件是使用相同的标号并省略其相关说明。不同于图1I所示的实施例，抵接部114与重布线110的表面并未覆盖导电保护层116。因此，在本实施例中，抵接部114与重布线110可选择不易氧化的导电材料，例如含镍、金、钛或铜的可能组合的合金材料。
请参照图3，其绘示出根据本发明又另一实施例的电子元件封装体剖面示意图，其中相同于图1I的部件是使用相同的标号并省略其相关说明。在本实施例中，抵接部114与重布线110的表面可覆盖或不覆盖导电保护层116(分别如图1I及图2所示)。而不同于上述实施例之处在于钝化保护层118局部覆盖抵接部114或表面覆盖导电保护层116的抵接部114的上表面。亦即，钝化保护层118与抵接部114或表面覆盖导电保护层116的抵接部114接触。当半导体芯片100组装于一外部电路(例如，PCB)时，抵接部114通过PCB上的凸块的电性接触来进行半导体芯片10与PCB之间的电连接。
请参照图4，其绘示出根据本发明又另一实施例的电子元件封装体剖面示意图，其中相同于图1I的部件使用相同的标号并省略其相关说明。在本实施例中，抵接部114与重布线110的表面可覆盖或不覆盖导电保护层116(分别如图1I及图2所示)。不同于上述实施例，钝化保护层118由非感光性防焊材料所构成。再者，钝化保护层118的上表面不低于抵接部114或表面覆盖导电保护层116的抵接部114的上表面。举例而言，钝化保护层118的上表面大体上切齐于抵接部114的上表面。再者，钝化保护层118与抵接部114或表面覆盖导电保护层116的抵接部114的侧壁直接接触，使两者之间不具有空隙。
以下配合图1A至图1I说明根据本发明实施例的电子元件封装体的制造方法。请参照图1A，提供一半导体晶片1000，包括多个半导体芯片区，例如CIS芯片区。此处，为简化附图，仅以单一半导体芯片区表示之。半导体晶片1000具有一第一表面10及与其相对的一第二表面20。再者，每一半导体芯片区包括：一钝化保护层102邻近于第二表面20以及多个导电垫结构104设置于钝化保护层102内。
再者，提供一基板2000，例如由玻璃、石英、塑胶、或蛋白石(opal)所构成的透光晶片，其中滤光片及/或抗反射层可选择形成于此透光晶片上。将基板2000通过围堰结构或粘着材料层而贴附于半导体晶片1000的第二表面20上。在本实施例中，基板2000经由围堰结构202而贴附至半导体晶片1000。由围堰结构202所构成的空腔204通常会对应于半导体芯片区(如，CIS芯片区)的感光区(未绘示)。
请参照图1B，将半导体晶片1000蚀刻、铣削(milling)、磨削(grinding)、或研磨(polishing)至所需的厚度，例如100微米(μm)。之后，通过现有光刻即蚀刻技术，在半导体晶片1000的每一半导体芯片区内形成多个接触开口(via opening)100a，其对应于每一半导体芯片区的导电垫结构104。接触开口100a自半导体晶片1000的第一表面10往第二表面20延伸且露出导电垫结构104。
请参照图1C，可通过化学气相沉积(chemical vapor deposition，CVD)或其他适用的沉积技术，在半导体晶片1000的第一表面10及每一接触开口100a的内表面顺应性形成一绝缘层106，例如氧化硅层，用以提供后续重布局线与半导体晶片1000之间的电性隔离。之后，去除接触开口100a底部的绝缘层106，以露出导电垫结构104。在另一实施例中，如图1J所示，100a底部的绝缘层106可未完全被移除，但仍可露出导电垫结构104。图1C与图1J所示的绝缘层106结构可选择性地应用于本发明，为简化说明，以下图示采用图1C所揭示的绝缘层106结构描述。
请参照图1D，在绝缘层106的表面上顺应性形成一晶种(seed)层108，使晶种层108经由接触开口100a而与导电垫结构104作电性接触。在一实施例中，晶种层108可由钛、钛化钨、铬、铜、或其合金所构成，用以加强后续重布局线与导电垫结构104之间的附着性。之后，可通过电镀法，在晶种层108形成一导电层(未绘示)，其材质包括铜、镍、金或其组合。接着，通过光刻及蚀刻制作工艺以图案化晶种层108上的导电层，以在半导体晶片1000的第一表面10上形成多个重布局线110。每一重布局线110经由接触开口100a内的晶种层108而与对应的导电垫结构104电连接。
请参照图1E，在半导体晶片1000的第一表面10上覆盖一牺牲图案层112，例如干膜(dry film)或湿式光致抗蚀剂材料。在本实施例中，牺牲图案层112具有多个开口112a，每一开口112a局部露出对应的重布局线110。
请参照图1F，可通过电镀法，在每一开口112a内形成具有单层结构的抵接部114，使抵接部114与重布局线110直接接触。抵接部114的材质可包括铜、镍、金、焊料或其组合。可以理解的是牺牲图案层112的厚度取决于抵接部114的所需高度。在一实施例中，牺牲图案层112的厚度约为50微米。
请参照图1G，去除牺牲图案层112。接着，去除未被重布局线110所覆盖的晶种层108。之后，可通过化学电镀(electroless plating)，在重布局线110及抵接部114的表面形成一导电保护层116，如图1H所示。在本实施例中，导电保护层116可由镍、金、或其合金所构成。
请参照图1I，在半导体晶片1000的第一表面10上形成一钝化保护层118。钝化保护层118具有多个开口118a，使钝化保护层118环绕表面覆盖有导电保护层116的抵接部114。在本实施例中，钝化保护层118可由感光的防焊材料所构成。因此，在进行光刻制作工艺之后，表面覆盖有导电保护层116的抵接部114突出于钝化保护层118的上表面，以作为后续半导体芯片与外部电路(例如，PCB)的电连接部，例如凸块。再者，钝化保护层118与表面覆盖有导电保护层116的抵接部114之间具有一间隙，使钝化保护层118不与表面覆盖有导电保护层116的抵接部114接触。之后，对贴附于基板2000的半导体晶片100进行切割制作工艺，以形成多个具有至少一半导体芯片100的电子元件封装体。此处，为简化附图，仅以单一电子元件封装体表示之。
需注意的是在一实施例中，在局部去除晶种层108之后(如图1G所示)，可省略形成导电保护层116(如图1H所示)的步骤，而依序进行钝化保护层118的制作及切割制作工艺，而完成电子元件封装体(如图2所示)的制作。
在另一实施例中，当钝化保护层118由感光的防焊材料所构成时，也可通过光刻制作工艺，使钝化保护层118覆盖局部覆盖抵接部114或是表面具有导电保护层116的抵接部114。之后，进行切割制作工艺，而完成电子元件封装体(如图3所示)的制作。
又另一实施例中，可在局部去除晶种层108之后(如图1G所示)，在半导体晶片1000的第一表面10上形成一钝化保护层118，使钝化保护层118完全覆盖重布局线110及抵接部114或表面具有导电保护层116的重布局线110及抵接部114。在此实施例中，钝化保护层118由非感光的防焊材料所构成。接着，可对钝化保护层118进行一研磨制作工艺，例如化学机械抛光(chemical mechanical polishing，CMP)制作工艺，直至露出抵接部114或表面具有导电保护层116的抵接部114。在此实施例中，钝化保护层118的上表面不低于抵接部114或表面覆盖导电保护层116的抵接部114的上表面。再者，钝化保护层118与抵接部114或表面覆盖导电保护层116的抵接部114的侧壁直接接触，使两者之间不具有空隙。之后，进行切割制作工艺，而完成电子元件封装体(如图4所示)的制作。
根据上述实施例，由于半导体芯片中用于与外部电路电连接的抵接部形成于牺牲图案层(例如，干膜)的开口中，因此可在光刻制作工艺能力(process capability)容许之下，大幅缩小抵接部的间距，进而在一既定尺寸的电子元件封装体中相对增加抵接部的数量。亦即，上述实施例可符合高效能或多功能的半导体芯片的需求。再者，抵接部可通过电镀法直接形成于重布局线上且在制作钝化保护层之前形成，相较于现有技术中由印刷法(printing)所制作的导电凸块而言，无需在导电凸块与重布局线之间额外制作底层凸块金属化(under-bump metallization，UBM)层。因此，可进一步降低电子元件封装体的制作成本。
虽然结合以上较佳实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作更动与润饰，因此本发明的保护范围应以附上的权利要求所界定的为准。

Claims (20)

1.一种电子元件封装体，包括：
至少一半导体芯片，具有第一表面及与其相对的第二表面，其中至少一重布线设置于该半导体芯片的该第一表面上，且电连接于该半导体芯片的至少一导电垫结构；
至少一抵接部，设置于该重布线上并与其电性接触；
钝化保护层，覆盖该半导体芯片的该第一表面，且环绕该抵接部；以及
基板，贴附于该半导体芯片的该第二表面。
2.如权利要求1所述的电子元件封装体，其中该抵接部突出于该钝化保护层的上表面，且该抵接部与该钝化保护层之间具有一间隙。
3.如权利要求1所述的电子元件封装体，其中该钝化保护层局部覆盖该抵接部的上表面。
4.如权利要求1所述的电子元件封装体，其中该钝化保护层的上表面不低于该抵接部的上表面，且该钝化保护层与该抵接部的侧壁直接接触。
5.如权利要求1所述的电子元件封装体，其中该抵接部与该重布线的材质相同。
6.如权利要求1所述的电子元件封装体，还包括一导电保护层，至少覆盖该抵接部的表面。
7.如权利要求6所述的电子元件封装体，其中该导电保护层由镍、金、或其合金所构成。
8.如权利要求1所述的电子元件封装体，还包括一晶种层，设置于该重布线与该导电垫之间。
9.如权利要求1所述的电子元件封装体，其中该钝化保护层由感光或非感光防焊材料所构成。
10.如权利要求1所述的电子元件封装体，其中该半导体芯片内具有至少一接触开口延伸至该第一表面且该导电垫结构位于该接触开口底部。
11.一种电子元件封装体的制造方法，包括：
提供至少一半导体芯片，其具有第一表面及与其相对的第二表面，其中该半导体芯片内具有至少一接触开口延伸至该第一表面且具有至少一导电垫结构位于该接触开口底部；
将该半导体芯片的该第二表面贴附于一基板；
在该半导体芯片的该第一表面上形成至少一重布线，且经由该接触开口而电连接该导电垫结构；
在该半导体芯片的该第一表面上覆盖一牺牲图案层，其中该牺牲图案层具有一开口，以局部露出该重布线；
在该开口内形成至少一抵接部，其中该抵接部与该露出的重布线电性接触；
去除该牺牲图案层；以及
在该半导体芯片的该第一表面上覆盖一钝化保护层，使该钝化保护层环绕该抵接部。
12.如权利要求11所述的电子元件封装体的制造方法，其中在形成该抵接部及去除该牺牲图案层之后还包括：
在该抵接部表面形成一导电保护层。
13.如权利要求12所述的电子元件封装体的制造方法，其中该牺牲图案层包括干膜或湿式光致抗蚀剂材料。
14.如权利要求11所述的电子元件封装体的制造方法，其中该抵接部与该重布线的材质相同。
15.如权利要求11所述的电子元件封装体的制造方法，该抵接部突出于该钝化保护层的上表面，且该抵接部与该钝化保护层之间具有一间隙。
16.如权利要求11所述的电子元件封装体的制造方法，其中该钝化保护层局部覆盖该抵接部的上表面。
17.如权利要求11所述的电子电子元件封装体的制造方法，其中该钝化保护层的上表面不低于该抵接部的上表面，且该钝化保护层与该抵接部的侧壁直接接触。
18.如权利要求17所述的电子元件封装体的制造方法，其中该抵接部包括铜、镍、金、焊料、或其组合且该抵接部是通过电镀法而形成的。
19.如权利要求18所述的电子元件封装体的制造方法，还包括在该重布线与该导电垫结构之间形成一晶种层。
20.如权利要求11所述的电子元件封装体的制造方法，其中该钝化保护层由感光或非感光防焊材料所构成。
CN201110073355.XA 2010-03-26 2011-03-25 电子元件封装体及其制造方法 Active CN102201383B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31805610P 2010-03-26 2010-03-26
US61/318,056 2010-03-26

Publications (2)

Publication Number Publication Date
CN102201383A true CN102201383A (zh) 2011-09-28
CN102201383B CN102201383B (zh) 2015-03-11

Family

ID=44655446

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110073355.XA Active CN102201383B (zh) 2010-03-26 2011-03-25 电子元件封装体及其制造方法

Country Status (3)

Country Link
US (2) US8710680B2 (zh)
CN (1) CN102201383B (zh)
TW (1) TWI515838B (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543924A (zh) * 2011-12-31 2012-07-04 桂林电子科技大学 基于s型铜布线的芯片级三维柔性封装结构
CN102543925A (zh) * 2011-12-31 2012-07-04 桂林电子科技大学 基于锯齿型铜布线的芯片级三维柔性封装结构
CN102569231A (zh) * 2011-12-31 2012-07-11 桂林电子科技大学 基于卷曲型铜布线的芯片级三维柔性封装结构
CN103107157A (zh) * 2011-11-15 2013-05-15 精材科技股份有限公司 晶片封装体及其形成方法
CN107146795A (zh) * 2016-03-01 2017-09-08 精材科技股份有限公司 晶片封装体及其制造方法
CN109755203A (zh) * 2017-11-08 2019-05-14 台湾积体电路制造股份有限公司 封装结构
CN110896591A (zh) * 2018-09-12 2020-03-20 Lg伊诺特有限公司 柔性电路板、包括其的芯片封装及包括芯片封装的电子设备
CN112039489A (zh) * 2020-01-22 2020-12-04 中芯集成电路（宁波）有限公司 一种薄膜压电声波滤波器及其制造方法
CN112039491A (zh) * 2020-03-31 2020-12-04 中芯集成电路（宁波）有限公司 一种薄膜压电声波滤波器及其制造方法
WO2021135620A1 (zh) * 2019-12-30 2021-07-08 颀中科技（苏州）有限公司 封装结构及其成型方法
CN113195192A (zh) * 2018-12-10 2021-07-30 ams传感器新加坡私人有限公司 用于光电模块的真空注射成型
CN113555488A (zh) * 2020-04-23 2021-10-26 斯坦雷电气株式会社 半导体发光装置

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110294237A1 (en) * 2010-05-27 2011-12-01 MOS Art Pack Corporation Packaging method of semiconductor device
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
TWI533424B (zh) * 2012-04-26 2016-05-11 旭德科技股份有限公司 封裝載板
CN103679108B (zh) 2012-09-10 2018-12-11 霍尼韦尔国际公司 具有多个图像传感器的光学标记读取装置
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101538541B1 (ko) * 2013-07-16 2015-07-22 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
TWI662670B (zh) * 2013-08-30 2019-06-11 精材科技股份有限公司 電子元件封裝體及其製造方法
MA36343B1 (fr) * 2013-10-14 2016-04-29 Nemotek Technologies Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
TWI638465B (zh) * 2013-12-09 2018-10-11 新加坡商海特根微光學公司 具有包括位在光電裝置上方不同高度之光學元件之多個光通道的模組
CN103762182B (zh) * 2013-12-11 2017-08-01 上海交通大学 基于水玻璃‑陶瓷复合介质的tsv封装再分布层制备方法
TWI578411B (zh) * 2014-04-03 2017-04-11 精材科技股份有限公司 晶片封裝體的製造方法
TWI585959B (zh) 2014-08-13 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
CN109742064B (zh) 2015-04-27 2021-06-11 精材科技股份有限公司 晶片封装体及其制造方法
TWI573244B (zh) * 2015-04-27 2017-03-01 精材科技股份有限公司 晶片封裝體及其製造方法、半導體電鍍系統
US9862600B2 (en) * 2015-05-21 2018-01-09 Ams International Ag Chip structure
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20180331061A1 (en) * 2017-05-11 2018-11-15 Qualcomm Incorporated Integrated device comprising bump on exposed redistribution interconnect
US11024604B2 (en) 2019-08-10 2021-06-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1357921A (zh) * 2001-12-18 2002-07-10 威盛电子股份有限公司 晶片上减少阻抗的覆晶焊垫配置
US20090039529A1 (en) * 2007-08-08 2009-02-12 Sebastian Mueller Integrated Circuit Having a Plurality of Connection Pads and Integrated Circuit Package
CN101369561A (zh) * 2007-08-17 2009-02-18 三星电子株式会社 半导体芯片封装件、电子装置及其制造方法
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20090152715A1 (en) * 2007-12-14 2009-06-18 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-applied Protective Layer
US20090184411A1 (en) * 2008-01-22 2009-07-23 Samsung Electronics Co., Ltd Semiconductor packages and methods of manufacturing the same
US20090261466A1 (en) * 2006-11-10 2009-10-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
US6884313B2 (en) * 2001-01-08 2005-04-26 Fujitsu Limited Method and system for joining and an ultra-high density interconnect
US7534652B2 (en) * 2005-12-27 2009-05-19 Tessera, Inc. Microelectronic elements with compliant terminal mountings and methods for making the same
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI467723B (zh) * 2012-09-26 2015-01-01 矽品精密工業股份有限公司 半導體封裝件及其製法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1357921A (zh) * 2001-12-18 2002-07-10 威盛电子股份有限公司 晶片上减少阻抗的覆晶焊垫配置
US20090261466A1 (en) * 2006-11-10 2009-10-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps
US20090039529A1 (en) * 2007-08-08 2009-02-12 Sebastian Mueller Integrated Circuit Having a Plurality of Connection Pads and Integrated Circuit Package
CN101369561A (zh) * 2007-08-17 2009-02-18 三星电子株式会社 半导体芯片封装件、电子装置及其制造方法
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20090152715A1 (en) * 2007-12-14 2009-06-18 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-applied Protective Layer
US20090184411A1 (en) * 2008-01-22 2009-07-23 Samsung Electronics Co., Ltd Semiconductor packages and methods of manufacturing the same

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107157A (zh) * 2011-11-15 2013-05-15 精材科技股份有限公司 晶片封装体及其形成方法
CN102543924A (zh) * 2011-12-31 2012-07-04 桂林电子科技大学 基于s型铜布线的芯片级三维柔性封装结构
CN102543925A (zh) * 2011-12-31 2012-07-04 桂林电子科技大学 基于锯齿型铜布线的芯片级三维柔性封装结构
CN102569231A (zh) * 2011-12-31 2012-07-11 桂林电子科技大学 基于卷曲型铜布线的芯片级三维柔性封装结构
CN107146795A (zh) * 2016-03-01 2017-09-08 精材科技股份有限公司 晶片封装体及其制造方法
CN109755203A (zh) * 2017-11-08 2019-05-14 台湾积体电路制造股份有限公司 封装结构
CN110896591A (zh) * 2018-09-12 2020-03-20 Lg伊诺特有限公司 柔性电路板、包括其的芯片封装及包括芯片封装的电子设备
CN110896591B (zh) * 2018-09-12 2023-10-24 Lg伊诺特有限公司 柔性电路板、包括其的芯片封装及包括芯片封装的电子设备
CN113195192A (zh) * 2018-12-10 2021-07-30 ams传感器新加坡私人有限公司 用于光电模块的真空注射成型
US11996505B2 (en) 2018-12-10 2024-05-28 Ams Sensors Singapore Pte. Ltd. Vacuum injection molding for optoelectronic modules
WO2021135620A1 (zh) * 2019-12-30 2021-07-08 颀中科技（苏州）有限公司 封装结构及其成型方法
CN112039489A (zh) * 2020-01-22 2020-12-04 中芯集成电路（宁波）有限公司 一种薄膜压电声波滤波器及其制造方法
CN112039491A (zh) * 2020-03-31 2020-12-04 中芯集成电路（宁波）有限公司 一种薄膜压电声波滤波器及其制造方法
CN113555488A (zh) * 2020-04-23 2021-10-26 斯坦雷电气株式会社 半导体发光装置

Also Published As

Publication number Publication date
US20110233782A1 (en) 2011-09-29
CN102201383B (zh) 2015-03-11
US8778798B1 (en) 2014-07-15
TW201133725A (en) 2011-10-01
US8710680B2 (en) 2014-04-29
TWI515838B (zh) 2016-01-01
US20140193950A1 (en) 2014-07-10

Similar Documents

Publication Publication Date Title
CN102201383B (zh) 电子元件封装体及其制造方法
CN101996953B (zh) 芯片封装体及其制造方法
TWI528514B (zh) 晶片封裝體及其製造方法
CN102034778B (zh) 芯片封装体及其制造方法
TWI525774B (zh) 晶片封裝體
US7981727B2 (en) Electronic device wafer level scale packages and fabrication methods thereof
CN100416785C (zh) 用于使用重新分配基板制造晶片层芯片尺寸封装的方法
CN101996955B (zh) 芯片封装体及其制造方法
US8502393B2 (en) Chip package and method for forming the same
US8310050B2 (en) Electronic device package and fabrication method thereof
US8541877B2 (en) Electronic device package and method for fabricating the same
CN104425452A (zh) 电子元件封装体及其制造方法
US8810012B2 (en) Chip package, method for forming the same, and package wafer
CN102891117A (zh) 晶片封装体及其制造方法
CN106252308A (zh) 晶片封装体与其制备方法
CN102148221A (zh) 电子元件封装体及其制造方法
TW201123321A (en) Electronic device package and fabrication method thereof
TWI539568B (zh) 電子元件封裝體及其製造方法
CN102779809A (zh) 晶片封装体及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant