TWI525774B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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Publication number
TWI525774B
TWI525774B TW100101192A TW100101192A TWI525774B TW I525774 B TWI525774 B TW I525774B TW 100101192 A TW100101192 A TW 100101192A TW 100101192 A TW100101192 A TW 100101192A TW I525774 B TWI525774 B TW I525774B
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Taiwan
Prior art keywords
layer
semiconductor substrate
chip package
hole
recess
Prior art date
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TW100101192A
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English (en)
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TW201125097A (en
Inventor
林佳昇
蔡佳倫
徐長生
李柏漢
Original Assignee
精材科技股份有限公司
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Priority claimed from US12/687,093 external-priority patent/US8432032B2/en
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201125097A publication Critical patent/TW201125097A/zh
Application granted granted Critical
Publication of TWI525774B publication Critical patent/TWI525774B/zh

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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description

晶片封裝體
本發明係有關於一種晶片封裝體，特別有關於一種具有矽通孔(through-silicon via)的晶片封裝體及其製造方法。
為了使電子裝置的尺寸越來越小，電子裝置內所含的晶片封裝體也需要越變越小。降低晶片封裝體尺寸的方法之一包含在被封裝的晶片內使用矽通孔。然而，在某些情況下，矽通孔內的重佈路線層在熱循環試驗過程中很容易從矽通孔的側壁脫層(delaminated)，因此，矽通孔也會使得被封裝晶片的信賴性下降。
因此，業界亟需一種新的晶片封裝體設計以及其製造方法。
本發明一實施例係提供一種晶片封裝體，包括半導體基底，具有第一表面和相對的第二表面；貫穿孔設置於第一表面上，由第一表面延伸至第二表面；導線層設置於第一表面之上，且延伸至貫穿孔；緩衝插塞設置於貫穿孔內的導線層之上；以及保護層設置於半導體基底的整個第一表面之上。
此外，本發明另一實施例還提供一種晶片封裝體的製造方法，包括：提供一半導體基底，具有第一表面和相對的第二表面；形成貫穿孔於第一表面上，由第一表面延伸至第二表面；在第一表面之上順應性地形成導線層，且延伸至貫穿孔；在貫穿孔內的導線層之上形成緩衝插塞；以及形成保護層覆蓋半導體基底的整個第一表面。
本發明之另一實施例提供一種晶片封裝體，包括半導體基底，具有第一表面和相對的第二表面；間隔層設置在半導體基底的第二表面下方；蓋板設置在間隔層下方；形成凹陷部鄰接半導體基底的側壁，由半導體基底的第一表面至少延伸至間隔層。然後，保護層設置在半導體基底的第一表面之上以及凹陷部內。
本發明之另一實施例還提供一種晶片封裝體的製造方法，包括：提供半導體基底，具有第一表面和相對的第二表面；在半導體基底的第二表面下方形成間隔層；將蓋板黏著至間隔層的下方；在半導體基底的第一表面上沿著切割線形成溝槽開口，由第一表面至少延伸至間隔層；在半導體基底的第一表面上方以及溝槽開口內形成保護層。然後，沿著切割線分割半導體基底，形成晶片封裝體，其中每個晶片封裝體包含至少一凹陷部，鄰接半導體基底的側壁，由半導體基底的第一表面至少延伸至間隔層，並且被保護層覆蓋。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下：
以下以實施例並配合圖式詳細說明本發明，在圖式或說明書描述中，相似或相同之部分係使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖式中各元件之部分將以描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明係以一製作影像感測元件封裝體(image sensor package)的實施例作為說明。然而，可以了解的是，在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(micro electro mechanical system;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(physical sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級晶片封裝(wafer level chip scale package；WLCSP)。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參閱第1圖，其係顯示本發明一實施例之晶片封裝體的部分剖面示意圖，其可由晶圓級封裝製程形成。首先，提供帶有半導體基底100的晶片10，半導體基底100具有第一表面100a與相對的第二表面100b。半導體元件102例如為互補式金氧半導體(CMOS)影像感測元件，以及/或微透鏡形成第二表面100b上作為主動面(active surface)。至少一貫穿孔(through hole)114形成於第一表面100a上，由第一表面100a延伸至第二表面100b。至少一導電墊102a經由貫穿孔114暴露出來，並且可經由內連線與半導體元件102電性連接。在另一實施例中，更可形成至少一凹陷部116鄰接半導體基底100的側壁，並由第一表面100a延伸至第二表面100b，其中凹陷部116是經由在切割線SL處切割出溝槽開口(trench opening)而形成，切割線SL設置於任兩個相鄰的晶片之間。
圖案化的絕緣層118在第一表面100a上形成，且延伸至貫穿孔114與凹陷部116的側壁。在另一實施例中，貫穿孔114底部上的絕緣層118被移除。形成絕緣層118的材料包含，但不限定於，例如為二氧化矽之無機材料，或者是例如為絕緣光阻之感光型絕緣材料。然後，圖案化的導線層120順應性地形成在位於第一表面100a之上的絕緣層118上，且延伸至貫穿孔114。在一實施例中，導線層120可以是重佈路線層，其可以是由銅、鋁、銀、鎳或前述金屬之合金所製成的金屬層。在另一實施例中，圖案化的導線層120更可順應性地形成在凹陷部116內，在貫穿孔114與凹陷部116內的導線層120之間會形成間隙，以隔絕貫穿孔114與凹陷部116內的導線層120。
值得一提的是，在貫穿孔114內形成緩衝插塞(buffer plug)124，然後形成保護層126覆蓋第一表面100a，並填充貫穿孔114與凹陷部116，在貫穿孔114內填充的緩衝插塞可用來分離導線層120與後續填充的保護層126。在凹陷部116內，導線層120可用來分離保護層126與後續形成的間隔層106。在本發明之實施例中，緩衝插塞124可由一層或一層以上的軟性材料形成，保護層126則可以是硬性材料，例如阻銲材料(solder mask)。
在一實施例中，為了提升晶片封裝體的信賴性，緩衝插塞124的材料並未完全固化(cured)，因此在貫穿孔114內的緩衝插塞124與保護層126之間的附著力會降低。要使得緩衝插塞124的材料未完全固化，緩衝插塞124可以在其玻璃轉化點(glass transition temperature；Tg)的溫度以下固化，或者以較短的時間進行固化，藉此可得到附著力較差的軟性固化產物。固化的方法有很多種，可藉由熱、光、電子束或其他類似的方式進行固化。當晶片封裝體進行熱循環試驗(thermal cycle test)時，由硬性材料製成的保護層126可能會收縮，然後從保護層126產生一向上拉拔的力，而軟性的緩衝插塞124則可以變形，以抵銷從保護層126產生的向上拉拔的力，並避免導線層120產生脫層現象。在上述的固化步驟後，大部分在貫穿孔114內的緩衝插塞124在形狀上或尺寸上都是不同的。
此外，為了補償保護層126的熱膨脹係數(coefficient of thermal expansion；CTE)與絕緣層118的熱膨脹係數之間較大的差距，依據本發明一實施例，使得緩衝插塞124的熱膨脹係數介於保護層126的熱膨脹係數與絕緣層118的熱膨脹係數之間，藉此可經由緩衝插塞124來調整保護層126與絕緣層118之間的熱膨脹係數差距，避免晶片封裝體在熱循環試驗期間產生脫層現象。在一實施例中，保護層126的熱膨脹係數可約為159ppm/℃，絕緣層118的熱膨脹係數可約為54ppm/℃，因此，緩衝插塞124的熱膨脹係數需介於約159ppm/℃至54ppm/℃之間。另外，在一實施例中，緩衝插塞124可由一層以上的光阻形成，並且含有一種以上的材料，因此，緩衝插塞124的熱膨脹係數可由54ppm/℃漸變至159ppm/℃。
再參閱第1圖，在半導體基底100的第二表面100b底下貼附蓋板110，蓋板110可以是透明基板或半導體基板。在本發明一實施例中，可在蓋板110與半導體基底100之間設置間隔層106，並在蓋板110與半導體元件102之間形成空穴112，其中空穴112被間隔層106圍繞。在另一實施例中，間隔層106可填滿蓋板110與半導體基底100之間的空間，且無空穴產生。間隔層106可由環氧樹脂(epoxy resin)、阻銲材料(solder mask)或任何其他合適的支撐材料製成。此外，當間隔層106是形成在蓋板110上時，可使用黏著層104來黏接間隔層106與半導體基底100。另外，當間隔層106是形成於半導體基底100上時，可在間隔層106與蓋板110之間施加黏著層。黏著層可以是高分子膜，或者是一種或一種以上的黏著劑，例如為環氧化物(epoxy)或聚氨酯(polyurethane)黏著劑。
導電凸塊128設置在位於第一表面100a上之保護層126的開口內，與導線層120電性連接，導電凸塊128可以是錫球(solder ball)或銲墊(solder paste)。
在凹陷部116內形成導線層120有許多優點，首先，如第1圖所示，在凹陷部116內的導線層120會延伸至切割線SL，且覆蓋半導體基底100的側壁，因此可避免晶片封裝體被水氣滲透。第二，間隔層106可能會由與保護層126相同的材料形成，例如阻銲材料(solder mask)，在此時，如果保護層與間隔層連接在一起，則在保護層與間隔層所產生的應力會很大。然而，依據本發明之一實施例，保護層126與間隔層106會被導線層120及黏著層104分開來，因此可降低在保護層126與間隔層106所產生的應力。
第2A-2H圖係顯示依據本發明之一實施例，製造晶片封裝體之各步驟的部分剖面示意圖。參閱第2A圖，首先，在晶圓廠製造階段(foundry stage)提供一半導體基底100，例如為帶有晶片之晶圓，其具有第一表面100a及相對的第二表面100b，複數個半導體元件102形成於第二表面100b上，複數個導電墊(conductive pad)102a形成於第二表面100b上，且與每個半導體元件102電性連接。
接著，進行封裝階段，在一實施例中，晶圓100的第二表面100b被貼附至作為載體的蓋板110上，蓋板110可由玻璃、石英(quartz)、蛋白石(opal)、塑膠或其它任何可供光線進出的透明基板製成。值得一提的是，也可以選擇性地形成濾光片(filter)以及/或抗反射層(anti-reflective layer)在蓋板110上。在一實施例中，間隔層106可在蓋板110或晶圓100上形成，然後將蓋板110與晶圓100互相貼附，藉此在蓋板110與晶圓100之間形成空穴112，如第2A圖所示，空穴112被間隔層106所圍繞。間隔層106的材料可以是環氧樹脂、阻銲材料或任何其他合適的支撐材料，例如無機材料或者為聚亞醯胺(polyimide；PI)之有機材料。為了增加封裝體的密封性，當間隔層106形成於蓋板110上時，可在間隔層106與晶圓100之間施加黏著層104；另外，當間隔層106形成於晶圓100上時，可在間隔層106與蓋板110之間施加黏著層。接著，可選擇性地在晶圓100的第一表面100a上進行薄化步驟，此薄化步驟可以是蝕刻、銑削(milling)、磨削(grinding)或研磨(polishing)製程。
參閱第2B圖，在晶圓100內藉由移除步驟例如鑽孔(drilling)或蝕刻方式，形成複數個貫穿孔114以及/或溝槽開口116，其係沿著由第一表面100a至第二表面100b的方向延伸，並且經由貫穿孔114暴露出導電墊102a。每個溝槽開口116在兩個相鄰的晶片10a與10b之間的切割線SL處形成，在一實施例中，貫穿孔114與溝槽開口116可藉由相同的蝕刻製程同時形成。另外，溝槽開口116可以是在預刻痕(pre-cutting)製程時經由切割刀於切割線SL處所形成的凹口(notch)。
接著，請參閱第2C圖，為了將半導體基底100與後續形成的導線層隔絕，可順應性地形成絕緣材料覆蓋半導體基底的第一表面100a，並且延伸至貫穿孔114與溝槽開口116的側壁與底部。然後，將絕緣材料圖案化，移除在貫穿孔114與溝槽開口116底部的絕緣材料，形成圖案化的絕緣層118，在貫穿孔114底部的導電墊102a可藉由圖案化的絕緣層118暴露出來。在一實施例中，絕緣層118可由感光性絕緣材料形成，感光性絕緣材料可以是感光性有機高分子材料，其成分包括，但不限定於聚亞醯胺(polyimide;PI)、苯環丁烯(butylcyclobutene;BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)或丙烯酸酯(accrylates)等材料。此感光性有機高分子材料可以利用塗佈方式，例如旋轉塗佈(spin coating)、噴塗(spray coating)或淋幕塗佈(curtain coating)，或者是其它適合之沈積方式塗佈。
參閱第2D圖，在整個絕緣層118上順應性地形成導電材料，覆蓋晶圓100的第一表面100a，且延伸至貫穿孔114與溝槽開口116的側壁與底部。在一實施例中，導電材料可以是銅、鋁、銀、鎳或前述金屬之合金，其可以經由物理氣相沈積(physical vapor deposition;PVD)法或濺鍍(sputtering)法順應性地沈積在絕緣層118上。然後，利用微影蝕刻製程將導電材料圖案化，形成導線層120，導線層120從晶圓100的第一表面100a延伸至貫穿孔114的側壁及底部，並且與貫穿孔114底部的導電墊電性連接。導線層120也可以在溝槽開口116的側壁與底部上形成，但是在貫穿孔114內的導線層120與溝槽開口116內的導線層120之間會形成一間隙使兩者隔絕開來，因此貫穿孔114內的導線層120與溝槽開口116內的導線層120並不連續。
接著，參閱第2E圖，利用塗佈方式，例如旋轉塗佈、噴塗或淋幕塗佈等方式，形成緩衝材料122覆蓋晶圓100的整個第一表面100a，並填充貫穿孔114與溝槽開口116。在一實施例中，緩衝材料122可以是感光性材料，例如無填充物的環氧基光阻(epoxy based photo resist)。接著，參閱第2F圖，利用曝光與顯影製程將緩衝材料122圖案化，留下部分的緩衝材料122在貫穿孔114內，形成緩衝插塞124，緩衝插塞124可以是在每個貫穿孔114內形成的插塞。然後，使得貫穿孔114內的緩衝插塞124不完全固化，以降低緩衝插塞124與後續形成的保護層之間的附著力，藉此，緩衝插塞124可抵抗在熱循環試驗期間來自保護層的向上拉拔力，並避免在貫穿孔114內的導線層120脫層。此外，因為緩衝插塞124未完全固化，在至少兩個貫穿孔114內形成的緩衝插塞124於剖面上會具有不同的形狀，例如，在一貫穿孔114內的緩衝插塞124與另一貫穿孔114內的緩衝插塞124之剖面形狀不同。此外，緩衝插塞124可由一層或一層以上的感光材料形成。
接著，參閱第2G圖，在導線層120上形成保護層126，覆蓋晶圓100的第一表面100a，並填充貫穿孔114與溝槽開口116。保護層126可以是帶有填充物的阻銲材料(solder mask with fillers)，填充物的材料例如為碳化矽、氧化矽或氧化鋁。值得一提的是，緩衝插塞124的熱膨脹係數是介於保護層126的熱膨脹係數與絕緣層118或導線層120的熱膨脹係數之間，因此，保護層126與絕緣層118或導線層120之間的熱膨脹係數差距可藉由緩衝插塞124進行調整，以避免晶片封裝體在熱循環試驗期間產生脫層問題。在一實施例中，保護層126的熱膨脹係數可約為159ppm/℃，絕緣層118的熱膨脹係數可約為54ppm/℃，因此，緩衝插塞124的熱膨脹係數需介於約159ppm/℃至54ppm/℃之間。
接著，請參閱第2H圖，導電凸塊128穿過保護層126形成，且與導線層120電性連接。在一實施例中，於保護層126形成之後，可將保護層126圖案化，形成開口暴露出部分的導線層120。接著，利用電鍍或網版印刷(screen printing)方式在上述開口內填充焊接材料，然後進行回銲(re-flow)步驟形成導電凸塊128，其例如為錫球(solder ball)或銲墊(solder paste)。然後，沿著切割線SL將上述晶圓級封裝體切割，分離各個晶片，形成複數個如第1圖所示之晶片封裝體。
依據本發明之實施例，位於切割線SL上的溝槽開口116是由蝕刻製程形成，因此在半導體基底100的側壁上不會有微小裂縫產生。此外，在晶圓級封裝體的切割製程之後會形成凹陷部116，凹陷部116內的導線層120會延伸至切割線SL，並覆蓋半導體基底100的側壁。因此，導線層120可有效地避免晶片封裝體被水氣滲透。
另外，在本發明一實施例中，於凹陷部116內沒有緩衝插塞存在，因此，凹陷部116內的保護層126之附著力比貫穿孔114內的保護層126之附著力強，藉此可避免凹陷部116內的保護層126脫層。
接著，參閱第3圖，其係顯示本發明一實施例之晶片封裝體的部分剖面示意圖，可由晶圓級晶片封裝製程形成。首先，提供帶有半導體基底100的晶片10，半導體基底100具有第一表面100a與相對的第二表面100b。半導體元件102例如為互補式金氧半導體(CMOS)影像感測元件，以及/或微透鏡形成第二表面100b上作為主動面。至少一貫穿孔114形成於第一表面100a上，由第一表面100a延伸至第二表面100b。至少一導電墊102a經由貫穿孔114暴露出來，並且可經由內連線與半導體元件102電性連接。
在半導體基底100的第二表面100b底下貼附蓋板110，蓋板110可以是透明基板或半導體基板。在一實施例中，於蓋板110與半導體基底100之間設置間隔層106，並在蓋板110與半導體元件102之間形成空穴112，其中空穴112被間隔層106圍繞。在另一實施例中，間隔層106可填滿蓋板110與半導體基底100之間的空間，因此無空穴產生。間隔層106可由環氧樹脂、阻銲材料或任何其他合適的支撐材料製成。此外，當間隔層106是形成在蓋板110上時，可使用黏著層104來黏接間隔層106與半導體基底100。另外，當間隔層106是形成於半導體基底100上時，可在間隔層106與蓋板110之間施加黏著層。黏著層可以是高分子膜，或者是一種或一種以上的黏著劑，例如為環氧化物或聚氨酯黏著劑。
可形成至少一凹陷部130鄰接半導體基底100的側壁，由第一表面100a延伸至間隔層106，或者更進一步地延伸至蓋板110，其中凹陷部130是經由在切割線SL處切割出溝槽開口而形成，切割線SL設置在任兩個相鄰的晶片之間。
絕緣層118在第一表面100a上形成，且延伸至貫穿孔114的側壁，在貫穿孔114底部上的絕緣層118被移除，以暴露出導電墊102a。形成絕緣層118的材料包含，但不限定於，例如為二氧化矽的無機材料，或者是例如為絕緣光阻的感光型絕緣材料。然後，在第一表面100a之上的絕緣層118上順應性地形成圖案化的導線層120，其延伸至貫穿孔114，但是不延伸至凹陷部130。在一實施例中，導線層120可以是重佈路線層，導線層120可以是由銅、鋁、銀、鎳或前述金屬之合金所製成的金屬層。
在貫穿孔114內，於導線層120之上形成緩衝插塞124，然後形成保護層126覆蓋第一表面100a，並填充貫穿孔114與凹陷部130。在貫穿孔114內，填充的緩衝插塞可用來分離導線層120與後續填充的保護層126。在凹陷部130內，保護層126直接覆蓋半導體基底100以及間隔層106的側壁，或者更進一步地覆蓋蓋板110的側壁。在此實施例中，緩衝插塞124可由一層或一層以上的軟性材料形成，保護層126則可以是硬性材料，例如阻銲材料。
在一實施例中，為了提升晶片封裝體的信賴性，緩衝插塞124的材料並未完全固化，因此在貫穿孔114內的緩衝插塞124與保護層126之間的附著力會降低。例如，可固化的緩衝插塞124可以在其玻璃轉化點(Tg)的溫度以下固化，或者以較短的時間進行固化，藉此可得到附著力較差的軟性固化產物。固化的方法有很多種選擇，可藉由使用熱、光、電子束或其他類似的方式進行固化。當晶片封裝體進行熱循環試驗時，由硬性材料製成的保護層126可能會收縮，然後從保護層126產生向上拉拔的力。然而，軟性的緩衝插塞124可以變形，以抵銷從保護層126產生的向上拉拔的力，並且避免在貫穿孔114內的導線層120發生脫層。在上述的固化製程進行之後，在貫穿孔114內的緩衝插塞124大部分在形狀上或尺寸上都是不同的。
此外，為了補償保護層126的熱膨脹係數(CTE)與絕緣層118的熱膨脹係數之間較大的差距，依據本發明之一實施例，緩衝插塞124的熱膨脹係數是介於保護層126的熱膨脹係數與絕緣層118的熱膨脹係數之間，因此可藉由緩衝插塞124來調整保護層126與絕緣層118之間的熱膨脹係數差距，避免晶片封裝體在熱循環試驗期間產生脫層現象。在一實施例中，保護層126的熱膨脹係數可約為159ppm/℃，並且絕緣層118的熱膨脹係數可約為54ppm/℃，因此，緩衝插塞124的熱膨脹係數需介於約159ppm/℃至54ppm/℃之間。另外，在一實施例中，緩衝插塞124可由一層以上的光阻形成，其含有一種以上的材料，因此，緩衝插塞124的熱膨脹係數可由54ppm/℃階梯式地漸變至159ppm/℃。
然後，在第一表面100a上之保護層126的開口內設置導電凸塊128，以與導線層120電性連接，導電凸塊128可以是錫球(solder ball)或銲墊(solder paste)。
在凹陷部130內的保護層126至少會覆蓋半導體基底100以及間隔層106的側壁，並且可更進一步地覆蓋蓋板110的側壁，使得在半導體基底100、間隔層106與蓋板110之間的界面不會暴露在外界環境中。因此，可避免晶片封裝體被水氣滲透。
第4A-4I圖係顯示依據本發明之一實施例，製造晶片封裝體的各步驟之部分剖面示意圖。參閱第4A圖，首先，在晶圓廠製造階段提供一半導體基底100，例如為帶有晶片之晶圓，其具有第一表面100a與相對的第二表面100b，複數個半導體元件102形成於第二表面100b上，複數個導電墊102a形成於第二表面100b上，且與每個半導體元件102電性連接。
接著，進行封裝階段，在一實施例中，晶圓100的第二表面100b被貼附至作為載體的蓋板110上，蓋板110可由玻璃、石英、蛋白石、塑膠或其它可供光線進出的透明基板製成。此外，也可以選擇性地在蓋板110上形成濾光片以及/或抗反射層。在一實施例中，間隔層106可在蓋板110上或晶圓100上形成，然後將蓋板110與晶圓100互相貼附，藉此在蓋板110與晶圓100之間形成空穴112，如第4A圖所示。空穴112被間隔層106所圍繞，間隔層106的材料可以是環氧樹脂、阻銲材料或任何其他合適的支撐材料，例如無機材料或者為聚亞醯胺的有機材料。為了增加封裝體的密封性，當間隔層106形成於蓋板110上時，可在間隔層106與晶圓100之間施加黏著層104；另外，當間隔層106形成於晶圓100上時，可在間隔層106與蓋板110之間施加黏著層。接著，可選擇性地在晶圓100的第一表面100a上進行薄化步驟，此薄化步驟可以是蝕刻、銑削(milling)、磨削(grinding)或研磨(polishing)製程。
參閱第4B圖，藉由移除製程，例如鑽孔(drilling)或蝕刻製程，在晶圓100內形成複數個貫穿孔114，其沿著由第一表面100a向第二表面100b的方向延伸，導電墊102a經由貫穿孔114暴露出來。
參閱第4C圖，為了將半導體基底100與後續形成的導線層隔絕，可順應性地形成絕緣材料覆蓋半導體基底的第一表面100a，並且延伸至貫穿孔114的側壁與底部。然後，將絕緣材料圖案化，移除在貫穿孔114底部的絕緣材料，形成圖案化的絕緣層118，在貫穿孔114底部的導電墊102a藉由圖案化的絕緣層118而暴露出來。在一實施例中，絕緣層118可由感光性絕緣材料形成。在此實施例中，感光性絕緣材料可以是感光性有機高分子材料，其成分包括，但不限定於聚亞醯胺(polyimide;PI)、苯環丁烯(butylcyclobutene;BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)及丙烯酸酯(accrylates)等材料。此感光性有機高分子材料可藉由塗佈製程形成，例如旋轉塗佈(spin coating)、噴塗(spray coating)或淋幕塗佈(curtain coating)，或者是其它適合的沈積製程。
參閱第4D圖，在整個絕緣層118上形成導電材料，此導電材料順應性地形成在晶圓100的第一表面100a之上，並且延伸至貫穿孔114的側壁與底部。在一實施例中，導電材料可以是銅、鋁、銀、鎳或前述金屬之合金，其可以藉由物理氣相沈積(PVD)或濺鍍製程順應性地沈積。然後，藉由微影與蝕刻製程將導電材料圖案化，形成圖案化的導線層120。圖案化的導線層120從晶圓100的第一表面100a延伸至貫穿孔114的側壁及底部，與在貫穿孔114底部的導電墊電性連接。為了電性隔絕，兩個相鄰的晶片10a與10b的圖案化導線層120之間會有空隙存在。
參閱第4E圖，藉由塗佈製程，例如旋轉塗佈、噴塗或淋幕塗佈等製程，形成緩衝材料122覆蓋晶圓100的整個第一表面100a，並填充貫穿孔114。在一實施例中，緩衝材料122可以是感光性材料，例如無填充物的環氧基光阻(epoxy based photo resist)。接著，參閱第4F圖，藉由曝光與顯影製程將緩衝材料122圖案化，留下部分的緩衝材料122在貫穿孔114內，形成緩衝插塞124，緩衝插塞124可以是在每個貫穿孔114內的插塞。然後，將貫穿孔114內的緩衝插塞124固化，但是不完全固化，以降低緩衝插塞124與後續形成的保護層之間的附著力。因此，緩衝插塞124可抵抗在熱循環試驗期間來自保護層的向上拉拔力，並避免在貫穿孔114內的導線層120發生脫層。此外，因為緩衝插塞124並未完全固化，在至少兩個貫穿孔114內形成的緩衝插塞124於剖面上會有不同的形狀，例如，在一貫穿孔114內的緩衝插塞124與另一貫穿孔114內的緩衝插塞124的剖面形狀不同。
接著，參閱第4G圖，沿著介於兩個相鄰的晶片10a與10b之間的切割線SL形成溝槽開口130，可藉由預切割(pre-cutting)製程經由切割刀形成溝槽開口130，使得溝槽開口130在半導體基底100以及間隔層106的側壁上具有傾斜的面，並且溝槽開口130可更進一步地形成在蓋板100的側壁上。此外，溝槽開口130在剖面上具有曲線形狀。在一實施例中，溝槽開口130可由半導體基底100的第一表面100a延伸至間隔層106的任何深度處而形成。在另一實施例中，溝槽開口130可由半導體基底100的第一表面100a延伸至蓋板110的任何深度處而形成。
參閱第4H圖，形成保護層126覆蓋晶圓100的第一表面100a，並填充貫穿孔114與溝槽開口130。在貫穿孔114內的緩衝插塞124被保護層126覆蓋，並且半導體基底100、間隔層106以及蓋板110的側壁也被保護層126覆蓋。保護層126可以是帶有填充物的阻銲材料(solder mask with fillers)，填充物的材料例如為碳化矽、氧化矽或氧化鋁。
參閱第4I圖，導電凸塊128穿過保護層126形成，以與導線層120電性連接。在一實施例中，於形成保護層126之後，可藉由將保護層126圖案化，形成開口暴露出部分的導線層120。接著，藉由電鍍或網版印刷(screen printing)方式在上述開口內填充焊接材料，然後進行回銲(re-flow)製程形成導電凸塊128，其例如為錫球或銲墊。然後，沿著切割線SL將上述晶圓級晶片封裝體切割，分離各個晶片，形成複數個如第3圖所示之晶片封裝體。
依據本發明之一實施例，位於切割線SL上的溝槽開口130是藉由預切割製程形成，因此溝槽開口130可由半導體基底100的第一表面100a延伸至間隔層106，或更進一步地延伸至蓋板110。此外，在切割製程之後，形成晶片封裝體的凹陷部130，並且凹陷部130被保護層126覆蓋，因此，在凹陷部130內的保護層126可有效地避免晶片封裝體被水氣滲透。
另外，在本發明之一實施例中，在凹陷部130內沒有緩衝插塞存在，因此，在凹陷部130內的保護層126之附著力比貫穿孔114內的保護層126之附著力強，藉此可避免凹陷部130內的保護層126發生脫層。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
10、10a、10b．．．晶片
100．．．半導體基底
100a．．．第一表面
100b．．．第二表面
102．．．半導體元件
102a．．．導電墊
104．．．黏著層
106．．．間隔層
110．．．蓋板
112．．．空穴
114．．．貫穿孔
116、130．．．凹陷部、溝槽開口
118．．．絕緣層
120．．．導線層
122．．．緩衝材料
124．．．緩衝插塞
126．．．保護層
128．．．導電凸塊
SL．．．切割線
第1圖係顯示依據本發明之一實施例，晶片封裝體的剖面示意圖。
第2A-2H圖係顯示依據本發明之一實施例，製造第1圖之晶片封裝體的各步驟之剖面示意圖。
第3圖係顯示依據本發明之一實施例，晶片封裝體的剖面示意圖。
第4A-4I圖係顯示依據本發明之一實施例，製造第3圖之晶片封裝體的各步驟之剖面示意圖。
10．．．晶片
100．．．半導體基底
100a．．．第一表面
100b．．．第二表面
102．．．半導體元件
102a．．．導電墊
104．．．黏著層
106．．．間隔層
110．．．蓋板
112．．．空穴
114．．．貫穿孔
116．．．凹陷部、溝槽開口
118．．．絕緣層
120．．．導線層
124．．．緩衝插塞
126．．．保護層
128．．．導電凸塊
SL．．．切割線

Claims (12)

  1. 一種晶片封裝體，包括：一半導體基底，具有一第一表面和一相對的第二表面；一凹陷部，鄰接該半導體基底的一側壁；一貫穿孔，設置於該半導體基底的該第一表面上，由該第一表面延伸至該第二表面；以及一保護層，設置於該半導體基底的該第一表面之上，且填充於該凹陷部與該貫穿孔內。
  2. 如申請專利範圍第1項所述之晶片封裝體，更包括：一間隔層，設置在該半導體基底的該第二表面之下；以及一蓋板，設置在該間隔層之下。
  3. 如申請專利範圍第2項所述之晶片封裝體，其中該凹陷部由該半導體基底的該第一表面延伸至該間隔層。
  4. 如申請專利範圍第2項所述之晶片封裝體，其中該凹陷部由該半導體基底的該第一表面延伸至該蓋板。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該凹陷部與該貫穿孔同時形成。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中該凹陷部由該半導體基底的該第一表面延伸至該第二表面。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該凹陷部在該貫穿孔之後形成。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該凹陷部是經由一預切割製程形成。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該貫穿孔內更包括一緩衝插塞，且該緩衝插塞設置於該保護層下方。
  10. 如申請專利範圍第9項所述之晶片封裝體，更包括一導線層順應性地設置於該半導體基底的該第一表面之上，延伸至該貫穿孔內，且設置於該緩衝插塞下方，以及設置在該凹陷部鄰接該半導體基底的該側壁上。
  11. 如申請專利範圍第10項所述之晶片封裝體，其中該導線層的材料包括鋁。
  12. 如申請專利範圍第1項所述之晶片封裝體，其中該凹陷部具有一傾斜面。
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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US8692382B2 (en) 2010-03-11 2014-04-08 Yu-Lin Yen Chip package
US8698316B2 (en) 2010-03-11 2014-04-15 Yu-Lin Yen Chip package
US8298863B2 (en) * 2010-04-29 2012-10-30 Texas Instruments Incorporated TCE compensation for package substrates for reduced die warpage assembly
TWI500132B (zh) * 2010-11-23 2015-09-11 Xintec Inc 半導體裝置之製法、基材穿孔製程及其結構
DE102011010248B3 (de) * 2011-02-03 2012-07-12 Infineon Technologies Ag Ein Verfahren zum Herstellen eines Halbleiterbausteins
WO2012175902A1 (en) 2011-06-23 2012-12-27 Mfn Technology Limited Method of making a structure comprising coating steps and corresponding structure and devices
TWI505413B (zh) 2011-07-20 2015-10-21 Xintec Inc 晶片封裝體及其製造方法
TWI470760B (zh) * 2011-07-21 2015-01-21 Xintec Inc 晶片封裝體及其形成方法
US8664041B2 (en) * 2012-04-12 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for designing a package and substrate layout
US8710681B2 (en) * 2012-05-31 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation rings for blocking the interface between package components and the respective molding compound
JP2014045142A (ja) * 2012-08-28 2014-03-13 Sony Corp 半導体装置及び半導体装置の製造方法
DE102012223904A1 (de) * 2012-10-05 2014-04-10 Continental Automotive Gmbh Verfahren zum Herstellen eines elektronischen Hochstrom-Schaltkreises mittels Gasspritz-Technologie und Abdichten mit isolierendem Polymer
GB201301683D0 (en) 2013-01-30 2013-03-13 Big Solar Ltd Method of creating non-conductive delineations with a selective coating technology on a structured surface
TWI567904B (zh) * 2013-03-06 2017-01-21 Win Semiconductors Corp A semiconductor wafer structure and a flip chip having a substrate through hole and a metal bump Stacked structure
US20150255499A1 (en) * 2014-03-07 2015-09-10 Xintec Inc. Chip package and method of fabricating the same
TWI560829B (en) * 2014-03-07 2016-12-01 Xintec Inc Chip package and method thereof
US9431350B2 (en) * 2014-03-20 2016-08-30 United Microelectronics Corp. Crack-stopping structure and method for forming the same
TW201543641A (zh) 2014-05-12 2015-11-16 Xintex Inc 晶片封裝體及其製造方法
US20160190353A1 (en) * 2014-12-26 2016-06-30 Xintec Inc. Photosensitive module and method for forming the same
DE102015203393A1 (de) 2015-02-25 2016-08-25 Infineon Technologies Ag Halbleiterelement und Verfahren zu Herstellen von diesem
TWI600125B (zh) * 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI585870B (zh) * 2015-05-20 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
US9704827B2 (en) 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure
US9711425B2 (en) * 2015-08-20 2017-07-18 Xintec Inc. Sensing module and method for forming the same
CN106469699A (zh) * 2015-08-21 2017-03-01 意法半导体有限公司 半导体装置及其制造方法
US10109663B2 (en) * 2015-09-10 2018-10-23 Xintec Inc. Chip package and method for forming the same
US10325946B2 (en) * 2015-10-10 2019-06-18 China Wafer Level Csp Co., Ltd. Packaging method and package structure for image sensing chip
GB2549134B (en) 2016-04-07 2020-02-12 Power Roll Ltd Asymmetric groove
GB2549132A (en) 2016-04-07 2017-10-11 Big Solar Ltd Aperture in a semiconductor
GB2549133B (en) * 2016-04-07 2020-02-19 Power Roll Ltd Gap between semiconductors
US10815121B2 (en) 2016-07-12 2020-10-27 Hewlett-Packard Development Company, L.P. Composite wafers
TWI664722B (zh) * 2016-12-20 2019-07-01 精材科技股份有限公司 半導體結構及其製作方法
CN107161945B (zh) * 2017-05-24 2019-02-22 成都泰美克晶体技术有限公司 一种at切型石英晶片mems加工方法
US10199333B2 (en) * 2017-07-05 2019-02-05 Omnivision Technologies, Inc. Delamination-resistant semiconductor device and associated method
CN107958194B (zh) * 2017-08-17 2021-11-19 柳州梓博科技有限公司 光电传感装置及电子设备
CN108010929A (zh) * 2017-11-29 2018-05-08 苏州晶方半导体科技股份有限公司 一种影像传感芯片的封装方法
KR102557402B1 (ko) * 2018-10-19 2023-07-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP6978697B2 (ja) * 2018-11-15 2021-12-08 日亜化学工業株式会社 発光装置の製造方法
KR20210048638A (ko) 2019-10-23 2021-05-04 삼성전자주식회사 반도체 패키지

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI227550B (en) * 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
JP4401181B2 (ja) * 2003-08-06 2010-01-20 三洋電機株式会社 半導体装置及びその製造方法
CN100514591C (zh) * 2005-03-02 2009-07-15 皇家飞利浦电子股份有限公司 半导体封装的制造方法及所制成的封装
US7402515B2 (en) * 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JPWO2007032213A1 (ja) * 2005-09-14 2009-03-19 日本電気株式会社 プリント配線基板および半導体パッケージ
US7569409B2 (en) * 2007-01-04 2009-08-04 Visera Technologies Company Limited Isolation structures for CMOS image sensor chip scale packages
EP2575166A3 (en) * 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts

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