TW201906021A - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法

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Publication number
TW201906021A
TW201906021A TW106130406A TW106130406A TW201906021A TW 201906021 A TW201906021 A TW 201906021A TW 106130406 A TW106130406 A TW 106130406A TW 106130406 A TW106130406 A TW 106130406A TW 201906021 A TW201906021 A TW 201906021A
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Taiwan
Prior art keywords
semiconductor substrate
layer
wafer
conductive
package structure
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Application number
TW106130406A
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English (en)
Other versions
TWI663661B (zh
Inventor
黃崑永
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力成科技股份有限公司
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Publication of TW201906021A publication Critical patent/TW201906021A/zh
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Publication of TWI663661B publication Critical patent/TWI663661B/zh

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種半導體封裝結構的製造方法。本方法包括以下步驟。於半導體基板的第一表面上形成第一重佈線路層。於半導體基板上形成多個通孔以及開口。配置晶片於半導體基板的開口中。於通孔中形成導電貫孔以電性連接至第一重佈線路層。於半導體基板的第二表面上形成第二重佈線路層，其中第二表面相對於第一表面。第二重佈線路層藉由導電貫孔電性連接至第一重佈線路層。於第二重佈線路層上形成多個導電結構。一種半導體封裝結構亦被提出。

Description

半導體封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關一種半導體封裝結構及其製造方法。
在某些類別的一般封裝技術（例如：扇出晶片級封裝（fan-out wafer level packaging；FO-WLP））之中，晶片藉由模封製程（molding process）密封於模封材料中。然而，由於模封材料與晶片之間的材料差異，在半導體封裝結構的製造過程中可能產生翹曲（warpage）問題。因此，如何在製程中避免翹曲的問題實為亟欲解決的重要課題。
本發明提供一種半導體封裝結構及其製造方法，其可以省略一般的模封製程以減少翹曲問題的產生，且製程較為簡單。
本發明提供一種半導體封裝結構的製造方法。本方法包括以下步驟。於半導體基板的第一表面上形成第一重佈線路層。於半導體基板上形成多個通孔以及開口。配置晶片於半導體基板的開口中。於半導體基板的通孔中形成導電貫孔以電性連接至第一重佈線路層。於半導體基板的第二表面上形成第二重佈線路層，其中第二表面相對於第一表面。第二重佈線路層藉由導電貫孔電性連接至第一重佈線路層。於第二重佈線路層上形成多個導電結構。
在本發明的一實施例中，半導體封裝結構的製造方法更包括於半導體基板上形成絕緣層，以使半導體基板電性隔離。
在本發明的一實施例中，第一重佈線路層包括圖案化導電層，且在配置晶片之前移除部分的絕緣層，以暴露出部分的圖案化導電層。
在本發明的一實施例中，晶片藉由黏著層以黏著於第一重佈線路層。
在本發明的一實施例中，半導體基板包括中心區以及圍繞中心區的周邊區，開口形成於中心區中，且通孔形成於周邊區中。
在本發明的一實施例中，在通孔中形成導電貫孔之後，於導電貫孔中形成空間。
在本發明的一實施例中，導電貫孔填充於通孔中，以形成導電柱。
在本發明的一實施例中，半導體封裝結構的製造方法更包括在形成導電貫孔之前在半導體基板的第二表面上以及在晶片上形成遮蓋層，其中遮蓋層暴露出通孔且部分覆蓋晶片。
本發明提供了一種半導體封裝結構。半導體封裝結構包括半導體基板、晶片、第一重佈線路層、第二重佈線路層、導電貫孔以及多個導電結構。基板具有第一表面以及相對於第一表面的第二表面。半導體基板包括貫穿半導體基板的多個通孔以及開口。晶片配置於半導體基板的開口中。第一重佈線路層位於半導體基板的第一表面上。第二重佈線路層位於半導體基板的第二表面上。第二重佈線路層電性連接至晶片。導電貫孔位於半導體基板的通孔中。第一重佈線路層藉由導電貫孔電性連接至第二重佈線路層。導電結構位於第二重佈線路層上。
在本發明的一實施例中，第一重佈線路層包括圖案化導電層，至少部分的圖案化導電層電性連接至導電貫孔。
在本發明的一實施例中，半導體基板包括中心區以及圍繞中心區的周邊區，開口位於中心區中，且通孔位於周邊區中。
在本發明的一實施例中，晶片包括多個導電凸塊，第二重佈線路層通藉由多個導電凸塊以與晶片電性連接。
基於上述，將晶片配置於半導體基板的開口中，以使半導體基板可以如密封體一般地保護晶片。因此，可以省略一般的模封製程，並且可以減少翹曲問題。此外，形成於通孔中的導電貫孔可以作為第一重佈線路層以及第二重佈線路層之間的導電路徑。因此，可以小型化半導體封裝結構，且保持了製程的簡單性。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1J是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。請參照圖1A，半導體基板100包括第一表面100a以及與第一表面100a相對的第二表面100b。半導體基板100例如可以是矽晶片或有矽覆蓋的剛性基板。半導體基板可以為其他適宜的基板，只要半導體基板100的熱膨脹係數（coefficient of the thermal expansion；CTE）可以與後續製程中要配置的晶片的熱膨脹係數大致匹配（match）即可。在封裝期間以及在元件完成後的操作期間，若熱膨脹係數不匹配可能在封裝結構中產生翹曲應力，因而可能導致封裝結構中產生分層（delaminate）或電性接點斷裂。因此，使用與晶片的熱膨脹係數相近的半導體基板，基本上可以降低因為半導體基底和晶片之間的熱膨脹係數不匹配，而在封裝結構上所產生的翹曲應力。在一些實施例中，可以在半導體基板100的第一表面100a上形成絕緣層120。舉例而言，絕緣層120可以是藉由化學氣相沉積（chemical vapor deposition；CVD）法所形成的氧化矽層或氮化矽層。絕緣層120可以於後續的製程中電性隔離半導體基板100，除此之外，對於絕緣層120的材料或形成方法於本發明並不加以限制。
第一重佈線路層110可以形成於半導體基板100的第一表面100a上。在一些實施例中，第一重佈線路層110可以包括圖案化導電層112以及介電層114。圖案化導電層112可以嵌入於介電層114中，而介電層114的一部分可被移除以暴露出至少一部分的圖案化導電層112。舉例而言，可以於半導體基板100的第一表面100a上形成介電層114，並將介電層114圖案化。接下來，可以藉由濺鍍製程（sputtering process）、蒸鍍製程（evaporation process）、電鍍製程（electroplating process）或其他適宜的製程以於介電層114上形成例如由銅、鋁、鎳等類似的導電材料所製成的導電層。接著，可以藉由微影（photolithography）以及蝕刻製程（etching process）將前述的導電層圖案化，以形成圖案化導電層112。在一些實施例中，圖案化導電層112可以形成於介電層114之前。圖案化導電層112以及介電層114的形成順序可以視設計需求而進行調整，於本發明並不加以限制。
在一些其他實施例中，上述的步驟可以重覆多次，以形成電路設計所要需的多層（multi-layered）重佈線路層。最上面的介電層114可以具有多個開口（未繪示），且前述的開口至少暴露出部分的最上面的圖案化導電層112。
請參照圖1B，可以藉由蝕刻製程、研磨製程（milling process）、機械研磨製程（mechanical grinding process）、化學機械研磨製程（chemical-mechanical polishing process；CMP process）或其他適宜的薄化製程來減小半導體基板100的厚度，但本發明不限於此。在一些實施例中，當提供半導體基板100時，半導體基板100的厚度可能已經被減小了。在一些其他實施例中，第一重佈線路層110可以位於用於支撐的載板50上。載板50可以由玻璃、塑膠或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的半導體封裝結構。在一些實施例中，去黏合層52可以位於載板50以及第一重佈線路層110之間，以提升於後續過程中的離型性（releasability）。舉例而言，去黏合層52可以光熱轉換（light to heat conversion；LTHC）離型層或是其他適宜的離型層。在一些其它實施例中，第一重佈線路層110可以直接與載板50接觸。
請參照圖1C，可以在半導體基板100上形成多個通孔102以及開口104。舉例而言，半導體基板100可以包括中心區CR以及圍繞中心區CR的周邊區PR。在一些實施例中，開口104可以形成於中心區CR中，且通孔102可以形成於周邊區PR中。舉例而言，通孔102以及開口104可以藉由微影以及蝕刻製程所形成，以貫穿半導體基板100。在一些實施例中，可以藉由乾式蝕刻製程、雷射鑽孔製程、機械鑽孔製程或其他適宜的移除製程，以貫穿半導體基板100而形成通孔102以及開口104。在一些其他實施例中，通孔102以及開口104可以藉由相同的製程所形成。通孔102以及開口104的形成順序於本發明中並不加以限制，若藉由乾式蝕刻製程可以同時形成，對準標記（alignment mark）（未繪示）也可以一併同時地形成於半導體基板100上。在一些實施例中，通孔102的內表面（未繪示）及/或開口104的內表面（未繪示）可以與半導體基板100的第一表面100a正交。請參照圖2，類似於圖1C，在一些其他實施例中，依據設計上的需求，在形成通孔102'以及開口104'之後，通孔102'的內表面及/或開口104'的內表面可以是錐狀的。換言之，各個通孔102'的頂部寬度可以大於各個通孔102'的底部（面向第一重佈線路層110）寬度及/或開口104'的頂部寬度可以大於開口104'的底部（面向第一重佈線路層110）寬度。
請回頭參照圖1D，在形成通孔102以及開口104之後，半導體基板100可以是電性絕緣的。舉例而言，絕緣層120可以藉由化學氣相沉積製程在半導體基板100的整個表面上共形（conformal）形成，以使半導體基板100電性隔離。絕緣層120亦可以作為半導體基板100的蝕刻停止層（etch-stop layer），以避免形成通孔102以及開口104之後圖案化導電層112被過度蝕刻（over etching）。在形成通孔102以及開口104之後，再形成一絕緣層（未繪示）於半導體基板100的第二表面100b上以及通孔102以及開口104的內表面和下方，接著再藉由非等向性（anisotropic）乾式蝕刻製程將通孔102下方的二層絕緣層（即，絕緣層120以及再形成於通孔102下方的絕緣層）蝕刻掉以露出圖案化導電層112，為避免同時將此二層絕緣層蝕刻掉導致半導體基板100的第二表面100b上以及通孔102以及開口104的內表面的絕緣層過薄，可以在形成通孔102以及開口104之後再過度蝕刻(Over etching)，先行去除一部分絕緣層120。在絕緣層120所暴露出的圖案化導電層112中，對應於周邊區PR的圖案化導電層112可作為之後進一步地電性連接，而對應於中心區CR的圖案化導電層112可以作為防止過度蝕刻的虛擬層（dummy layer）。
請參照圖1E，晶片130可以配置於半導體基板100的開口104中。舉例而言，晶片130可以是特殊應用積體電路（Application-specific integrated circuit；ASIC）晶片、微機電系統（Microelectromechanical Systems；MEMS）晶片等類似的矽晶片。其他適宜的主動元件也可以作為晶片130。在一些實施例中，當在半導體基板100的中心區CR中形成開口104或是移除部分的絕緣層120以暴露出對應於中心區CR的圖案化導電層112時，對準標記（alignment mark）（未繪示）可以同時地形成於半導體基板100上，以用於晶片130的定位。如此一來，對準標記可以使晶片130能夠精確地定位於半導體基板100的開口104之中。在一些實施例中，晶片130可以包括主動面130a以及相對於位於主動面130a的背面130b。在一些其他實施例中，晶片130的背面130b可以使用黏著層132以黏著至第一重佈線路層110。舉例而言，黏著層132可以包括環氧樹脂（epoxy resin）、無機材料、有機聚合物材料或其他適宜的黏著材料。在一些實施例中，晶片130可以包括設置於主動面130a上的多個導電凸塊134，且導電凸塊134可以用於晶片130的電子訊號的傳輸。導電凸塊134的材料可以包括銅、錫、金、鎳、焊料或上述的組合，但本發明不限於此。舉例而言，導電凸塊134可以是回焊焊料凸塊（reflowed solder bump），導電柱（例如焊料柱、金柱或銅柱等）或導電打線柱（conductive stud）。導電凸塊134可以為其他可能的形式和形狀，於本發明中並不加以限制。本發明中亦可不需要導電凸塊134，圖案化導電層162可直接連結到晶片130的鋁墊上。
在一些實施例中，在將晶片130配置於半導體基板100的開口104中之後，半導體基板100與晶片130之間可以形成間隙G，其中半導體基板100可以被絕緣層120所覆蓋。換句話說，間隙G可以被定義為開口104在配置晶片130之後的剩餘空間。在一些其他實施例中，可以將填料（未繪示）填充於間隙G中，以支撐晶片130。舉例而言，填料的材料可以包括例如環氧樹脂（epoxy resin）或丙烯酸樹脂（acrylic resin）等聚合材料，但本發明不限於此。在一些實施例中，填料的熱膨脹係數可以介於晶片130的的熱膨脹係數與半導體基板100的熱膨脹係數之間，以可以降低彼此之間的剪應力（shearing stress）。在一些其他實施例中，依據設計上的需求，填料可以具有導熱性，以用於散熱。
請參照圖1F，可以在半導體基板100的第二表面100b上以及在晶片130上形成遮蓋層140。舉例而言，遮蓋層140可以暴露出通孔102且部分地覆蓋晶片130。在一些實施例中，遮蓋層140可以包括聚醯亞胺、環氧樹脂、有機聚合物材料或其他適宜的絕緣材料，其可以具有可以部分地覆蓋半導體基板100上的絕緣層以及晶片130，且不會進入通孔102以及間隙G的性質。舉例而言，可以於絕緣層120以及晶片130的頂表面上形成樹脂層（例如：乾膜），並藉由微影以及蝕刻製程以形成遮蓋層140，其中遮蓋層140具有多個對應於半導體基板100的通孔102的開口。在一些實施例中，遮蓋層140可以包括位於中心區CR中的開口，以至少暴露出晶片130的部分導電凸塊134或鋁墊，以作為進一步地的電性連接。換句話說，在至少暴露出晶片130的部分導電凸塊134的同時，遮蓋層140可以部分地覆蓋半導體基板100的開口104。在一些其他實施例中，當形成半導體基板100的通孔102時，可以在半導體基板100上同時形成對準標記以定位遮蓋層140。
請參照圖1G，可以在半導體基板100的通孔102中形成導電貫孔150，以電性連接第一重佈線路層110。在一些實施例中，導電貫孔150可以是藉由濺鍍製程、微影製程、電鍍製程、去光阻製程、蝕刻製程或其他適宜的方法，以在遮蓋層140上以及在半導體基板100的通孔102中共形形成的導電層。舉例而言，導電層可以共形形成於通孔102的內表面中，且延伸至遮蓋層140的頂表面上，並進一步形成至遮蓋層140的開口，其中晶片130的導電凸塊134暴露於遮蓋層140的開口。如此一來，導電貫孔150可以電性連接於晶片130以及第一重佈線路層110的圖案化導電層112之間。在一些實施例中，由於導電層可以共形地沉積於通孔102的內表面及/或遮蓋層140的開口中。可以在對應於通孔102的導電貫孔150及/或遮蓋層140的開口中形成空間S。因此，可以有效地降低製造成本並節省製程時間。換言之，在這些實施例中，通孔102可以不被導電貫孔150所填充。在一些其他實施例中，導電貫孔150可以填充於半導體基板100的通孔102中，以成為導電柱。
請參照圖1H，第二重佈線路層160可以形成於半導體基板100的第二表面100b上，以藉由導電貫孔150將晶片130以及第一重佈線路層110電性連接。第二重佈線路層160可以包括圖案化導電層162以及介電層164。舉例而言，圖案化阻層（未繪示）可以形成在對應於遮蓋層140的導電貫孔150上，並且導電材料可以與導電貫孔150一起共形形成。接著，可以移除圖案化阻層以形成圖案化導電層162。接著，介電層164可以形成在圖案化導電層162上，且暴露出至少一部分的圖案化導電層162以形成第二重佈線路層160。在一些實施例中，在形成介電層164之前，可以藉由蝕刻製程以移除延伸至遮蓋層140的頂表面上的部分導電貫孔150。在一些其他實施例中，可以依據介電層164的材料特性，將介電層164填充於對應於周邊區PR及/或中心區CR的空間S。值得注意的是，上述形成圖案化導電層162以及介電層164的製程可以重覆多次，以形成電路設計所要需的多層重佈線路層。最上面的介電層164可以具有開口（未繪示），且開口至少暴露出部分的最上面的圖案化導電層，以作為進一步地電性連接。在一些實施例中，由介電層164所暴露出的部分圖案化導電層162可以被稱為凸塊底金屬（Under bump metallurgy；UBM），以用於後續的置球製程（ball-mount process）。
請參照圖1I，可以對應於介電層164的開口形成多個導電結構170，以電性連接第二重佈線路層160的圖案化導電層162。舉例而言，導電結構170的材料可以包括錫、鉛、銅、金、鎳、上述之組合或其他適宜的導電材料。在一些實施例中，導電結構170可以藉由置球製程（ball placement process）、化學鍍製程（electroless-plating process）或其他適宜的製程而形成。導電結構170可以包括導電柱、導電凸塊、焊球或上述之組合。然而，導電結構170的材料以及形成方式於本發明中並不加以限制。導電結構170可以依據設計上的需求而具有其他可能的形式以及形狀。在一些實施例中，可以選擇性地進行焊接製程（soldering process）以及迴焊製程（reflowing process），以提升導電結構170與第二重佈線路層160之間的附著力。
請參照圖1J，在形成導電結構170之後，可以將載板50從第一重佈線路層110移除，以形成半導體封裝結構10。舉例而言，可以例如將紫外光雷射、可見光或熱等外部能量施加到至去黏合層52，而使得第一重佈線路層110可以從載板50上剝離。在一些實施例中，在移除載板50之後，被第一重佈線路層110的介電層114所暴露的圖案化導電層112可以用於外部的電性連接。
綜上所述，本發明將晶片配置於半導體基板的開口中，使得半導體基板可以如密封體一般地保護晶片。因此，可以省略一般的模封製程。此外，可以將半導體基板以及晶片之間的熱膨脹係數不匹配最小化，以減少其之間的翹曲問題。此外，當形成半導體基板的開口和通孔時，可以同時在半導體基板上形成用於晶片以及遮蓋層的定位的對準標記，因而可以簡化的製程且增加半導體封裝結構的可靠度（reliability）。此外，形成於通孔中的導電貫孔可以作為第一重佈線路層以及第二重佈線路層之間的導電路徑。因此，可以小型化半導體封裝結構，且保持了製程的簡單性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧半導體封裝結構
50‧‧‧載板
52‧‧‧去黏合層
100‧‧‧半導體基板
100a‧‧‧第一表面
100b‧‧‧第二表面
102‧‧‧通孔
104‧‧‧開口
110‧‧‧第一重佈線路層
112‧‧‧圖案化導電層
114‧‧‧介電層
120‧‧‧絕緣層
130‧‧‧晶片
130a‧‧‧主動面
130b‧‧‧背面
132‧‧‧黏著層
134‧‧‧導電凸塊
140‧‧‧遮蓋層
150‧‧‧導電貫孔
160‧‧‧第二重佈線路層
162‧‧‧圖案化導電層
164‧‧‧介電層
170‧‧‧導電結構
CR‧‧‧中心區
PR‧‧‧周邊區
G‧‧‧間隙
S‧‧‧空間
圖1A至圖1J是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖2是依據本發明一實施例的封裝結構於形成貫孔以及開口後的剖面示意圖。

Claims (10)

  1. 一種半導體封裝結構的製造方法，包括： 於半導體基板的第一表面上形成第一重佈線路層； 於所述半導體基板上形成多個通孔以及開口； 配置晶片於所述半導體基板的所述開口中； 於所述半導體基板的所述通孔中形成導電貫孔，所述導電貫孔電性連接至所述第一重佈線路層； 於所述半導體基板的第二表面上形成第二重佈線路層，所述第二表面相對於所述第一表面，且所述第二重佈線路層電性連接至所述晶片，其中所述第二重佈線路層藉由所述導電貫孔以電性連接至所述第一重佈線路層；以及 於所述第二重佈線路層上形成多個導電結構。
  2. 如申請專利範圍第1項所述的半導體封裝結構的製造方法，更包括在於所述半導體基板上形成所述多個通孔以及所述開口之前減少所述半導體基板的厚度。
  3. 如申請專利範圍第1項所述的半導體封裝結構的製造方法，其中在配置所述晶片於所述半導體基板的所述開口中之後，在所述晶片以及所述半導體基板之間形成間隙。
  4. 一種半導體封裝結構，包括： 半導體基板，具有第一表面以及相對於所述第一表面的第二表面，其中所述半導體基板包括貫穿所述半導體基板的多個通孔以及開口； 晶片，配置於所述半導體基板的所述開口中； 第一重佈線路層，位於所述半導體基板的所述第一表面上； 第二重佈線路層，位於所述半導體基板的所述第二表面上，其中所述第二重佈線路層電性連接至所述晶片； 導電貫孔，位於所述半導體基板的所述通孔中，其中所述第一重佈線路層藉由所述導電貫孔電性連接至所述第二重佈線路層；以及 多個所述導電結構，位於所述第二重佈線路層上。
  5. 如申請專利範圍第4項所述的半導體封裝結構，更包括： 絕緣層，使所述半導體基板電性隔離。
  6. 如申請專利範圍第4項所述的半導體封裝結構，更包括： 黏著層，位於所述第一重佈線路層以及所述晶片之間。
  7. 如申請專利範圍第4項所述的半導體封裝結構，其中在所述晶片以及對應於所述開口的所述半導體基板之間具有間隙，且所述間隙中包括填料。
  8. 如申請專利範圍第4項所述的半導體封裝結構，其中所述導電貫孔共形設置於所述半導體基板的所述通孔中。
  9. 如申請專利範圍第4項所述的半導體封裝結構，其中所述導電貫孔包括位於所述半導體基板的所述通孔中的導電柱。
  10. 如申請專利範圍第4項所述的半導體封裝結構，更包括： 遮蓋層，位於所述半導體基板的所述第二表面上以及所述晶片上，其中所述遮蓋層部分覆蓋所述半導體基板以及所述晶片。
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