TWI664722B - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

Info

Publication number
TWI664722B
TWI664722B TW106144899A TW106144899A TWI664722B TW I664722 B TWI664722 B TW I664722B TW 106144899 A TW106144899 A TW 106144899A TW 106144899 A TW106144899 A TW 106144899A TW I664722 B TWI664722 B TW I664722B
Authority
TW
Taiwan
Prior art keywords
carrier
wafer
semiconductor structure
adhesive layer
manufacturing
Prior art date
Application number
TW106144899A
Other languages
English (en)
Other versions
TW201841355A (zh
Inventor
何彥仕
劉滄宇
林佳昇
賴炯霖
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201841355A publication Critical patent/TW201841355A/zh
Application granted granted Critical
Publication of TWI664722B publication Critical patent/TWI664722B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一種半導體結構的製作方法包含下列步驟：使用第一暫時黏著層將第一載體貼附於晶圓的第一表面上。蝕刻晶圓背對第一載體的第二表面，以形成至少一穿孔與至少一溝槽，其中晶圓的焊墊由穿孔裸露。形成絕緣層於晶圓的第二表面上、穿孔的壁面上與溝槽的壁面上。使用第二暫時黏著層將第二載體貼附於晶圓的第二表面上，使得穿孔與溝槽由第二載體覆蓋。移除第一載體與第一暫時黏著層。

Description

半導體結構及其製作方法
本案是關於一種半導體結構的製作方法。
一般而言，在製作具有影像感測區的半導體結構時，會先將光學玻璃以間隔元件接合於晶圓上，之後才進行有關蝕刻、化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍或研磨製程。然而，由於光學玻璃與間隔元件的熱擴散係數(Coefficient Thermal Expansion；CTE)不同，在經高溫製程(例如化學氣相沉積)後可能會造成光學玻璃、間隔元件與晶圓翹曲(Warpage)。
上述的翹曲現象在具有大尺寸影像感測區的半導體結構更為明顯。由於間隔元件位在影像感測區外側，影像感測區越大表示間隔元件對於光學玻璃與晶圓的支撐力越小，因此越容易發生翹曲。如此一來，在切割翹曲的且堆疊的光學玻璃、間隔元件與晶圓後，所形成的晶片封裝體其良率難以提升。
本發明之一技術態樣為一種半導體結構的製作方法。
根據本發明一實施方式，一種半導體結構的製作方法包含下列步驟：(a)使用第一暫時黏著層將第一載體貼附於晶圓的第一表面上。(b)蝕刻晶圓背對第一載體的第二表面，以形成至少一穿孔與至少一溝槽，其中晶圓的焊墊由穿孔裸露。(c)形成絕緣層於晶圓的第二表面上、穿孔的壁面上與溝槽的壁面上。(d)使用第二暫時黏著層將第二載體貼附於晶圓的第二表面上，使得穿孔與溝槽由第二載體覆蓋。(e)移除第一載體與第一暫時黏著層。
在本發明一實施方式中，上述半導體結構的製作方法更包含形成重佈線層於絕緣層上與焊墊上。
在本發明一實施方式中，上述步驟(a)包含使用具有第一波長的第一紫外光照射第一暫時黏著層，使第一暫時黏著層產生黏性。
在本發明一實施方式中，上述步驟(e)包含使用具有第二波長的第二紫外光照射第一暫時黏著層，以消除第一暫時黏著層的黏性，其中第二波長不同於第一波長。
在本發明一實施方式中，上述步驟(d)包含使用具有第一波長的第一紫外光照射第二暫時黏著層，使第二暫時黏著層產生黏性。
在本發明一實施方式中，在上述步驟(e)後，半導體結構的製作方法更包含將具有間隔元件的光學元件設置於 晶圓的第一表面上，使得間隔元件位於光學元件與第一表面之間，其中間隔元件覆蓋焊墊與溝槽，且圍繞晶圓的影像感測區。
在本發明一實施方式中，上述半導體結構的製作方法更包含在光學元件設置於晶圓的第一表面後，移除第二載體與第二暫時黏著層。
在本發明一實施方式中，上述移除第二載體的步驟包含使用具有第二波長的第二紫外光照射第二暫時黏著層，以消除第二暫時黏著層的黏性，其中第二波長不同於第一波長。
在本發明一實施方式中，上述半導體結構的製作方法更包含在移除第二載體與第二暫時黏著層後，形成阻隔層覆蓋重佈線層、穿孔與溝槽。
在本發明一實施方式中，上述形成阻隔層的步驟包含以阻隔層填滿溝槽。
在本發明一實施方式中，上述半導體結構的製作方法更包含圖案化阻隔層，使阻隔層具有裸露重佈線層的至少一開口。
在本發明一實施方式中，上述半導體結構的製作方法更包含形成導電結構於阻隔層之開口中的重佈線層上。
在本發明一實施方式中，上述半導體結構的製作方法更包含在形成導電結構後，沿溝槽縱向切割光學元件、間隔元件與阻隔層，以形成至少一晶片封裝體。
在本發明一實施方式中，上述光學元件係以玻璃製成。
在本發明一實施方式中，上述光學元件的透光度均大於第一載體的透光度與第二載體的透光度。
在本發明一實施方式中，上述光學元件的厚度均小於第一載體的厚度與第二載體的厚度。
在本發明上述實施方式中，由於半導體結構的製作方法在形成穿孔、溝槽與絕緣層前，尚未設置間隔元件與光學元件，而是以第一暫時黏著層將第一載體貼附於晶圓上，讓第一載體可對晶圓提供足夠的支撐力，避免晶圓因高溫而產生翹曲。此外，在形成絕緣層後，可使用第二暫時黏著層將第二載體貼附於晶圓的第二表面上，利用第二載體對晶圓的支撐力，使得第一載體可被移除而不會使晶圓彎曲破裂。由於第一載體移除後已無高溫製程，因此將具有間隔元件的光學元件設置於晶圓的第一表面上並不會在後續製程中發生光學元件、間隔元件與晶圓翹曲的現象。
100、100a、100b、100c‧‧‧晶片封裝體
110‧‧‧第一暫時黏著層
120‧‧‧第一載體
130‧‧‧晶圓
130a、130b‧‧‧晶片
131‧‧‧穿孔
132‧‧‧第一表面
133‧‧‧溝槽
134‧‧‧第二表面
136、136a‧‧‧影像感測區
138、138a‧‧‧焊墊
139‧‧‧絕緣層
140‧‧‧絕緣層
150‧‧‧重佈線層
160‧‧‧第二載體
170‧‧‧第二暫時黏著層
180、180a、180b‧‧‧光學元件
181‧‧‧頂面
182、182a、182b‧‧‧支撐部
183‧‧‧底面
184、184a、184b、184c‧‧‧透鏡部
186‧‧‧容置空間
190、190a‧‧‧間隔元件
192‧‧‧黏膠
210‧‧‧阻隔層
212‧‧‧開口
220‧‧‧導電結構
L-L‧‧‧線段
S1~S5‧‧‧步驟
第1圖繪示根據本發明一實施方式之半導體結構的製作方法的流程圖。
第2圖至第10圖繪示根據本發明一實施方式之半導體結構的製作方法的剖面圖。
第11圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第12圖繪示根據本發明一實施方式之晶片封裝體的剖面 圖。
第13圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
以下配合圖式說明本發明之複數個實施方式，為簡化圖式，一些習知慣用的結構與元件將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之半導體結構的製作方法的流程圖。半導體結構的製作方法包含下列步驟。首先在步驟S1中，使用第一暫時黏著層將第一載體貼附於晶圓的第一表面上。接著在步驟S2中，蝕刻晶圓背對第一載體的第二表面，以形成至少一穿孔與至少一溝槽，其中晶圓的焊墊由穿孔裸露。之後在步驟S3中，形成絕緣層於晶圓的第二表面上、穿孔的壁面上與溝槽的壁面上。接著在步驟S4，使用第二暫時黏著層將第二載體貼附於晶圓的第二表面上，使得穿孔與溝槽由第二載體覆蓋。之後在步驟S5中，移除第一載體與第一暫時黏著層。
在以下敘述中，將說明上述各步驟。
第2圖至第10圖繪示根據本發明一實施方式之半導體結構的製作方法的剖面圖。請參閱第2圖，晶圓130具有相對的第一表面132與第二表面134、影像感測區136、焊墊138與絕緣層139。影像感測區136、焊墊138與絕緣層139位於第一表面132上。晶圓130的材質可包含矽，例如為矽晶圓。 第一暫時黏著層110位於第一載體120與晶圓130之間，也就是說，第一載體120利用第一暫時黏著層110貼附於晶圓130的第一表面132上。第一暫時黏著層110可經不同波長的紫外光照射而產生黏性或消除黏性。在此步驟中，可使用具有第一波長的第一紫外光照射第一暫時黏著層110，使第一暫時黏著層110產生黏性。
第一載體120可對晶圓130提供支撐力，避免晶圓130於後續製程中破裂。此外，第一載體120還可保護晶圓130的影像感測區136與焊墊138，避免於後續製程中損壞。在本實施方式中，第一載體120的材質可以為玻璃或壓克力。
同時參閱第2圖與第3圖，待第一載體120以第一暫時黏著層110貼附於晶圓130後，可蝕刻晶圓130的第二表面134，以形成至少一穿孔131與至少一溝槽133，使晶圓130的焊墊138由穿孔131裸露。也就是說，穿孔131的位置對應於焊墊138的位置。此外，穿孔131較靠近影像感測區136，溝槽133離影像感測區136較遠，且溝槽133至少部分位於兩個穿孔131之間。
同時參閱第3圖與第4圖，待穿孔131與溝槽133形成後，可形成絕緣層140於晶圓130的第二表面134上、穿孔131的壁面上與溝槽133的壁面上。在此步驟中，絕緣層140可先以化學氣相沉積法(CVD)覆蓋晶圓130的第二表面134、穿孔131的壁面、焊墊138與溝槽133的壁面，接著以圖案化製程去除覆蓋焊墊138下表面的絕緣層140，而得到第4圖的結構。圖案化製程可包含曝光、顯影、蝕刻等光微影技術 (Photolithography)。在本實施方式中，絕緣層140的材質可以為二氧化矽，且絕緣層139的材質可與絕緣層140相同。
同時參閱第4圖與第5圖，待絕緣層140形成後，重佈線層150可形成於絕緣層140上與焊墊138上，而與焊墊138電性接觸。重佈線層150的材質可以包含鋁，可採用電鍍的方式形成，但並不用以限制本發明。
同時參閱第5圖與第6圖，待重佈線層150形成後，可使用第二暫時黏著層170將第二載體160貼附於晶圓130的第二表面134上，使得穿孔131與溝槽133由第二載體160覆蓋。第二暫時黏著層170位於第二載體160與晶圓130之間，也就是說，第二載體160利用第二暫時黏著層170貼附於晶圓130的第二表面134上。第二暫時黏著層170的材質可與第一暫時黏著層110的材質相同。第二暫時黏著層170可經不同波長的紫外光照射而產生黏性或消除黏性。在此步驟中，可使用具有第一波長的第一紫外光照射第二暫時黏著層170，使第二暫時黏著層170產生黏性。
第二載體160可對晶圓130提供支撐力，避免晶圓130於後續製程中破裂。此外，第二載體160還可保護重佈線層150，避免於後續製程中損壞。在本實施方式中，第二載體160的材質可以為玻璃或壓克力。
同時參閱第6圖與第7圖，待第二載體160以第二暫時黏著層170貼附於晶圓130下方後，可移除晶圓130上方的第一載體120與第一暫時黏著層110。在此步驟中，可使用具有第二波長的第二紫外光照射第一暫時黏著層110，以消除第 一暫時黏著層110的黏性。上述第二波長不同於第一波長。第一載體120移除後，可重複使用於其他晶圓上，以節省材料成本。
同時參閱第7圖與第8圖，待第一載體120與第一暫時黏著層110移除後，可將具有間隔元件190的光學元件180設置於晶圓130的第一表面132上，使得間隔元件190位於光學元件180與第一表面132之間。間隔元件190覆蓋焊墊138與溝槽133，且間隔元件190圍繞晶圓130的影像感測區136。間隔元件190可利用黏膠192固定於晶圓130的第一表面132上。在間隔元件190接合晶圓130之前，間隔元件190可先設置於光學元件180的表面。
在本實施方式中，間隔元件190的材質可以包含環氧樹脂(Epoxy)。光學元件180係以玻璃製成，光學元件180用以供光線穿過，以讓其下方的影像感測區136感測。因此，對於光學元件180之物理特性的要求與用來支撐晶圓130之第一載體120(見第6圖)、第二載體160不同。舉例來說，光學元件180的透光度均大於第一載體120的透光度與第二載體160的透光度。此外，光學元件180的厚度可小於第一載體120的厚度與第二載體160的厚度，以降低整個半導體結構的厚度。第7圖與第8圖的半導體結構可採晶圓級尺寸(Wafer level)出貨，依製造者需求而定。
光學元件180可以為抗反射(AR)玻璃或紅外線(IR)玻璃，但並不用以限制本發明。另外，光學元件180的材質可以包含燃料二氧化矽(Fuel silica)。
由於半導體結構的製作方法在形成穿孔131、溝槽133與絕緣層140前，尚未設置間隔元件190與光學元件180，而是以第一暫時黏著層110將第一載體120貼附於晶圓130上，讓第一載體120可對晶圓130提供足夠的支撐力，避免晶圓130因高溫(例如形成絕緣層140的CVD製程)而產生翹曲。此外，在形成絕緣層140後，可使用第二暫時黏著層170將第二載體160貼附於晶圓130的第二表面134上，利用第二載體160對晶圓130的支撐力，使得第一載體120可被移除而不會使晶圓130彎曲破裂。由於第一載體120移除後已無高溫製程，因此將具有間隔元件190的光學元件180設置於晶圓130的第一表面132上並不會在後續製程中發生光學元件180、間隔元件190與晶圓130翹曲的現象。
同時參閱第8圖與第9圖，待光學元件180設置於晶圓130的第一表面132後，可移除第二載體160與第二暫時黏著層170。在此步驟中，可使用具有第二波長的第二紫外光照射第二暫時黏著層170，以消除第二暫時黏著層170的黏性。第二載體160移除後，可重複使用於其他晶圓上，以節省材料成本。
待移除第二載體160與第二暫時黏著層170後，可形成阻隔層210覆蓋重佈線層150、穿孔131與溝槽133。在此步驟中，阻隔層210可填滿溝槽133。接著，可圖案化阻隔層210，使阻隔層210具有裸露重佈線層150的至少一開口212。在本實施方式中，阻隔層210的材質可以包含環氧樹脂，例如防焊綠漆(Solder mask)。
同時參閱第9圖與第10圖，待阻隔層210的開口212形成後，可形成導電結構220於阻隔層210之開口212中的重佈線層150上。導電結構220可以為球閘陣列(Ball Grid Array；BGA)的導電球體(例如錫球)或導電凸塊，其形狀與材質並不用以限制本發明。
待形成導電結構220後，可沿溝槽133縱向切割光學元件180、間隔元件190與阻隔層210。舉例來說，可用刀具沿線段L-L切割光學元件180、間隔元件190與阻隔層210，以形成第10圖的晶片封裝體100。晶圓130經切割製程後可產生至少一個第10圖的晶片130a。
導電結構220可電性連接外部電子裝置(如電路板)，以將訊號透過重佈線層150傳輸至晶片封裝體100的焊墊138。在本實施方式中，晶片封裝體100可以為影像感測晶片(例如CMOS晶片)，但並不用以限制本發明。
第11圖繪示根據本發明一實施方式之晶片封裝體100a的剖面圖。晶片封裝體100a為半導體結構，其包含晶片130a、間隔元件190與光學元件180a。晶片130a其一表面具有焊墊138與影像感測區136。間隔元件190覆蓋焊墊138且圍繞影像感測區136。光學元件180a設置於間隔元件190上且覆蓋影像感測區136。光學元件180a具有頂面181與底面183，底面183朝向影像感測區136，頂面181背對影像感測區136。與10圖實施方式不同的地方在於光學元件180a的頂面181為圓弧狀。在本實施方式中，光學元件180a包含支撐部182與透鏡部184。支撐部182位於間隔元件190上且具有底面 183。透鏡部184位於支撐部182上且具有頂面181，且透鏡部184覆蓋影像感測區136。
第12圖繪示根據本發明一實施方式之晶片封裝體100b的剖面圖。晶片封裝體100b包含晶片130a、間隔元件190與光學元件180b。與11圖實施方式不同的地方在於晶片封裝體100b還包含晶片130b與間隔元件190a。晶片130b與晶片130a相鄰。晶片130b的一表面具有焊墊138a與影像感測區136a。間隔元件190a覆蓋焊墊138a，且圍繞影像感測區136a。此外，光學元件180b從間隔元件190延伸至間隔元件190a而覆蓋晶片130b的影像感測區136a。光學元件180b的部分底面183的朝向影像感測區136a，部分頂面181背對影像感測區136a。在本實施方式中，光學元件180b包含支撐部182a與兩透鏡部184a、184b。支撐部182a位於間隔元件190與間隔元件190a上，且具有底面183。透鏡部184a、184b位於支撐部182a上且具有頂面181。透鏡部184a、184b分別覆蓋影像感測區136、136a。
第13圖繪示根據本發明一實施方式之晶片封裝體100c的剖面圖。晶片封裝體100c包含晶片130a、間隔元件190與光學元件180c。與11圖實施方式不同的地方在於光學元件180c包含支撐部182b與複數個透鏡部184c。支撐部182b位於間隔元件190上且圍繞出容置空間186。透鏡部184c實體連接於支撐部182b且位於容置空間186中。透鏡部184c與影像感測區136重疊。透鏡部184c的數量並不用以限制本發明。此外，透鏡部184c的其中之一(最上方的透鏡部184c)具有頂面 181，且透鏡部184a的其中之一(最下方的透鏡部184c)具有底面183。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (14)

  1. 一種半導體結構的製作方法，包含下列步驟：(a)使用一第一暫時黏著層將一第一載體貼附於一晶圓的一第一表面上；(b)蝕刻該晶圓背對該第一載體的一第二表面，以形成至少一穿孔與至少一溝槽，其中該晶圓的一焊墊由該穿孔裸露；(c)形成一絕緣層於該晶圓的該第二表面上、該穿孔的壁面上與該溝槽的壁面上；(d)使用一第二暫時黏著層將一第二載體貼附於該晶圓的該第二表面上，使得該穿孔與該溝槽由該第二載體覆蓋；(e)形成一重佈線層於該絕緣層上與該焊墊上；(f)移除該第一載體與該第一暫時黏著層；(g)將具有一間隔元件的一光學元件設置於該晶圓的該第一表面上，使得該間隔元件位於該光學元件與該第一表面之間，其中該間隔元件覆蓋該焊墊與該溝槽，且圍繞該晶圓的一影像感測區；(h)在該光學元件設置於該晶圓的該第一表面後，移除該第二載體與該第二暫時黏著層；以及(i)在移除該第二載體與該第二暫時黏著層後，形成一阻隔層覆蓋該重佈線層、該穿孔與該溝槽。
  2. 如請求項1所述的半導體結構的製作方法，該步驟(a)包含：使用具有一第一波長的一第一紫外光照射該第一暫時黏著層，使該第一暫時黏著層產生黏性。
  3. 如請求項2所述的半導體結構的製作方法，該步驟(f)包含：使用具有一第二波長的一第二紫外光照射該第一暫時黏著層，以消除該第一暫時黏著層的黏性，其中該第二波長不同於該第一波長。
  4. 如請求項1所述的半導體結構的製作方法，該步驟(d)包含：使用具有一第一波長的一第一紫外光照射該第二暫時黏著層，使該第二暫時黏著層產生黏性。
  5. 如請求項4所述的半導體結構的製作方法，移除該第二載體的步驟包含：使用具有一第二波長的一第二紫外光照射該第二暫時黏著層，以消除該第二暫時黏著層的黏性，其中該第二波長不同於該第一波長。
  6. 如請求項4所述的半導體結構的製作方法，形成該阻隔層的步驟包含：以該阻隔層填滿該溝槽。
  7. 如請求項4所述的半導體結構的製作方法，更包含：圖案化該阻隔層，使該阻隔層具有裸露該重佈線層的至少一開口。
  8. 如請求項7所述的半導體結構的製作方法，更包含：形成一導電結構於該阻隔層之該開口中的該重佈線層上。
  9. 如請求項8所述的半導體結構的製作方法，更包含：在形成該導電結構後，沿該溝槽縱向切割該光學元件、該間隔元件與該阻隔層，以形成至少一晶片封裝體。
  10. 如請求項4所述的半導體結構的製作方法，其中該光學元件係以玻璃製成。
  11. 如請求項4所述的半導體結構的製作方法，其中該光學元件的透光度均大於該第一載體的透光度與該第二載體的透光度。
  12. 如請求項4所述的半導體結構的製作方法，其中該光學元件的厚度均小於該第一載體的厚度與該第二載體的厚度。
  13. 如請求項4所述的半導體結構的製作方法，其中該光學元件為抗反射玻璃或紅外線玻璃。
  14. 如請求項4所述的半導體結構的製作方法，其中該光學元件的材質包含燃料二氧化矽。
TW106144899A 2016-12-20 2017-12-20 半導體結構及其製作方法 TWI664722B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662436655P 2016-12-20 2016-12-20
US62/436,655 2016-12-20

Publications (2)

Publication Number Publication Date
TW201841355A TW201841355A (zh) 2018-11-16
TWI664722B true TWI664722B (zh) 2019-07-01

Family

ID=62561892

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106144899A TWI664722B (zh) 2016-12-20 2017-12-20 半導體結構及其製作方法

Country Status (3)

Country Link
US (1) US10461117B2 (zh)
CN (1) CN108206195B (zh)
TW (1) TWI664722B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI649856B (zh) * 2016-05-13 2019-02-01 精材科技股份有限公司 晶片封裝體與其製造方法
KR20210080718A (ko) 2019-12-20 2021-07-01 삼성전자주식회사 반도체 패키지

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050158009A1 (en) * 2000-02-10 2005-07-21 Epic Technologies, Inc. Structure and method for temporarily holding integrated circuit chips in accurate alignment
US20080224192A1 (en) * 2007-03-14 2008-09-18 Luke England Packaging methods for imager devices
US20090134483A1 (en) * 2007-11-23 2009-05-28 Jui-Ping Weng Electronic assembly for image sensor device
US20120193741A1 (en) * 2011-01-31 2012-08-02 Swarnal Borthakur Methods for forming backside illuminated image sensors with front side metal redistribution layers
US20140110807A1 (en) * 2008-11-11 2014-04-24 Lapis Semiconductor Co., Ltd. Camera module
US20160020238A1 (en) * 2013-03-01 2016-01-21 Ams Ag Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation
US20160163755A1 (en) * 2014-12-09 2016-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor chip sidewall interconnection

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307243B1 (en) * 1999-07-19 2001-10-23 Micron Technology, Inc. Microlens array with improved fill factor
US6531341B1 (en) * 2000-05-16 2003-03-11 Sandia Corporation Method of fabricating a microelectronic device package with an integral window
JP2001358997A (ja) * 2000-06-12 2001-12-26 Mitsubishi Electric Corp 半導体装置
JP3773177B2 (ja) * 2001-11-30 2006-05-10 松下電器産業株式会社 固体撮像装置およびその製造方法
US7288757B2 (en) * 2005-09-01 2007-10-30 Micron Technology, Inc. Microelectronic imaging devices and associated methods for attaching transmissive elements
CN1956202A (zh) * 2005-10-24 2007-05-02 台湾沛晶股份有限公司 影像芯片构装结构及其构装方法
JP4160083B2 (ja) * 2006-04-11 2008-10-01 シャープ株式会社 光学装置用モジュール及び光学装置用モジュールの製造方法
US7923298B2 (en) * 2007-09-07 2011-04-12 Micron Technology, Inc. Imager die package and methods of packaging an imager die on a temporary carrier
US20090206431A1 (en) * 2008-02-20 2009-08-20 Micron Technology, Inc. Imager wafer level module and method of fabrication and use
CN101620303B (zh) * 2008-06-30 2011-06-08 鸿富锦精密工业（深圳）有限公司 相机模组
US8367477B2 (en) * 2009-03-13 2013-02-05 Wen-Cheng Chien Electronic device package and method for forming the same
TWI425597B (zh) * 2009-12-31 2014-02-01 Kingpak Tech Inc 具有黑色膠體之影像感測器封裝結構
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
TWI449162B (zh) * 2010-05-17 2014-08-11 Kingpak Tech Inc 具有特定焦距之晶圓級影像感測器模組之製造方法
JP2012009816A (ja) * 2010-05-28 2012-01-12 Casio Comput Co Ltd 半導体装置およびその製造方法
US8692358B2 (en) * 2010-08-26 2014-04-08 Yu-Lung Huang Image sensor chip package and method for forming the same
CN103101875A (zh) * 2011-11-11 2013-05-15 精材科技股份有限公司 半导体封装件及其制法
TWI585959B (zh) * 2014-08-13 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
US9543347B2 (en) * 2015-02-24 2017-01-10 Optiz, Inc. Stress released image sensor package structure and method
US10157943B2 (en) * 2016-01-22 2018-12-18 Omnivision Technologies, Inc. Trenched-bonding-dam device and manufacturing method for same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050158009A1 (en) * 2000-02-10 2005-07-21 Epic Technologies, Inc. Structure and method for temporarily holding integrated circuit chips in accurate alignment
US20080224192A1 (en) * 2007-03-14 2008-09-18 Luke England Packaging methods for imager devices
US20090134483A1 (en) * 2007-11-23 2009-05-28 Jui-Ping Weng Electronic assembly for image sensor device
US20140110807A1 (en) * 2008-11-11 2014-04-24 Lapis Semiconductor Co., Ltd. Camera module
US20120193741A1 (en) * 2011-01-31 2012-08-02 Swarnal Borthakur Methods for forming backside illuminated image sensors with front side metal redistribution layers
US20160020238A1 (en) * 2013-03-01 2016-01-21 Ams Ag Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation
US20160163755A1 (en) * 2014-12-09 2016-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor chip sidewall interconnection

Also Published As

Publication number Publication date
CN108206195A (zh) 2018-06-26
TW201841355A (zh) 2018-11-16
US10461117B2 (en) 2019-10-29
CN108206195B (zh) 2020-08-25
US20180175101A1 (en) 2018-06-21

Similar Documents

Publication Publication Date Title
TWI629759B (zh) 晶片封裝體及其製造方法
TWI549247B (zh) 晶片封裝體
TWI614852B (zh) 晶片封裝體及其製造方法
TWI474476B (zh) 晶片封裝體及其形成方法
TWI726148B (zh) 光學裝置及其製造方法
US20160190353A1 (en) Photosensitive module and method for forming the same
US9142486B2 (en) Chip package and fabrication method thereof
TWI529821B (zh) 晶片封裝體及其形成方法
TWI642149B (zh) 晶片封裝體及其製造方法
TWI624039B (zh) 晶片封裝體及其製造方法
US9966400B2 (en) Photosensitive module and method for forming the same
TW201707199A (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TWI600125B (zh) 晶片封裝體及其製造方法
TWI620284B (zh) 晶片封裝體及其製造方法
JP6933697B2 (ja) チップパッケージおよびその製造方法
TW201715672A (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TW201742200A (zh) 晶片封裝體及其製造方法
TWI664722B (zh) 半導體結構及其製作方法
CN110797358B (zh) 晶片封装体及其制造方法
TWI588954B (zh) 晶片封裝體及其製造方法
JP2010263145A (ja) 半導体装置及びその製造方法
TWI564975B (zh) 晶片封裝體及其製造方法
JP6564525B2 (ja) 半導体チップパッケージ構造およびそのためのパッケージング方法
TWI585957B (zh) 半導體結構的製造方法
TW201712818A (zh) 晶片封裝體及其製造方法