TWI642149B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI642149B
TWI642149B TW105133520A TW105133520A TWI642149B TW I642149 B TWI642149 B TW I642149B TW 105133520 A TW105133520 A TW 105133520A TW 105133520 A TW105133520 A TW 105133520A TW I642149 B TWI642149 B TW I642149B
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Taiwan
Prior art keywords
substrate
conductive structure
chip package
passive
layer
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TW105133520A
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TW201715662A (zh
Inventor
何彥仕
劉滄宇
李柏漢
廖季昌
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精材科技股份有限公司
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Publication of TW201715662A publication Critical patent/TW201715662A/zh
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Abstract

本發明揭露一種晶片封裝體，包括一基底。基底內具有一感測區或元件區。一第一導電結構位於基底上，且與感測區或元件區電性連接。一被動元件縱向地堆疊於基底上，且與第一導電結構橫向排列。本發明亦揭露一種晶片封裝體的製造方法。

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種具有被動元件的晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
一般而言，晶片封裝體與其他電子元件(例如，被動元件)各自獨立地設置於電路板上，且間接地彼此電性連接。然而如此一來，電路板的尺寸受到限制，進而導致所形成的電子產品的尺寸難以進一步縮小。再者，由於晶片封裝體與其他電子元件之間的電性傳輸路徑長，造成電子產品的功率(power)及/或訊號(signal)的衰減程度高，也容易產生雜訊(noise)，因此降低了電子產品的品質。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一基底。基底內具有一感測區或元件區。一第一導電結構位於基底上，且與感測區或元件區電性連接。一被動元件縱向地堆疊於 基底上，且與第一導電結構橫向排列。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一基底。基底內具有一感測區或元件區。在基底上形成一第一導電結構。第一導電結構與感測區或元件區電性連接。將一被動元件縱向地堆疊於基底上。被動元件與第一導電結構橫向排列。
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧晶片區
120‧‧‧感測區或元件區
130‧‧‧絕緣層
140‧‧‧導電墊
150‧‧‧光學部件
160‧‧‧間隔層
170‧‧‧蓋板
180‧‧‧空腔
190‧‧‧開口
210‧‧‧絕緣層
220‧‧‧重佈線層
230‧‧‧保護層
240‧‧‧開口
250‧‧‧開口
260‧‧‧第一導電結構
270‧‧‧接合層
300‧‧‧被動元件
310‧‧‧元件區
320‧‧‧接合結構
330‧‧‧開口
340‧‧‧絕緣層
350‧‧‧重佈線層
360‧‧‧保護層
370‧‧‧開口
380‧‧‧第二導電結構
A‧‧‧晶片封裝結構
P‧‧‧平面
第1A至1E圖係繪示出根據本發明某些實施例之晶片封裝體的製造方法的剖面示意圖。
第2圖係繪示出根據本發明某些實施例之被動元件的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明某些實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體 的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體或系統級封裝(System in Package，SIP)之晶片封裝體。
請參照第1E圖及第2圖，第1E圖繪示出根據本發明 某些實施例之晶片封裝體的剖面示意圖，且第2圖係繪示出根據本發明某些實施例之被動元件的剖面示意圖。晶片封裝體包括具有一基底100的晶片封裝結構A。基底100具有一第一表面100a及與其相對的一第二表面100b。在某些實施例中，基底100可為一矽基底或其他半導體基底。
在某些實施例中，基底100內具有一感測區或元件區120。感測區或元件區120可鄰近於第一表面100a，且感測區或元件區120內可包括一感測元件及/或一主動元件(例如，電晶體)。在某些實施例中，感測區或元件區120內包括感光元件或其他適合的光電元件。在其他實施例中，感測區或元件區120內可包括感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
基底100的第一表面100a上具有一絕緣層130。一般而言，絕緣層130可由層間介電層(interlayer dielectric，ILD)、金屬間介電層(inter-metal dielectric，IMD)及覆蓋之鈍化層(passivation)組成。為簡化圖式，此處僅繪示出單層絕緣層130。換句話說，晶片封裝結構A包括由基底100及絕緣層130所構成的一晶片/晶粒。在某些實施例中，絕緣層130可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在某些實施例中，基底100的第一表面100a上的絕緣層130內具有一個或一個以上的導電墊140。在某些實施例中，導電墊140可為單層導電層或具有多層之導電層結構。為 簡化圖式，此處僅以單層導電層作為範例說明，並以絕緣層130內的兩個導電墊140作為範例說明。在某些實施例中，絕緣層130內包括一個或一個以上的開口，露出對應的導電墊140。在某些實施例中，感測區或元件區120可透過基底100內的內連線結構(未繪示)而與導電墊140電性連接。
在某些實施例中，一光學部件150設置於絕緣層130上，且對應於感測區或元件區120。在某些實施例中，光學部件150可為微透鏡陣列、濾光層、其組合或其他適合的光學部件。在某些其他實施例中，晶片封裝結構A可不包括光學部件150。
在某些實施例中，一蓋板170設置於基底100的第一表面100a上，以保護光學部件150。在某些其他實施例中，晶片封裝結構A可不包括蓋板170，因而露出絕緣層130及光學部件150。在某些實施例中，蓋板170可包括玻璃、石英、透明高分子或其他適合的透明材料。
在某些實施例中，基底100與蓋板170之間具有一間隔層(或稱作圍堰(dam))160，覆蓋導電墊140而露出光學部件150。在某些實施例中，間隔層160、蓋板170及絕緣層130在感測區或元件區120上共同圍繞出一空腔180，使得光學部件150位於空腔180內。在某些其他實施例中，晶片封裝結構A可不包括間隔層160。
在某些實施例中，間隔層160大致上不吸收水氣。在某些實施例中，間隔層160不具有黏性，因此可透過額外的黏著膠將蓋板170貼附於基底100上。在某些其他實施例中，間 隔層160可具有黏性，因此可透過間隔層160將蓋板170貼附於基底100上，如此一來間隔層160可不與任何的黏著膠接觸，以確保間隔層160之位置不因黏著膠而移動。同時，由於不需使用黏著膠，可避免黏著膠溢流而污染光學部件150。
在某些實施例中，間隔層160可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))、光阻材料或其他適合的絕緣材料。
在某些實施例中，多個開口190貫穿基底100且延伸至絕緣層130內，進而自基底100的第二表面100b露出對應的導電墊140。在某些實施例中，開口190鄰近於第一表面100a的口徑小於其鄰近於第二表面100b的口徑，因此開口190具有傾斜的側壁。在某些其他實施例中，開口190鄰近於第一表面100a的口徑可能等於或大於其鄰近於第二表面100b的口徑。
在某些實施例中，一絕緣層210設置於基底100的第二表面100b上，且順應性地延伸至開口190的側壁上，並露出導電墊140。在某些實施例中，絕緣層210可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
在某些實施例中，一圖案化的重佈線層220設置於 基底100的第二表面100b上，且順應性地延伸至開口190的側壁及底部上。重佈線層220可透過絕緣層210與基底100電性隔離，且可經由開口190直接電性接觸或間接電性連接露出的導電墊140。因此，開口190內的重佈線層220也稱為矽通孔電極(through silicon via，TSV)。在其他實施例中，重佈線層220也可能以T型接觸(T-contact)或其他適合的方式電性連接至對應的導電墊140。
在某些實施例中，重佈線層220可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。
在某些實施例中，一保護層230設置於基底100的第二表面100b上，且填入開口190，以覆蓋重佈線層220。在某些實施例中，保護層230未填滿開口190，使得一孔洞形成於開口190內的重佈線層220與保護層230之間。在某些其他實施例中，保護層230填滿開口190。在某些實施例中，保護層230具有平坦的表面。在某些其他實施例中，保護層230具有不平坦的表面，例如保護層230的表面具有對應於開口190的凹陷部。
在某些實施例中，保護層230可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
基底100的第二表面100b上的保護層230具有開口240及250，露出重佈線層220的一部份。在某些實施例中，開 口240的寬度大於開口250的寬度。在某些其他實施例中，開口240的寬度可能等於或小於開口250的寬度。
在某些實施例中，多個第一導電結構260(例如，焊球、凸塊或導電柱)設置於保護層230的多個開口240內，以與露出的重佈線層220及感測區或元件區120電性連接。在某些實施例中，第一導電結構260可包括錫、鉛、銅、金、鎳、其他適合的導電材料、或前述之組合。
在某些實施例中，接合層270設置於保護層230的開口250內，而與露出的重佈線層220電性連接。在某些實施例中，接合層270可包括錫、鉛、銅、金、鎳、其他適合的接合材料、或前述之組合。在某些實施例中，接合層270的材料相同於第一導電結構260的材料。在某些其他實施例中，接合層270的材料不同於第一導電結構260的材料。
在某些實施例中，一被動元件300縱向地堆疊於基底100上，被動元件300與基底100並非彼此橫向排列。被動元件300與第一導電結構260位於基底100的同一側，且彼此橫向排列。再者，被動元件300與光學部件150位於基底100的相對兩側，被動元件300與蓋板170位於基底100的相對兩側。在某些實施例中，多個第一導電結構260非連續地或分散地環繞被動元件300。
在某些實施例中，被動元件300的厚度小於第一導電結構260的厚度。在某些實施例中，被動元件300的尺寸小於基底100的尺寸。再者，當基底100的尺寸足夠大或被動元件300的尺寸足夠小時，可在基底100的第二表面100b上設置一個以 上具有相同或不同功能的被動元件300。在某些實施例中，被動元件300對應於基底100的中心，且完全或局部重疊於感測區或元件區120。在某些其他實施例中，被動元件300可能未重疊於感測區或元件區120。
在某些實施例中，被動元件300可為積體/整合被動元件(integrated passive device，IPD)。在某些其他實施例中，被動元件300可為電阻、電容、電感或其他適合的被動元件。如第2圖所示，被動元件300內具有一元件區310。元件區310內的電路可構成電阻、電容、電感、其他適合的被動元件、或其組合。
在某些實施例中，多個接合結構320設置於被動元件300的上表面上，如第2圖所示。接合結構320與元件區310電性連接。在某些實施例中，接合結構320與基底100位於被動元件300的同一側。
在某些實施例中，接合結構320設置於開口250內，且突出於開口250。在某些實施例中，接合結構320直接接觸重佈線層220，且由接合層270所局部環繞，如第1E圖所示。在某些其他實施例中，接合結構320嵌入接合層270內。一部分的接合層270可縱向地夾設於接合結構320與重佈線層220之間。在某些實施例中，接合結構320與第一導電結構260及/或接合層270皆位於重佈線層220上，因此接合結構320與第一導電結構260及/或接合層270位於相同層位。
在某些實施例中，接合結構320的厚度介於大約10μm至大約20μm的範圍內，例如15μm。在某些實施例中，接 合結構320可包括銅、鋁、其他適合的導電材料、或前述之組合。包含銅的接合結構320可在基底100與被動元件300之間提供良好的電性連接路徑，降低功率及/或訊號的衰減。再者，接合結構320也可為晶片封裝結構A提供良好的導熱路徑。
在某些實施例中，接合結構320的材料不同於第一導電結構260及/或接合層270的材料。在某些其他實施例中，接合結構320的材料相同於第一導電結構260及/或接合層270的材料。在某些實施例中，接合結構320為導電柱、導電層或其他適合的接合結構。
如第2圖所示，多個開口330延伸於被動元件300內。元件區310經由開口330自被動元件300的下表面局部露出。在某些實施例中，開口330的結構相同或類似於開口190的結構。再者，一絕緣層340設置於被動元件300的下表面，且絕緣層340順應性地延伸至開口330的側壁上，並局部露出元件區310。在某些實施例中，絕緣層340的結構及/或材料相同或類似於絕緣層210的結構及/或材料。
圖案化的重佈線層350設置於被動元件300的下表面，且順應性地延伸至開口330的側壁及底部上。重佈線層350可經由開口330電性連接露出的元件區310，因此開口330內的重佈線層350也稱為矽通孔電極。在某些實施例中，重佈線層350的結構及/或材料相同或類似於重佈線層220的結構及/或材料。再者，一保護層360設置於被動元件300的下表面，且填入開口330，以覆蓋重佈線層350。在某些實施例中，保護層360的結構及/或材料相同或類似於保護層230的結構及/或材料。
被動元件300的下表面上的保護層360具有開口370，露出重佈線層350的一部份。再者，多個第二導電結構380(例如，焊球、凸塊或導電柱)設置於保護層360的多個開口370內，以與露出的重佈線層350電性連接。第二導電結構380與基底100位於被動元件300的相對兩側。在某些實施例中，第二導電結構380的尺寸小於第一導電結構260的尺寸。在某些實施例中，第二導電結構380的厚度小於接合結構320的厚度。在某些其他實施例中，第二導電結構380的厚度可等於或大於接合結構320的厚度。
在某些實施例中，第二導電結構380可包括錫、鉛、銅、金、鎳、其他適合的導電材料、或前述之組合。在某些實施例中，第二導電結構380的材料相同於第一導電結構260及/或接合結構320的材料。在某些其他實施例中，第二導電結構380的材料不同於第一導電結構260及/或接合結構320的材料。
如第1E圖所示，第二導電結構380的頂部(頂表面)與第一導電結構260的頂部(頂表面)大致上對齊於平面P。換句話說，第二導電結構380的頂部與第一導電結構260的頂部大致上共平面。在某些實施例中，接合結構320、被動元件300及第二導電結構380的總厚度大致上相同於第一導電結構260的厚度。
在某些實施例中，基底100及被動元件300可接合於一電路板(未繪示)上。基底100透過第一導電結構260與電路板物理性連接，且基底100內的感測區或元件區120透過第一導 電結構260與電路板電性連接。被動元件300透過第二導電結構380與電路板物理性及電性連接。在某些實施例中，藉由電路的佈局設計，使得晶片封裝體經由第二導電結構380傳輸功率，且經由第一導電結構260傳輸訊號。在某些其他實施例中，晶片封裝體經由第二導電結構380及某些第一導電結構260傳輸功率，且經由其他的第一導電結構260傳輸訊號。由於功率對電磁效應的影響較大，因此經由第二導電結構380傳輸功率，能夠利用被動元件300提供穩定電流的功能，盡可能避免功率的強度降低。
根據本發明的上述實施例，能夠將一個或一個以上的被動元件整合於晶片封裝體內，而大致上不會增加晶片封裝體的尺寸，如此一來晶片封裝體所連接的電路板不再需要保留設置被動元件的空間，進而可以縮小電路板的尺寸，因此所形成的電子產品的尺寸能夠進一步降低。再者，由於被動元件直接與晶片連接，大幅縮短了被動元件與晶片之間的電性傳輸路徑，因此可避免功率及/或訊號的衰減，也有效防止雜訊的產生，使得電子產品的品質及可靠度提升。
在上述實施例中，晶片封裝體包括前照式(front side illumination，FSI)感測裝置，但在某些其他實施例中，晶片封裝體亦可包括背照式(back side illumination，BSI)感測裝置。另外，雖然上述實施例以光學感測裝置作為範例說明，然而本發明並不限定於此，可以應用本發明將被動元件整合於任何適合類型的晶片封裝體內。
以下配合第1A至1E圖及第2圖說明本發明某些實 施例之晶片封裝體的製造方法，其中第1A至1E圖係繪示出根據本發明某些實施例之晶片封裝體的製造方法的剖面示意圖，且第2圖係繪示出根據本發明某些實施例之被動元件的剖面示意圖。
請參照第1A圖，提供一基底100，其具有一第一表面100a及與其相對的一第二表面100b，且包括複數晶片區110。為簡化圖式，此處僅繪示出單一晶片區110。在某些實施例中，基底100可為一矽基底或其他半導體基底。在某些實施例中，基底100為一矽晶圓，以利於進行晶圓級封裝製程。
在某些實施例中，每一晶片區110的基底100內具有一感測區或元件區120。感測區或元件區120可鄰近於第一表面100a，且感測區或元件區120內可包括一感測元件及/或一主動元件(例如，電晶體)。在某些實施例中，感測區或元件區120內包括感光元件或其他適合的光電元件。在其他實施例中，感測區或元件區120內可包括感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
基底100的第一表面100a上具有一絕緣層130。一般而言，絕緣層130可由層間介電層、金屬間介電層及覆蓋之鈍化層組成。為簡化圖式，此處僅繪示出單層絕緣層130。在某些實施例中，絕緣層130可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在某些實施例中，每一晶片區110的絕緣層130內具有一個或一個以上的導電墊140。在某些實施例中，導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，並以絕緣層130內的兩個導電墊140作為範例說明。在某些實施例中，每一晶片區110的絕緣層130內包括一個或一個以上的開口，露出對應的導電墊140。在某些實施例中，感測區或元件區120內的感測元件可透過基底100內的內連線結構(未繪示)而與導電墊140電性連接。
在某些實施例中，可依序進行半導體裝置的前段(front end)製程及後段(back end)製程來製作前述結構。例如，在進行前段製程期間，在基底100內製作感測區或元件區120，且在進行後段製程期間，在基底100上製作絕緣層130、內連線結構及導電墊140。換句話說，以下晶片封裝體的製造方法係用於對完成後段製程的基底進行後續的封裝製程。
在某些實施例中，每一晶片區110內具有一光學部件150設置於基底100的第一表面100a上，且對應於感測區或元件區120。在某些實施例中，光學部件150可為微透鏡陣列、濾光層、其組合或其他適合的光學部件。
接著，在一蓋板170上形成一間隔層160，透過間隔層160將蓋板170接合至基底100的第一表面100a上，且間隔層160在每一晶片區110內的基底100與蓋板170之間形成一空腔180，使得光學部件150位於空腔180內，並透過蓋板170保護空腔180內的光學部件150。在其他實施例中，可先在基底100上形成間隔層160，之後將蓋板170接合至基底100上。
在某些實施例中，蓋板170可包括玻璃、石英、透明高分子或其他適合的透明材料。在某些實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)形成間隔層160。再者，間隔層160可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。或者，間隔層160可包括光阻材料，且可透過曝光及顯影製程而圖案化，以露出光學部件150。
請參照第1B圖，以蓋板170作為承載基板，對基底100的第二表面100b進行薄化製程(例如，蝕刻製程、銑削(milling)製程、磨削(grinding)製程或研磨(polishing)製程)，以減少基底100的厚度。
接著，透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在每一晶片區110的基底100內形成多個開口190，開口190自基底100的第二表面100b露出絕緣層130。
在某些實施例中，開口190對應於導電墊140而貫穿基底100，且開口190鄰近於第一表面100a的口徑小於其鄰近於第二表面100b的口徑，因此開口190具有傾斜的側壁，進而降低後續形成於開口190內的膜層的製程難度，並提高可靠度。舉例來說，由於開口190鄰近於第一表面100a的口徑小於其鄰近於第二表面100b的口徑，因此後續形成於開口190內的膜層(例如，絕緣層及重佈線層)能夠較輕易地沉積於開口190 與絕緣層130之間的轉角，以避免影響電性連接路徑或產生漏電流的問題。
在某些實施例中，可透過微影製程及蝕刻製程，在相鄰晶片區110之間的基底100內形成額外的開口(或溝槽)，此額外的開口沿著晶片區110之間的切割道延伸且貫穿基底100，使得多個晶片區110內的基底100的多個部分彼此分離。再者，此額外的開口可具有傾斜的側壁，亦即多個晶片區110內的基底100的多個部分會具有傾斜的邊緣側壁。
請參照第1C圖，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在基底100的第二表面100b上形成一絕緣層210。在某些實施例中，絕緣層210順應性地沉積於開口190的側壁及底部上。在某些實施例中，絕緣層210可包括環氧樹脂、無機材料、有機高分子材料或其他適合的絕緣材料。
接著，可透過微影製程及蝕刻製程，去除開口190底部的絕緣層210及其下方的絕緣層130，使得開口190延伸至絕緣層130內而露出對應的導電墊140。
接著，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層210上形成圖案化的重佈線層220。重佈線層220順應性地延伸至開口190的側壁及底部。重佈線層220可透過絕緣層210與基底100電性隔離，且可經由開口190直接電性接觸或間接電性連接露出的導電墊140。在某些實施例中，重佈線層220可包括鋁、銅、金、 鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料或其他適合的導電材料。
請參照第1D圖，可透過沉積製程，在基底100的第二表面100b上形成一保護層230，且填入開口190，以覆蓋重佈線層220。在某些實施例中，保護層230可包括環氧樹脂、綠漆、無機材料、有機高分子材料或其他適合的絕緣材料。
在某些實施例中，保護層230僅局部填充開口190，使得一孔洞形成於開口190內的重佈線層220與保護層230之間。在某些實施例中，孔洞與保護層230之間的界面具有拱形輪廓。由於保護層230部分填充於開口190而留下孔洞，因此後續製程中遭遇熱循環(thermal cycle)時，孔洞能夠作為保護層230與重佈線層220之間的緩衝，以降低保護層230與重佈線層220之間由於熱膨脹係數不匹配所引發不必要的應力，且防止外界溫度或壓力劇烈變化時保護層230會過度拉扯重佈線層220，進而可避免靠近導電墊結構的重佈線層220剝離甚至斷路的問題。
接著，可透過微影製程及蝕刻製程，在基底100的第二表面100b上的保護層230內形成開口240及250，以露出圖案化的重佈線層220的一部分。在某些實施例中，開口240的寬度大於開口250的寬度。在某些其他實施例中，開口240的寬度可能等於或小於開口250的寬度。
請參照第1D圖，可透過網版印刷製程或其他適合的製程，在保護層230的開口250內填入接合層270，而與露出的重佈線層220電性連接。在某些實施例中，接合層270局部填 入開口250。在某些其他實施例中，接合層270全部填滿開口250。在某些實施例中，開口250內的接合層270突出於開口250。在某些其他實施例中，開口250內的接合層270進一步延伸至保護層230上。在某些實施例中，接合層270可包括錫、鉛、銅、金、鎳、其他適合的接合材料、或前述之組合。
接著，可透過網版印刷製程或其他適合的製程，在保護層230的開口240內填入多個第一導電結構260，以與露出的重佈線層220及感測區或元件區120電性連接。第一導電結構260填滿開口240，且突出於開口240。在某些實施例中，第一導電結構260可包括錫、鉛、銅、金、鎳、其他適合的導電材料、或前述之組合。在某些實施例中，第一導電結構260的形成方法相同於接合層270的形成方法。
之後，沿著相鄰晶片區110之間的切割道(未繪示)切割保護層230、基底100、絕緣層130、間隔層160及蓋板170，以形成複數獨立的晶片封裝結構A。舉例來說，可使用切割刀具或雷射進行切割製程，其中使用雷射切割製程可以避免上下膜層發生位移。
請參照第1E圖，將一被動元件300放置於晶片封裝結構A上，且進行回焊(reflow)製程，使得被動元件300與晶片封裝結構A互相接合及電性連接。具體而言，被動元件300接合於基底100的第二表面100b上，使得被動元件300與基底100縱向地堆疊。在某些實施例中，被動元件300的尺寸小於基底100的尺寸。再者，當基底100的尺寸足夠大或被動元件300的尺寸足夠小時，可在基底100的第二表面100b上接合一個以上具有 相同或不同功能的被動元件300。
在某些實施例中，被動元件300與第一導電結構260位於基底100的同一側，且彼此橫向排列。再者，被動元件300與光學部件150及蓋板170位於基底100的相對兩側。在某些實施例中，被動元件300可被多個第一導電結構260所環繞。在某些實施例中，被動元件300可為積體/整合被動元件。在某些其他實施例中，被動元件300可為電阻、電容、電感或其他適合的被動元件。
請參照第2圖，被動元件300內具有一元件區310。元件區310內的電路結構可構成電阻、電容、電感、其他適合的被動元件、或其組合。在某些實施例中，在將被動元件300接合至晶片封裝結構A之前，多個接合結構320形成於被動元件300的上表面上，且與元件區310電性連接。在某些實施例中，接合結構320可包括銅、鋁、其他適合的導電材料、或前述之組合。
如第2圖所示，多個開口330形成於被動元件300內且自被動元件300的下表面局部露出元件區310。一絕緣層340形成於被動元件300的下表面，且順應性地延伸至開口330的側壁上，並局部露出元件區310。圖案化的重佈線層350形成於被動元件300的下表面，且順應性地延伸至開口330的側壁及底部上。一保護層360形成於被動元件300的下表面，且填入開口330，以覆蓋重佈線層350。再者，被動元件300的下表面上的保護層360內形成開口370，露出重佈線層350的一部份。在某些實施例中，開口330、絕緣層340、重佈線層350、保護層360、 開口370的配置及形成方法分別相同或類似於開口190、絕緣層210、重佈線層220、保護層230、開口240的配置及形成方法，故此處不再重複說明。
在某些實施例中，在形成開口330之前，可先對被動元件300的下表面進行薄化製程(例如，蝕刻製程、銑削製程、磨削製程或研磨製程)，以減少被動元件300的厚度。
接著，可透過網版印刷製程或其他適合的製程，在保護層360的多個開口370內填入多個第二導電結構380，以與露出的重佈線層350電性連接。第二導電結構380填滿開口370，且突出於開口370。在某些實施例中，第二導電結構380可包括錫、鉛、銅、金、鎳、其他適合的導電材料、或前述之組合。在某些實施例中，第二導電結構380的形成方法相同於第一導電結構260及/或接合層270的形成方法。
在某些實施例中，被動元件300的基底為晶圓，且透過進行晶圓級封裝製程及切割製程，以形成多個被動元件300。可以理解的是，第2圖所示之被動元件300僅作為範例說明，被動元件300的結構並不限定於此。再者，為簡化圖式，第1E圖中未繪示出第2圖中的開口330、絕緣層340、重佈線層350、保護層360、開口370。
如前述，在將被動元件300放置於晶片封裝結構A上之後，同時對第一導電結構260、接合層270、第二導電結構380進行回焊製程，使得被動元件300透過接合結構320及接合層270與晶片封裝結構A互相接合及電性連接。在某些實施例中，透過將接合結構320埋置於接合層270內，使得接合結構320 由接合層270所環繞，進而在被動元件300與基底100之間形成穩固的接合鍵結。在某些實施例中，一部分的接合層270受到接合結構320擠壓而自開口250延伸到保護層230上方。在某些其他實施例中，接合層270可能未延伸到保護層230上方。
在某些實施例中，接合結構320與第一導電結構260及/或接合層270皆位於重佈線層220上，因此接合結構320與第一導電結構260及/或接合層270位於相同層位。在某些其他實施例中，一部分的接合層270可夾設於接合結構320與重佈線層220之間，因此接合結構320與第一導電結構260及/或接合層270位於不同層位。
如第1E圖所示，接合結構320嵌入接合層270內，使得第二導電結構380的頂部(頂表面)與第一導電結構260的頂部(頂表面)大致上對齊於平面P。換句話說，第二導電結構380的頂部與第一導電結構260的頂部大致上共平面。在某些實施例中，被動元件300的厚度小於第一導電結構260的厚度。在某些實施例中，接合結構320、被動元件300及第二導電結構380的總厚度大致上相同於第一導電結構260的厚度。
在某些實施例中，透過進行回焊製程，將被動元件300及晶片封裝結構A接合於一電路板(未繪示)上，此時基底100透過第一導電結構260與電路板物理性及電性連接，且被動元件300透過第二導電結構380與電路板物理性及電性連接。由於第二導電結構380的頂部與第一導電結構260的頂部大致上共平面，因此被動元件300及晶片封裝結構A能順利地直接接合至電路板上。如此一來，一個或一個以上的被動元件能夠直接 整合於晶片封裝體內，所連接的電路板不再需要保留設置被動元件的空間，因此可以進一步縮小電子產品的尺寸。
再者，由於被動元件300直接與晶片封裝結構A連接，大幅縮短了被動元件300與晶片封裝結構A之間的電性傳輸路徑，因此可完整地傳輸功率，避免訊號變差，也有效防止雜訊的產生，進而提升電子產品的品質及可靠度。
可以理解的是，雖然第1A至1E圖的實施例為具有前照式感測裝置之晶片封裝體的製造方法，然而關於晶片的外部電性連接路徑(例如，基底內的開口、重佈線層、保護層、導電結構等)及被動元件的製作方法亦可應用於背照式感測裝置的製程中或是其他類型的晶片封裝體的製程中。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。

Claims (18)

  1. 一種晶片封裝體，包括：一基底，其中該基底內具有一感測區或元件區；一第一導電結構，其中該第一導電結構位於該基底上，且與該感測區或元件區電性連接；一被動元件，其中該被動元件縱向地堆疊於該基底上，且與該第一導電結構橫向排列；以及一第二導電結構，其中該第二導電結構與該基底位於該被動元件的相對兩側。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該第二導電結構的材料相同於該第一導電結構的材料。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該第二導電結構的頂部大致上對齊於該第一導電結構的頂部。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該第二導電結構的尺寸小於該第一導電結構的尺寸。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該被動元件透過一接合結構接合於該基底上。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中該接合結構與該第一導電結構位於相同層位。
  7. 如申請專利範圍第5項所述之晶片封裝體，其中該接合結構由一接合層所環繞，且該接合層的材料不同於該接合結構的材料。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該接合層的材料相同於該第一導電結構的材料。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該被動元件的厚度小於該第一導電結構的厚度。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該被動元件與該感測區或元件區重疊。
  11. 一種晶片封裝體的製造方法，包括：提供一基底，其中該基底內具有一感測區或元件區；在該基底上形成一第一導電結構，其中該第一導電結構與該感測區或元件區電性連接；將一被動元件縱向地堆疊於該基底上，其中該被動元件與該第一導電結構橫向排列；以及在將該被動元件縱向地堆疊於該基底上之前，在該基底上形成一接合層，其中將具有一接合結構的該被動元件縱向地堆疊於該基底上，使得該接合結構嵌入該接合層內。
  12. 如申請專利範圍第11項所述之晶片封裝體的製造方法，其中透過相同的製程形成該接合層及該第一導電結構。
  13. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括對該第一導電結構及該接合層進行回焊製程。
  14. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括：在將該被動元件縱向地堆疊於該基底上之前，在該被動元件上形成一第二導電結構，其中將具有該第二導電結構的該被動元件縱向地堆疊於該基底上。
  15. 如申請專利範圍第14項所述之晶片封裝體的製造方法，其中該第二導電結構的頂部與該第一導電結構的頂部大致上共平面。
  16. 如申請專利範圍第14項所述之晶片封裝體的製造方法，其中透過相同的製程形成該第二導電結構及第一導電結構。
  17. 如申請專利範圍第14項所述之晶片封裝體的製造方法，更包括對該第一導電結構及該第二導電結構進行回焊製程。
  18. 如申請專利範圍第11項所述之晶片封裝體的製造方法，更包括在將該被動元件縱向地堆疊於該基底上之前，對該基底進行切割製程。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9943239B2 (en) * 2016-03-07 2018-04-17 Taiwan Semiconductor Manufacturing Company Ltd. Optical sensing system and associated electronic device
CN109411487B (zh) * 2017-08-15 2020-09-08 胜丽国际股份有限公司 堆叠式感测器封装结构
US20190096866A1 (en) * 2017-09-26 2019-03-28 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
CN107863363A (zh) * 2017-11-20 2018-03-30 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
CN108831860A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
TWI788903B (zh) * 2020-08-06 2023-01-01 力成科技股份有限公司 封裝結構及其製造方法
US11990494B2 (en) 2020-08-06 2024-05-21 Powertech Technology Inc. Package structure and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214644B1 (en) * 2000-06-30 2001-04-10 Amkor Technology, Inc. Flip-chip micromachine package fabrication method
US6225692B1 (en) * 1999-06-03 2001-05-01 Cts Corporation Flip chip package for micromachined semiconductors
TW512505B (en) * 2001-11-06 2002-12-01 Jian Huei Jiuan Common type packaging method of microsensor
TWI285418B (en) * 2006-01-06 2007-08-11 Advanced Semiconductor Eng Packaging structure of camera module
TW200834938A (en) * 2007-02-08 2008-08-16 Advanced Chip Eng Tech Inc Image sensor package with die receiving opening and method of the same
TW200837902A (en) * 2007-03-15 2008-09-16 Advanced Chip Eng Tech Inc Image sensor module having build-in package cavity and the method of the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5742100A (en) * 1995-03-27 1998-04-21 Motorola, Inc. Structure having flip-chip connected substrates
JP4160083B2 (ja) * 2006-04-11 2008-10-01 シャープ株式会社 光学装置用モジュール及び光学装置用モジュールの製造方法
CN100585850C (zh) * 2007-06-27 2010-01-27 财团法人工业技术研究院 具晶粒三维堆叠结构的影像感测模块
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
CN202394956U (zh) * 2011-12-02 2012-08-22 日月光半导体（上海）股份有限公司 半导体封装构造

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225692B1 (en) * 1999-06-03 2001-05-01 Cts Corporation Flip chip package for micromachined semiconductors
US6214644B1 (en) * 2000-06-30 2001-04-10 Amkor Technology, Inc. Flip-chip micromachine package fabrication method
TW512505B (en) * 2001-11-06 2002-12-01 Jian Huei Jiuan Common type packaging method of microsensor
TWI285418B (en) * 2006-01-06 2007-08-11 Advanced Semiconductor Eng Packaging structure of camera module
TW200834938A (en) * 2007-02-08 2008-08-16 Advanced Chip Eng Tech Inc Image sensor package with die receiving opening and method of the same
TW200837902A (en) * 2007-03-15 2008-09-16 Advanced Chip Eng Tech Inc Image sensor module having build-in package cavity and the method of the same

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