TW512505B - Common type packaging method of microsensor - Google Patents
Common type packaging method of microsensor Download PDFInfo
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- TW512505B TW512505B TW090127477A TW90127477A TW512505B TW 512505 B TW512505 B TW 512505B TW 090127477 A TW090127477 A TW 090127477A TW 90127477 A TW90127477 A TW 90127477A TW 512505 B TW512505 B TW 512505B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
Description
五、發明說明(1) [發明背景] 以_ 一般而言,感測器的封裝核心技術,可依照下列層次 來纟兄明 曰 第一層(Level 0ne)晶圓層(Wa f e r i e ve j ) 主f係同種材料或異種材料的結纟,提供多層不同的 、、且口,偏向完成較須厚度或複雜的感測去 包括··陽極接合、共融合金接合、 干、带見的方法 (silicon fusion bonding) > CVD 石同虫接合V. Description of the invention (1) [Background of the invention] In general, the core technology of sensor packaging can be described in accordance with the following levels: Level 0ne Wafer layer (Wa ferie ve j) The main f is the crust of the same material or different materials, providing multiple layers of different, and mouth, biased to complete the more thick or complex sensing to include ... Anodic bonding, fused gold bonding, dry, see the method ( silicon fusion bonding) > CVD
Unt glass b〇nding) δ)Λέ/^νΐ)/ 封、混融玻璃接合 g 大約的製程如下表所示 製程 陽極接合 材料 Pyrex硼矽破璃 摻雜極多的納 製程規格需求 30 0-450 〇C,3 00- 1 000V, 〜3 0分鐘非常平坦的表面 共融合金接 合(反應性 金屬接合) 薄層金屬如金 363 t 有機接合 高分子或環氧樹 脂銀膠 低溫,缺點:非完全密 封,有老化現象(aging effects) 512505 五、發明說明(2) 石夕融接合 矽與矽 親水性(Hydrophi 1 ic), 清潔拋光的矽晶 圓,1 0 0 0 - 1 2 0 〇它,數小時 第二層(Leve 1 Two)晶片層(Ch i p 1 eve 1) 主要是感測元件與電路元件本身接腳的引出,常用的技術 為將元件置於導線架上’用打線機將元件上的鮮墊引線至 導線架上,或利用覆晶製作凸塊的技術,將凸塊製作於元 件的鲜塾上。 第三層(Level Three)基板層(Board level) 主要係感測元件與電路元件對電路基板的接合,使感測元 件與電路元件能互相溝通,另外也使電路基板能有較大的 銲墊’能接至外界的電氣設備,常用的技術為表面黏著技 術(Surface Mount Technology,SMT);另外也使用覆晶 技術作感測元件與電路元件的結合(integratiQn) 。 _ 第四層(Level Four) 感測器(系統)層 主要係提供待封體與外殼的介面,此處的待封體,係基板 層以上的元件,技術發展的重點為: & (a)引線拉出的絕緣問題,應使用何種絕緣膠、油、塗 料。 土Unt glass b〇nding) δ) Λέ / ^ νΐ) / Sealing and hybrid glass bonding g. The approximate process is shown in the table below. Process anodizing material Pyrex borosilicate glass is doped with a lot of nano-process specifications. 30 0-450 〇C, 3 00-1 000V, ~ 30 minutes Very flat surface co-fusion gold bonding (reactive metal bonding) Thin metal such as gold 363 t Organic bonding polymer or epoxy silver glue Low temperature, disadvantages: incomplete Sealed, with aging effects 512505 V. Description of the invention (2) Shi Xirong joins silicon with silicon hydrophilicity (Hydrophi 1 ic), clean and polished silicon wafer, 1 00-1 2 0 〇 it, For several hours, the second layer (Leve 1 Two) chip layer (Ch ip 1 eve 1) is mainly the pin-out of the sensing element and the circuit element itself. The commonly used technique is to place the component on a lead frame. The fresh pad on the lead is leaded to the lead frame, or the bump is made on the fresh wafer of the component by using a flip-chip manufacturing bump technology. The third level (Board level) is mainly the connection between the sensing element and the circuit element to the circuit substrate, so that the sensing element and the circuit element can communicate with each other, and also allows the circuit substrate to have larger pads. 'Electrical equipment that can be connected to the outside world, commonly used technology is Surface Mount Technology (SMT); In addition, flip-chip technology is also used as the combination of sensing elements and circuit elements (integratiQn). _ The fourth layer (Level Four) sensor (system) layer mainly provides the interface between the body to be sealed and the shell. The body to be sealed here is a component above the substrate layer. The focus of technological development is: & (a ) What kind of insulating glue, oil, and paint should be used for the insulation of the lead wire. earth
(b)待封體的定位 形外殼能穷切㈣定位膠使方形待封體與圓 Δ 山切結合且對準無誤,封閉或開放。 ί線或無線連接器的設計與製作,有線電線的選擇, 右是含電路元件在内,則一定要四條線以上,包^ 2電源線,二條訊號線;若僅為主動式感測元件,如 熱電耦,壓電材料等,則需要二條線。 外殼(housing)的設計與製作 材料的選擇有金屬、塑膠、陶瓷、玻璃或以上的複合;加 =方式也因材料不同而有(㈧塑膠:射出成型、浸"/(Η 孟屬:抽拉、銲接、壓合、切削、放電、鎖合、沖壓 c)陶竟:膠合(d)玻璃:膠合、陽極接合。 外形方面則有管子與盒子等變化;安裝方式有外加式. 與侵入式:f孔置入;減能力則考慮機械 強度、化學強度、EMC熱傳測試。 近年來,在成本考量下,塑膠外殼受到較大的重視, 也有較大的製作彈性,例如,使用雙層(或雙料)共射的射 出成形製程,將防電磁波干擾或高導電性等材料 料或核心料。 '' ^ 封裝形式可分成 半閉 單面不閉:化學感測器 全閉(b) Positioning of the to-be-sealed body The shape of the shell can be poorly cut. The positioning glue enables the square to-be-sealed body to be combined with the round Δ mountain cut without misalignment, closed or open. The design and production of wires or wireless connectors, the choice of wired wires, including circuit components on the right, must be more than four lines, including ^ 2 power lines, two signal lines; if only active sensing elements, For thermocouples, piezoelectric materials, etc., two wires are required. Housing (housing) design and selection of materials are metal, plastic, ceramic, glass or more of the above; the addition method also depends on the material (㈧Plastic: injection molding, dipping " / (Η Meng: pumping Drawing, welding, pressing, cutting, discharging, locking, stamping c) pottery: glued (d) glass: glued, anodic bonding. There are changes in the shape of the tube and box, etc .; the installation methods are external and intrusive. : F-hole insertion; the reduction of power takes into account mechanical strength, chemical strength, and EMC heat transfer test. In recent years, under the consideration of cost, plastic housing has been paid more attention, and there is greater flexibility in production, for example, using double layers ( (Or dual-material) co-injection injection molding process, which will prevent electromagnetic interference or high conductivity and other materials or core materials. ^ ^ The package can be divided into semi-closed and single-sided: chemical sensor is fully closed
512505 五、發明說明(4) 上 空 下 通 壓 力 感 測 器 上 空 下 空 加 速 度 計(acceleration sensors) 上 空 下 密 絕 對 壓 力 感測器 上 密 下 密 線 圈 封 裝 上 通 下 通 差 動 壓 力 感測器、風速計 介面 a :感 其 與 例子 氣體 離子 氣體 溫度 光學 電蟻 壓力 參考圖一,說明一般微系統在封裝時,各元件之間的 問題,a、 b、 c、 d、 e, 表示各類封裝介面。 測元件1 0 1與環境的介面1 0 2 需求為,對待測參數要透明,對其他無關的環境物理 化學參數要阻擋。 感測 感測 與溼 感剛 場感 器(gas sensors):半透氣的薄膜(semi 一 transparent membranes) 器(ionic sensors):保護層(paSsiVation layers) 度感測器(gas and humidity sensors):網格及 過濾器(grids and filters) 器(temperature sensors ):金屬短柱(metal stud) 器(optical sensors):玻璃窗(giass windows) 測器(magnetic field sensors):塑膠層 (plastic layers) 器(pressure sensors ):直接與待測媒介接觸512505 V. Description of the invention (4) Overhead and down pressure sensor Overhead and down accelerometer (acceleration sensors) Overhead and down absolute pressure sensor Top and bottom dense coil package Up and down differential pressure sensor, wind speed Interface a: Sensitivity and example gas Ion gas temperature Optical electric ant pressure Refer to Figure 1 to explain the problems between components when general microsystems are packaged, a, b, c, d, e, which represent various types of packaging interfaces . The interface between the measuring element 1 0 1 and the environment 1 0 2 requires that the parameters to be measured should be transparent, and other unrelated environmental physical and chemical parameters should be blocked. Gas sensors: semi-transparent membranes, ionic sensors: paSsiVation layers, gas and humidity sensors: net Grids and filters temperature sensors: metal studs optical sensors: giass windows magnetic field sensors: plastic layers ( pressure sensors): Direct contact with the medium under test
第8頁 512505 五、發明說明(5) 流量感測器(f 1 〇 w s e n s 〇 r s ):直接與待測媒介接觸 加速度(acceleration sensors):不與待測媒介接觸 化學感測器(chemical sensors):直接與待測媒介接觸 b :感測元件與封裝材料丨〇 5的介面或晶片置合與相連技 術(chip mounting and interconnection techniques) 可能發生的問題為 機械應力-在接合過程中產生的,如陽極接合、融合接 合、共融合金接合、黏膠接合等製程所產生的 接合力(bonding force)Page 8 512505 V. Description of the invention (5) Flow sensor (f 1 〇wsens 〇rs): direct contact with the medium to be measured acceleration (acceleration sensors): no contact with the medium to be tested chemical sensors (chemical sensors) : Direct contact with the medium to be tested b: the interface between the sensing element and the packaging material 丨 〇5 chip mounting and interconnection techniques (chip mounting and interconnection techniques) possible problems are mechanical stress-generated during the bonding process, such as Bonding force generated by processes such as anodic bonding, fusion bonding, fusion gold bonding, and adhesive bonding
熱應力-在接合程序之後發生,例如晶片、黏晶材料,與 基板有不同的溫度膨脹係數(Coefficient of Thermal Expansion, CTE) 熱效應-抵補溫度係數、漂移(〇ffset temperature coefficient, drift) 對位不準(mi sal ignment) -會讓壓力感測器或加速度感測 器量到其他無關的分量 c ·感測元件與電子電路元件丨〇 3的介面,可能發生的問題 為寄生效應與負載效應 d •電子元件與封裝材料的介面,可能發生的問題為EMC,Thermal stress-occurs after the bonding process, such as wafers, sticky crystal materials, and has a different coefficient of thermal expansion (CTE) from the substrate. Thermal effect-offset temperature coefficient, drift. Quasi (mi sal ignment)-Allows pressure sensors or acceleration sensors to measure other unrelated components c · The interface between the sensing element and the electronic circuit element 丨 〇3, possible problems are parasitic effects and load effects d • The interface between electronic components and packaging materials is EMC.
以及水氣、灰塵、腐蝕、傷害銲墊與連接線路,散熱性 e :電子元件與電氣的介面1〇4,即電氣接線(electricalAnd moisture, dust, corrosion, damage to the pads and connection lines, heat dissipation e: the interface between electronic components and electrical 104, that is, electrical wiring (electrical
Wlre) ’可能發生的問題為小轉大、EMC,與拉扯損壞 或無線傳送(wireless transmission)Wlre) ’Possible problems are small to large, EMC, pull damage, or wireless transmission
第9頁Page 9
k 一 :玎‘ 五、發明說明(6) 由以上的說明可知一種微感測器的封裝方法需要克服 上述各元件之間的介面問題 Πk a: 玎 ’5. Description of the invention (6) From the above description, we know that a micro-sensor packaging method needs to overcome the interface problems between the above components Π
'J μ'J μ
將覆晶封裝技術運用於微感測器的封裝’近年來已有 一些研究,(Mayer, F. ; Haberli, A. ; Jacobs, Η.; Ofner, G.; Paul, 0.; Baltes, H. MSingle-chip CMOS anemometer", Electron Devices Meeting, 1997. Technical Digest., International , 1997, pp. 895 -8 9 8 )利用覆晶的概念將熱式(thermal ) CMOS風速計元件 (含訊號處理電路),封裝於陶瓷基板上,其使用2微米 CMOS製程,完成電路及薄膜,接著以單光罩後製程完成Applying flip-chip packaging technology to the packaging of microsensors has been studied in recent years, (Mayer, F .; Haberli, A .; Jacobs, Η .; Ofner, G .; Paul, 0 .; Baltes, H MSingle-chip CMOS anemometer ", Electron Devices Meeting, 1997. Technical Digest., International, 1997, pp. 895 -8 9 8) The concept of flip-chip is used to integrate thermal CMOS anemometer components (including signal processing circuits). ), Packaged on a ceramic substrate, which uses a 2 micron CMOS process to complete the circuit and film, and then completes the process with a single photomask
微加工的部分。首先以PECVD沉積1微米的氮化矽(sn icon n i tr i d e, Si3N4)於上層表面,作為保護層,再於下層表 面PEC而0 · 6德「米的氮化石厂定義出空穴面積,—K0臟刻至 上層的場氧化層(f i e 1 d ox i de ),可得出所需的薄膜結 構’其上有一組加熱器(heater),2組熱電堆 (thermopiles),每一組熱電堆由2〇個bidoped(閘-多晶 石夕)/(電容-多晶矽)的熱電偶所組成。 加熱為及熱電堆的輸出入端點接至5個接觸銲墊2 〇丄, 女口 |^1 一 一 ;不。陶瓷基板以厚膜印刷製作6個大銲墊2 0 2作為 之^電線之用,5個小銲墊用於連接感測晶片上的凸塊2’〇3 片另外在中間印製一長方形框的焊墊’作為與感測晶 人 上的凸塊框(bump frame)2〇4連接密封之用,材料為 至’耐腐蝕,高度25微米 '然後用雷射切割在長方形Micromachined parts. First PECVD deposited 1 micron silicon nitride (sn icon ni tr ide (Si3N4)) on the upper surface as a protective layer, and then PEC on the lower surface, and the hole area was defined by a 0.66 "meter nitride plant,- K0 dirty etched to the upper field oxide layer (fie 1 d ox i de), we can get the required thin film structure. 'There is a set of heaters, 2 sets of thermopiles, each set of thermopiles It consists of 20 bidoped (brake-polycrystalline) / (capacitor-polycrystalline silicon) thermocouples. The heating input and output terminals of the thermopile are connected to 5 contact pads 2 0 丄, female port | ^ 1 one by one; no. The ceramic substrate is printed in thick film to make 6 large pads 2 2 for the wires, and 5 small pads for connecting the bumps on the sensor chip. A pad with a rectangular frame printed in the middle is used to connect and seal with the bump frame 204 on the sensing crystal. The material is up to 'corrosion resistant, 25 microns in height' and then cut with laser rectangle
第10頁 512505 五、發明說明(7) 切出一開口 ,作為穿孔(access ho le) 2 0 5。當感測晶片與 陶瓷基板覆晶2 0 6結合後,有腐蝕性的氣體,將因為長方 框及凸塊框的密封功能,而不能接觸晶片的電路,因此也 傷不到晶片上的電路。 在美國專利US Patent 6140144 (10/31/2000)中,才号 示一種類似於[Mayer]的做法。主要係提出一種利用包含 有穿孔或空穴的基材(substrate),在其上置一含有感測 元件的晶片,並以銲墊(pad)和底部填充劑利用毛細管現 象填充連結,再以金屬線、w i r e b 〇 n d和銲墊連接電子電 路丄必要時可以選擇性的沈積保護性的薄膜於其上,以 護這些電路,其適用的對象擴及多種感測器,如壓力’、 加速度計、化學感測器等等,但此法雜、 降低良率以及增加製造成本。 上稍嫌後雜, 在美國專利US Patent 6 1 469 1 7 ( 1 1 /ΐ4/2〇〇ίΠ + 但 子,則可由、°構(感測器)以矽晶圓為基材,而上声二墓 為蓋子,則用二ίί,f破璃披覆於石夕晶圓上。若以砂 合。石夕融接合為密璃^蓋子,則用陽極接 所需溫度較高; 卜’上下層的膨脹係數相同, 點 (400 °C〜5 0 0 t),但密為盖’用陽極接合,所需溫度較低 差異。若用披覆破璃的矽曰乂差’上、下層膨脹係數有· 此專利所提方法 ^®,可取長補短。 矽基板,在整個梦裎;^功的機制在於擔任微加工結 衣私元成後,必須伴捭料4 丁从、口構的Page 10 512505 V. Description of the invention (7) Cut out an opening as an access hole 2 0 5. After the sensing wafer is combined with the ceramic substrate flip chip 206, there is corrosive gas, which will not be able to contact the circuit of the wafer due to the sealing function of the long box and the bump box, so the circuit on the wafer will not be damaged. . In US Patent 6140144 (10/31/2000), a method similar to [Mayer] is only disclosed. The main purpose is to use a substrate containing perforations or holes, on which a wafer containing a sensing element is placed, and a pad and an underfill are used to fill the connection with a capillary phenomenon, and then a metal is used. Wires, wireb and pads connect electronic circuits. If necessary, a protective film can be selectively deposited on them to protect these circuits. The applicable object is extended to a variety of sensors, such as pressure, accelerometer, Chemical sensors, etc., but this method is complicated, reduces yield and increases manufacturing costs. The upper part is slightly miscellaneous. In the US patent 6 1 469 1 7 (1 1 / ΐ4 / 2〇〇ίΠ +), it can be made by a silicon wafer as a substrate, and The tomb of Sheng Er Er is covered with two ί, f broken glass on the Shi Xi wafer. If sand is used. Shi Xi is fused into dense glass ^ Lid, then the temperature required for anode connection is higher; Bu ' The expansion coefficient of the upper and lower layers is the same, the point (400 ° C ~ 500 t), but the dense cover is anodically bonded, and the required temperature is lower. If it is covered with broken glass, the upper and lower layers are different. Expansion coefficient: The method mentioned in this patent ^ ® can be used to make up for shortcomings. The silicon substrate is used throughout the nightmare; the mechanism of the work lies in the role of microfabrication, which must be accompanied by materials.
第11頁 肩保符被加工結構四周仍 五、發明說明(8) 保有未加工前的平坦的矽θ圓#所 1V k 的接人而苗;目,丨命西0材貝,便與蓋子作晶圓級 妾口 ,而盍子則而要蝕刻出密閉空穴3 〇 1 , 的微結構,也要蝕刻出穿孔3〇2,以#俨姑山合、、内凸出 如m ^ i牙孔3 02,以便坏接出電氣導線, 圖一所不。此方法的缺點,是僅限於加 密封的結構。 疋度冲之類兀全 在美國專利US Patent 6225 69 2 ( 3/ 1 /2〇〇 一種封裝微加工結構的方法,+ I筏娓山 _ 判 溫共燒陶甍中有一空穴:ί上==出利用多層低 ,,打貝牙孔(Vla)亚以導電線電性的連接,並在頂層用 二广回流的方式和銲塾結合,最後在底層用密 J =er、rinf銲塾與微加工的半導體設備(MEMs)結 二底部ί ΐ ΐI的目ϋ:但由於此法在製作過程中並未加 隹0 、 W,故可能會因為熱膨脹係數不同而產生埶庫 使產品壽命減少,且在低溫共燒陶竞和微力2 不U體設備接合處利用密封環接合,對於密封的程度並 一在美國專利us Patent 62 1 4644 (4/1 0/200 1 )中,揭 加工結構的方*,主要係提出-種利用銲墊 為微加工的晶片與基材間的連结,並在晶片與 二^ Ϊ充底部填充劑使得兩者間的結合更為緊密,且提 ^個=封的空穴,並解決兩者間熱膨脹係數不同的問 構。一1^方法的缺點,僅限於加速度計之類完全密封的結The shoulder protector is still around the processed structure. Fifth, the invention is explained. (8) The flat silicon θ circle # before the processing is maintained. As a wafer-level nozzle, the microstructure of the cavity must be etched to seal the microstructure of 301, and the perforation 302 should also be etched, with # 俨 姑 山 合, protruding inside as m ^ i The tooth holes 3 02, so that the electrical wires are badly connected. The disadvantage of this method is that it is limited to a sealed structure. Wu Du Chong and the like are described in US Patent 6225 69 2 (3/1 2/00) a method for packaging micro-machined structures, + I raft 娓 山 _ There is a hole in the co-firing ceramic pottery: ί The upper == out uses multiple layers. The Vla is electrically connected with conductive wires, and the top layer is combined with the welding pad with the method of reflow, and the bottom layer is welded with dense J = er and rinf.塾 and micro-machined semiconductor devices (MEMs) at the bottom of the bottom ί ΐ ΐI: But because this method does not add 隹 0, W during the production process, it may produce a library due to different thermal expansion coefficients to make the product life Reduced, and the use of sealing ring joints at the joints of low temperature co-fired ceramics and micro force 2 U-body equipment, the degree of sealing is not disclosed in US Patent 62 1 4644 (4/1 0/200 1) The structural formula * mainly proposes a kind of connection between the wafer and the substrate using microfabrication using solder pads, and filling the wafer with the underfill to make the bonding between the two more tight, and improve Holes = closed holes, and solve the problem of different thermal expansion coefficients between the two. One disadvantage of the method, only An accelerometer or the like is completely sealed junction
[發明目的] 目的之一 目的之二 目的之三 目的之四 目的之五 目的之六 目的之七 提供一種小銲墊轉成大銲墊的輸出入接腳的承 載基板(LTCC)。 提供一種因應不同感測器需求的環境介面。 提供一種具有雙面接合元件的基板。 提供一種感測單元與封裝材料的介面或晶片置 合與相連的技術,以減少機械應力,熱應力, 熱效應,與對位不準的問題。 提供一種感測元件與電子元件的介面技術,以 減)寄生效應與負載效應。靠LTCC之間相連的 =線、貝穿孔,故連線短,即使是高頻應用, ^不會有太大的寄生效應與負載效應。 Ϊ 1電子元件與封裝材料❺彳面技術,以 丁仅^免除水軋、灰塵、腐蝕、傷 害知墊與連接線路。 S「種電氣接線技術,以減少電磁干擾,並 八有抗拉扯功能或具有無線傳送的功能。 發明技術] A基本上,覆晶凸塊的功能在本發明中可^ ΠΓ •作為電性相遠之田a r A # 4知3肀可歸納如下 。 連用^ (感測元件與訊號處理電路結合) 五、發明說明(10) 2 、口構元件(structuring elements),因為凸输的 ί大小可以依需要而變,可作為電氣用途元 按,提高機械強度,如壓力計。 钱械支 與底部填充劑 3 ·选封功能,利用凸塊的形狀大小多樣化, 的配合,可達成密封的功能。 4 ·熱傳路徑,散熱或導熱。 甚至無線通 5·使智慧型感測器微小化(含訊號處理電路 訊電路)。 6 ·材料多樣化,不侷限於鉛錫合金。 7.::孔填充金屬可作為介於二層不同傳輸線阻抗的匹配 凡件,凸塊可減少考慮封裝所生的寄生效應。 工使各類微系統在封裝時有一共通型結構,本發明 =1ί與電氣介面融人於承載基板,此處的承載基板 低::/、燒陶究為主’感測元件一律以微加工完成。微系 凡件約可分成四類元件 =面=件(Single-S1ded component)包括··感測元 件、電子元件。 •又面兀件(double_sided c〇mp〇nent)包括·環境介[Objective of the Invention] One of the objectives, the second of the objectives, the third of the objectives, the fourth of objectives, the fifth of objectives, the sixth of objectives, and the seventh objective provide a load substrate (LTCC) of small input pads into large input and output pins. Provide an environmental interface to meet the needs of different sensors. A substrate having a double-sided bonding element is provided. Provided is a technology for interfacing and connecting a sensing unit and a packaging material or a chip to reduce mechanical stress, thermal stress, thermal effects, and misalignment. Provide an interface technology for sensing elements and electronic components to reduce) parasitic effects and load effects. The LTCC is connected by the = line and the perforation, so the connection is short. Even in high-frequency applications, there will not be too much parasitic effects and load effects. Ϊ 1 surface technology of electronic components and packaging materials, so as to avoid water rolling, dust, corrosion, damage to the pads and connection lines. S "Electrical wiring technology to reduce electromagnetic interference, and has anti-pull function or wireless transmission function. Inventive technology] A Basically, the function of flip-chip bumps can be used in the present invention ^ ΠΓ • as an electrical phase Tonoda ar A # 4 knows 3 肀 can be summarized as follows: Combined use ^ (sensing element combined with signal processing circuit) V. Description of the invention (10) 2, structuring elements, because the size of the convex input can be It can be changed as required, and it can be used as an electrical element to improve the mechanical strength, such as a pressure gauge. Coins and underfills 3 · Selection sealing function, the use of diversified shapes and sizes of the bumps can achieve the sealing function 4. Heat transfer path, heat dissipation or heat conduction. Even wireless communication 5. Minimize smart sensors (including signal processing circuits and signal circuits). 6 Diversified materials, not limited to lead-tin alloys. 7. :: The hole-filling metal can be used as a matching component between two layers of different transmission line impedances, and the bumps can reduce the consideration of parasitic effects generated by the package. The various types of microsystems have a common structure when packaging. The interface is integrated into the carrier substrate. Here, the carrier substrate is low :: /, the sensing element is mainly based on micro-processing. Micro-system components can be divided into about four types of components = surface = pieces (Single-S1ded component) includes: sensing elements, electronic components, and double-sided components (double_sided c〇mp〇nent) includes
J、:低:共燒陶瓷上下兩面皆可以作為接合電子元件與 ,測兀件之用,也可以做接觸銲墊。 3 ·單/雙面元件包括電氣介面 4·外殼J ,: Low: Both the upper and lower sides of the co-fired ceramics can be used for joining electronic components and testing components, and can also be used as contact pads. 3Single / double-sided components including electrical interface 4
第14頁Page 14
程便j低溫共燒陶瓷作為承載基板的原理,是因為它的製 ♦ A又天生具有容易作成雙面元件,符合環境介面與 :乳介面的要求,其特點如下: •利用沖模’可以製作出大量開放空穴40 1作為環境介 二面,以容納待測媒介進入感測元件,參考圖四。 和用冲模’可以製作出密閉空穴4 〇 2以容納主動元件, 一或作為元件隔絕的屏障,參考圖四。 •可利用貫穿填孔金屬,配合下面印刷金屬的蓋子,組 成一隔絕用空穴,有EMC的功能。Cheng Bian j Low-temperature co-fired ceramics are the principle of the carrier substrate because of its manufacture. A is inherently easy to make double-sided components, which meets the requirements of environmental interfaces and milk interfaces. Its characteristics are as follows: • Can be produced using a die. A large number of open cavities 40 1 are used as the environmental interface to accommodate the medium to be tested into the sensing element, as shown in FIG. 4. With the use of a die, a closed cavity 402 can be made to accommodate the active element, or as a barrier for the element isolation, refer to FIG. • It is possible to use a hole-filling metal in combination with a printed metal cover below to form a cavity for isolation, which has the function of EMC.
四·可利用貫穿填孔金屬,使基板下面有類似導線架,或 探針卡的小銲墊轉大銲墊的電氣介面。 五·上層基板拋光磨平,或使用表面平整的上層基板,得 出共面度與粗糙度足夠小。 ·可將被動元件如電阻5 〇 1、電感5 〇 2及電容5 〇 3,選擇性 地以印刷的方式,佈局於各層之間,參考圖五。 ^ 低溫共燒陶瓷帶(tape)系統乃是由玻璃/陶瓷介電捲 帶(tape)以整捲方式提供,配合縮收匹配金屬化漿膏 (metal izat ion paste)作為印刷與填孔之用。所用的金 屬化漿膏可採混合式,例如埋入層用銀膏,而上層或接合_ 層用金或銅,如此一來,就可以輕易與其他分離式主動或 被動兀件軟銲在一起。低溫共燒陶瓷技術較像印刷線路板 (Print Wire Board,PWB)技術,可並行處理不同層,每 層可以被衝孔、印刷、及烘乾,結果最佳的良率與成本效4. It can use penetrating metal to make the electrical interface similar to the lead frame under the substrate or the small pads of the probe card to the large pads. 5. The upper substrate is polished or flattened, or the upper substrate with a flat surface is used, and the coplanarity and roughness are sufficiently small. • Passive components such as resistors 501, inductors 502, and capacitors 503 can be selectively printed between the layers, refer to Figure 5. ^ Low-temperature co-fired ceramic tape system is provided by glass / ceramic dielectric tape in the form of a whole roll. It is matched with metal izat ion paste for printing and hole filling. . The metallization paste used can be mixed, such as silver paste for the buried layer, and gold or copper for the upper layer or the bonding layer, so that it can be easily soldered with other separate active or passive components. . Low-temperature co-fired ceramic technology is more like Print Wire Board (PWB) technology, which can process different layers in parallel, and each layer can be punched, printed, and dried, with the best yield and cost efficiency.
第15頁 512505 五、發明說明(12) 獲得,因為每一道程序與前一道無關 層在豐合之前’可單獨檢測,故良率可提升。—旦 ,完畢,即可疊合在一起,共燒於8〇〇_9〇(rc ,二= 度,完全整合的基板。 乂成阿岔 用於低溫共燒陶瓷封裝的材料,其介電常數約略 〜之間’延允許較寬的微波傳輸線,也因此比起Si、 =As ’或是Aiumina基板上的電路有較低的導體損 此之外,低溫共燒陶究也有低的1〇ss tangent,約〇 = :10GHz ’因而有較低的介電衰減。低溫共燒 .通 吊疋多層0.1-0.15mm厚的陶甍所組成, 才裝通 二輸線及部分被動元件於其中。各層元件的 在未燒結爾,用雷射或是機械式鑽孔,作為貫穿孔 因此微小化密集封裝,所雲的R F杨仏 ’ 線,皆可完成 而的傳輸線、偏壓線及控制 圖六為發明所提出的一種較佳的封裝 共燒陶究所構成,基板上方可藉由覆二基裝板 測元件(晶片)1G1,與電路元件(晶片)m,以覆 二f免701及銲墊702與基板結合,所需連接線路,可印刷 」土板上層或基板中間各層,以貫穿孔連接,若空間容 =1可,電氣介面104[(如連接器(可含有USB功能^〇3、 F k Λ扠組604、光通訊模組6〇5,例如紅外線通訊 (Α)—者擇一)置承載基板之上層601,若空間有限, ::::氣介面,置於基板的底層6〇2。承載基板可藉由 k擇性衝孔層、多孔性材料層、保護性材料披覆、透明性Page 15 512505 V. Description of the invention (12) Obtained, because each program has nothing to do with the previous one, it can be tested separately before the convergence, so the yield can be improved. -Once finished, they can be stacked together and co-fired at 800-90 ° (RC, 2 = degree, fully integrated substrate). The material used for low-temperature co-fired ceramic packaging is Acha, a dielectric material. The constant is approximately ~ the extension between allows a wider microwave transmission line, so it has lower conductor loss than Si, = As or the circuit on the Aiumina substrate, and the low-temperature co-firing ceramics has a low 1 〇 ss tangent, about 0 =: 10GHz ', so it has low dielectric attenuation. Low temperature co-firing. It is composed of multi-layer 0.1-0.15mm thick ceramics, and only the second transmission line and some passive components are installed in it. The layers of components are unsintered, and laser or mechanical drilling is used as through-holes. Therefore, compact and dense packaging can be achieved. All transmission lines, bias lines, and control lines can be completed. It is a better package co-fired ceramics proposed by the invention. The top of the substrate can be covered with a two-component mounting board to measure the component (chip) 1G1 and the circuit component (chip) m to cover two f-free 701 and solder. The pad 702 is combined with the substrate, and the required connection lines can be printed. The middle layers are connected by through holes. If the space capacity = 1, the electrical interface 104 [(such as a connector (which can include USB function ^ 03, Fk Λ fork group 604, optical communication module 605, such as infrared communication) (A) —Either one) Place the upper layer 601 of the carrier substrate. If space is limited, :::: air interface is placed on the bottom layer 60 of the substrate. The carrier substrate can be made of a selective punching layer and a porous material. Layer, protective material coating, transparency
第16頁 D125〇5 而 晶 的 的 件 蓋 承 光 路 另 發明說明(13) 料披覆等,達成環境介面的需<。 圖七為圖六的另一種實施例, ,電路元件與感測元件,都3 ?某些CM0S的感測器 — 都疋在同一塊晶片上,則此 再將電氣介面置於基板 片也可利用此承載基板來封| 底層。 圖八為圖六的另一種實施例 底層。 圖九為圖六的另一種實施例 2. 3. 係將電路元件置於基板 皆置入承載基板的空穴中,再係將電路元件、感測元 之。 冉Μ陶瓷板,由覆晶方式封 圖十為圖六的又另一種實祐 乂 載基板的最上層,此種方式特ώ係將各種兀件皆置於 學感測器。 飞特別適用於紅外線熱像儀等 圖十一為圖六的另一種實尬 元件由原本置於基板的空穴中,2將感測兀件,與電 圖七至圖十亦可以此方式實施。置於基板的上方; 圖十二為本發明低溫共繞陶 圖十三為低溫共燒陶兗的姓1的=^机程圖。 ^ ^、、、°楫不意圖。 芩照圖十二及圖十三,其詳 將低溫共燒陶莞材料「空白破二驟如下所述: 10、20、30和40的外形。 尤▼」切出基材 分二在基材10、20、3〇上打出貫穿孔5 ” 7、1 7。 2 5及空义 將貫穿孔5、15、25填充導電材料,例如 、 ^ 或錫的薄Page 16 D125〇5 The crystal cover covers the light path. Another invention description (13) material coating, etc., to meet the needs of the environmental interface. FIG. 7 is another embodiment of FIG. 6. The circuit element and the sensing element are both 3? Some CM0S sensors are all on the same chip, and then the electrical interface is placed on the substrate. The carrier substrate can also be used to seal the bottom layer. Fig. 8 is a bottom layer of another embodiment of Fig. 6. Fig. 9 is another embodiment of Fig. 6. 2. The circuit elements are placed on the substrate. Both are placed in the cavity of the carrier substrate, and then the circuit elements and the sensing elements are placed. Ran M ceramic plate is sealed by the flip-chip method. Figure 10 is the top layer of another real-life substrate on Figure 6. This method involves placing various components on the sensor. Fly is particularly suitable for infrared cameras. Figure 11 is another embarrassing component of Figure 6. It was originally placed in the cavity of the substrate. 2 The sensing element and the electrical diagram 7 to Figure 10 can also be implemented in this way. . It is placed on the top of the substrate; Figure 12 is a low temperature co-firing ceramic pottery of the present invention; ^ ^ ,,, ° 楫 is not intended.芩 According to Figure 12 and Figure 13, the details of the low-temperature co-firing ceramic material "blank breaking two steps are as follows: the shape of 10, 20, 30, and 40. You ▼" cut out the substrate divided into two on the substrate 10, 20, 30 through holes 5 "7, 1 7. 25 and the empty meaning will fill the through holes 5, 15, 25 filled with conductive materials, such as,
五 、發明說明(14)V. Description of the invention (14)
膜膏。 4·將導電線12、22、32印刷在基材上 墊及被動元件。 並選擇性的印刷銲 5·檢查基材10、20、30和40的缺陷。6 ·將基材1 〇、2 0、3 0和4 0彼此堆疊在 結形成陶瓷組合5 0。 7 ·將電路元件及感測元件或電氣介面 7、1 7 中。 一起’並加壓加熱燒 置於事先挖好的空穴 8.=銲使覆晶凸塊一 m叩銲塾上。 完成上述步驟後,則視聯接器型 二當以鍚球為外接"。時,則製二 法: •用鍍或印刷的方式將鍚膏放上銲墊。 I 0 ·將锡球置於銲墊上。 II ·鍚球經由回流而結合。 (2 )連接器和感測元一 則製造流程為丨, q寺冋封裝在低溫共燒陶瓷中 12. 注入底部填充劑。 13. 清潔整個封裝體。 14·整個封裝髀 15.整個封裝體電性的測試。 衣體做最後外觀的檢測。Film paste. 4. Print conductive wires 12, 22, and 32 on the substrate and passive components. And selective print welding 5. Check the substrates 10, 20, 30 and 40 for defects. 6 • The substrates 10, 20, 30, and 40 are stacked on each other to form a ceramic combination 50. 7 · Place circuit elements and sensing elements or electrical interfaces 7, 1 7 in. Put it together and heat it under pressure and place it in the hole that was dug in advance. After the above steps are completed, the connector type is regarded as the external connection of the ball. When it is, then the second method: • Place the paste on the pad by plating or printing. I 0 · Place the solder ball on the solder pad. II. The ball is bonded via reflux. (2) The manufacturing process of the connector and the sensing element is as follows: q Temple is packaged in a low-temperature co-fired ceramic 12. Inject an underfill. 13. Clean the entire package. 14. Entire package 髀 15. Electrical test of the entire package. The body is tested for final appearance.
實施例一 I力感測器Example 1 I force sensor
第18頁 5l25〇5 五、發明說明(15) m〇1曰及電路元件103置入基板上事先挖好的空穴中, 塊701與低溫共燒陶莞基板上的印刷銲墊作 二,連、结’並使用底部填充劑801將覆晶凸塊填充,如此 —來不但可以避免外部惡劣環境對 結的可靠产…且此方法亦以=封; 程:ι :益ΐ低製程的繁雜性;另外對於電路元件中由於製 則二其、:r、f較大的電阻、電容及電感等被動元件時, m t板中選擇性的印上被動元件802作為電路連結或 考: 二當量測相對壓力時’通氣孔803則為為參 或疋不舄要通氣孔,並以直空封奘曰 ^量測時,當外界流體的壓力、由;用與以 ’即訊號處理IC,得到流體壓力轉換成 於電 連接器,達到小銲塾轉大銲墊的效果連…或使用 本實施例封裝時,須考慮流體是否具有侵蝕性, 2的加以披覆-層保護膜’或者當流體壓力量測範^ :日二需要使用有限元素法ANSYS去分析,覆晶凸塊的圍大較 數目、與底部填充劑的組合,可姦 少 度,以抗衡流體壓力作用於薄膜上的總力。夕、機械強 :十五則為另一壓力感測态貫施例 與圖十四相同,不同處在於通孔8〇3改由基S板上封方衣進的入方法 圖十六又為另一實施例的剖面圖,封裝的方法 四相似,鐵在於將原本的電路元件及被動元件皆】:Page 18 5125 05. Description of the invention (15) m01 means that the circuit element 103 is placed in a hole dug in advance on the substrate, and the block 701 and the low-temperature co-fired printed pad on the substrate are used as two. Connect and knot 'and use the underfill 801 to fill the flip-chip bumps, so-not only can avoid the reliable production of knots in the harsh external environment ... and this method is also sealed; Process: ι: The complexity of the low-cost process In addition, for passive components such as larger resistances, capacitors, and inductors due to rule two in the circuit components, the passive component 802 is selectively printed on the mt board as a circuit connection or test: two equivalents When measuring the relative pressure, the vent hole 803 is a reference hole or a vent hole, and it is sealed with a straight air. When measuring, when the pressure of the external fluid, the reason is; The fluid pressure is converted to the electrical connector to achieve the effect of small solder pads to large pads ... or when using the package of this embodiment, it must be considered whether the fluid is corrosive, 2 should be coated-protective film or when the fluid Pressure measurement range ^: Nichiji needs to use the finite element method ANSYS To analyze, the large number of flip-chip bumps and the combination with the underfill can be reduced to counteract the total force of the fluid pressure on the film. Evening and mechanical strength: Fifteen is another example of pressure sensing. The same embodiment as in Figure 14, except that the through hole 803 is changed from the sealing method of the square S board. Figure 16 is The cross-sectional view of another embodiment is similar to the four packaging methods. The iron lies in the original circuit components and passive components.]:
512505 五、發明說明(16) 感測元件之下,如圖中1 〇 3及8 0 2所示,此封壯 利用低溫共燒陶瓷的特性,使感測器體承^ ^法可充分 4貝灵為縮小。 實施例二 加速度感測器 圖十七為加速度感測器實施例的剖面圖,512505 V. Description of the invention (16) Below the sensing element, as shown in Figures 103 and 802, this seal uses the characteristics of low-temperature co-fired ceramic to make the sensor body support ^ ^ method can be fully 4 Belling is shrinking. Embodiment 2 Acceleration Sensor FIG. 17 is a cross-sectional view of an embodiment of an acceleration sensor.
Analog Devices公司所生產的單石CM〇s加^,广本上與 不過Ana log Devices公司的封裝方式,H验度计相仿,只 於T0-8的導線架上,再打線連接晶片的:墊:=晶片置 護殼再以真空方式封蓋。而本實施例所提的線架,保 ΪΪ 2 2共ΐ結構9〇1的感測元件101與低、;共二圖究 直接後日日、.、口 & ,其它結構則和壓力感測器相同,二= 處為封裝時需採用真空封裝’使得共振結 直 同 作動,以降低感測誤差;另外,低、、w Α ”工902中 器(connector)預先成為一尸準/夏陶竞可以和連接 只亢成马糕準件,再將CMOS晶片,盥低 n 从曰m拉人、 A低,皿共燒陶竞上層與CMOS晶 曰曰_ 口 ,注入底部填充劑,然後將連接器--與 低溫共燒陶瓷下層的大型銲墊接合,最後整體切割。〃 、圖十八為另一實施例的剖面圖,封裝的方法與圖十六 相似不同處在於將原本的電路元件及被動元件皆置於感 測元件之下,如圖中1〇3及8〇2所示。 實施例三濕度、溫度、氣流感測器The monolithic CMOs produced by Analog Devices Co., Ltd. are widely used in packaging methods similar to Ana log Devices, but the H tester is similar, only on the lead frame of T0-8, and then connected to the chip: pad : = The chip is placed in a protective cover and then vacuum-sealed. The wire frame provided in this embodiment has a sensing element 101 and a low-temperature structure, which are 22 in common and have a structure of 901. A total of two maps are directly related to the future, and the other structures are pressure sensing. The same device is used. The vacuum packaging is required when the two parts are packaged, so that the resonant junctions act together to reduce the sensing error. In addition, the low, and w Α ”connector 902 connector becomes a cadaver / Xia Tao in advance. You can connect the connection to the standard cake, and then set the CMOS chip, lower n from m to A, and lower the pot to the upper layer and the CMOS crystal. Inject the underfill, and then Connector--It is joined with the large solder pads on the lower layer of the low-temperature co-fired ceramic, and finally cut off as a whole. Figure 18 is a cross-sectional view of another embodiment. The packaging method is similar to Figure 16 except that the original circuit components Both the passive element and the passive element are placed under the sensing element, as shown in Figs. 103 and 80. Example 3 Humidity, temperature, gas flu detector
第20頁 、發明說明(17) 、圖十九為濕度、溫度與氣流感測器的實施例,係將三 種感’則元件做在同一片晶片上,再置於含有通道入口 1 1 1 ^通,出口 1 1 2的陶瓷基板上;其可用於空調系統,汽 車’豕庭’與醫院的回饋控制。Page 20, Description of the Invention (17), and Figure 19 are examples of the humidity, temperature, and gas flu detectors. The three sensing elements are made on the same chip, and then placed on the channel containing the inlet 1 1 1 ^ It can be used for the feedback control of air-conditioning system, automobile '豕 庭' and hospital.
f度感測器主要由壓阻擴散至矽晶圓,薄膜由微加工技術 兀成’吸濕性層可由p〇丨y丨m丨de披覆達成,每個壓電阻都 放置於南敏感區,當環境溼度增加時,p〇丨y丨m丨de會膨 脹’進而引起壓阻的變化,並由電路得出相對溼度。溫度 ^,器’是利用擴散式電阻於矽晶圓上來達成。氣流感測 1疋在CM〇S所製的介電薄膜上,由沉積的多晶矽電阻加熱 〔類似hot wire) ’並於電阻兩旁設置各一個therm〇piies 用來檢出氣流V造成薄膜上的溫差dT 。 貫施例四 氣體感測器The f-degree sensor is mainly diffused from the piezoresistance to the silicon wafer. The thin film is formed by micro-processing technology. The hygroscopic layer can be achieved by coating with p〇 丨 y 丨 m 丨 de. Each piezoresistor is placed in the south sensitive area. When the ambient humidity increases, p0 丨 y 丨 m 丨 de will expand and cause changes in piezoresistance, and the relative humidity will be obtained from the circuit. The temperature is achieved using a diffused resistor on a silicon wafer. Gas flu test 1 on a dielectric film made by CM0S, heated by deposited polycrystalline silicon resistance (similar to hot wire) 'and one thermo piies on each side of the resistor to detect the temperature difference on the film caused by the airflow V dT.实施 例 四 Gas sensor
圖二十為一種微型氧氣感測器,利用含有通氣孔1 2 1 的低溫共燒陶瓷承載基板,做為與待測氣體的環境介面, 且可將電氣介面與電路元件置於承載基板内,電極兩側之 氧氣濃度差異來產生電壓,幻農度和電壓成比例的關係來 預測待測氣體濃度,其應用範圍,包括環保產業,如室 ,、大氣等空氣品質監測,醫療產業,如育嬰室、呼吸氣 等氧氣監控。測量範圍:〇〜25% 02 ,準確度:〇· 5% 。 另外一氧化碳微感測器,其封裝方式也1目仿。 另一種實施例,封裝的方法與圖十六相仿,係將原本Figure 20 shows a miniature oxygen sensor, which uses a low-temperature co-fired ceramic carrier substrate with vent holes 1 2 1 as the environmental interface with the gas to be measured, and the electrical interface and circuit components can be placed in the carrier substrate. The difference in oxygen concentration between the two sides of the electrode generates voltage, and the proportional relationship between voltage and voltage is used to predict the concentration of the gas to be measured. Its application range includes environmental protection industries such as room, air, and other air quality monitoring, and medical industries such as education Baby room, breathing gas and other oxygen monitoring. Measuring range: 0 ~ 25% 02, accuracy: 0.5%. In addition, the packaging method of carbon monoxide micro-sensors is also similar. In another embodiment, the packaging method is similar to that in FIG.
第21頁 512505 五、發明說明(18) 的電路元件及被動元件皆置於感測元件之下。 實施例五 音波感測器 圖二Η 為一種由polyimide所構成的condenser麥 克風’製作於矽基板上(内含〇n-chip CMOS放大器)(Page 21 512505 5. The circuit components and passive components of (18) are placed under the sensing components. Example 5 Sonic Sensor Figure 2Η is a condenser microphone made of polyimide on a silicon substrate (including an on-chip CMOS amplifier) (
Pedersen, M·, et.al·, "A Polymer CondenserPedersen, M., et.al., " A Polymer Condenser
Microphone on Silicon with on-chip CMOS amplifier, ▼▼ Transducers ’97,IEEE,Chicago,june 16 — 19, 1 997,pp· 445-446·),薄膜底部有下電極,而多孔 polyimide backplate的底層為上電極,當薄膜受聲壓變 形時,condenser電容值會變化,再經〇n_chip放大器而取 1應聲音大小的電壓值;封裝日夺’只要將放大器的輸出 型式和承載基板的鮮墊覆晶結*,並在承 ίί ifT广。lyimid^,開-通孔⑶即可。電氣 接線,由基板厚膜印刷的銲墊接出即可。 ,、 板,可使用厚膜技術的陶瓷基板。 b處的承載基 另一實施例,封裝的方法與圖 夕 電路元件及被動元件皆置於感測元件^下。’係將原本的 實施例六 無線感測器 無線感測器係一 功能接頭的感測器, .^ 兴馬有線傳送或I, 主要包括一個含右汚、次無線傳送 有感測元件及電路元Microphone on Silicon with on-chip CMOS amplifier, ▼▼ Transducers '97, IEEE, Chicago, june 16 — 19, 1 997, pp · 445-446 ·), the bottom of the film has a lower electrode, and the bottom of the porous polyimide backplate is up The electrode, when the film is deformed by the sound pressure, the condenser capacitance value will change, and then take the voltage value of 1 corresponding to the sound value through the On_chip amplifier; the package is only required to cover the output type of the amplifier and the fresh pad of the carrier substrate. *, And Cheng Cheng if if Guang. lyimid ^, just open-through hole (3). The electrical wiring can be connected by solder pads printed on the thick film of the substrate. ,, Board, ceramic substrate with thick film technology can be used. Carrier base at b. In another embodiment, the packaging method and diagram. Circuit components and passive components are placed under the sensing element ^. 'The original embodiment 6 wireless sensor wireless sensor is a sensor with a functional connector,. ^ Xingma wired transmission or I, mainly including a right-stained, secondary wireless transmission with sensing elements and circuits yuan
第22頁 五 、發明說明(19) 件的感〉、目||哭 池,:二阳,一個含有可被動無線接收電能的單元或電 每於彳I恶^傳送量測訊號單元的模組,如圖二十二,為本 貝也例=監芽通訊模組的整體方塊圖。 一封衣日守’係將藍芽通訊模組連同感測單元及電路元件 ΡΙ丨4 :衣於承載基板上,再注入底部填充劑密封之,天線 、J可置於$板最上層,或是直接内埋於基板中。 另一實施方法,是使電路元件,包括ADC與USB的處理 工犯及提供USB規格的連接器,直接將具USB功能的藍芽模 組,與之相連,即成具藍芽通訊功能的無線感測器。 其他如光學感測器的封裝,需要透明的環境介面,如 玻璃專’也很谷易;(參考M· r· Gongora-Rubio,et. al· Overview of l〇w temperature co-fired ceramics tape technology f〇r meso-system technology",Page 22 V. Description of the invention (19) Sense of the item>, Head || Crying Pond: Eryang, a module containing a unit that can passively receive electrical energy or a unit that transmits measurement signals As shown in Figure 22, this example is the overall block diagram of the monitoring bud communication module. A piece of clothing Rishou 'is a Bluetooth communication module with a sensing unit and circuit components PI4: clothing on the carrier substrate, and then injected with an underfill agent to seal it. The antenna and J can be placed on the top layer of the board, or It is directly embedded in the substrate. Another implementation method is to make the circuit components, including the ADC and USB processing workers and connectors that provide USB specifications, directly connect the Bluetooth module with USB function to form a wireless with Bluetooth communication function. Sensor. Others, such as the packaging of optical sensors, require a transparent environmental interface, such as glass. It is also easy to use; (Refer to M · r · Gongora-Rubio, et. Al · Overview of l0w temperature co-fired ceramics tape technology f〇r meso-system technology ",
Sensors and Actuators A 89 ( 20 0 1 ) 222-24 1 )事實 上’低溫共燒陶瓷是可以和其他材料來結合的,如玻璃、 陶曼、金屬、石夕,可以採用共燒或後燒(P〇St_fired), 此技術與厚膜及某些薄膜技術是完全相容的。玻璃可用 共燒或塗佈玻璃粉(g 1 a s s f r i t s )以較低溫後燒來與低溫 共燒陶竟結合,陶竟則可用共燒粉(co-firing frits)、 釉、環氧樹脂、或硬銲技術來與低溫共燒陶瓷結合;矽可 _ 塗佈金屬性的黏晶貧(metallic die-attaching pastes) 加以共燒或後燒結合低溫共燒陶瓷。Sensors and Actuators A 89 (20 0 1) 222-24 1) In fact, 'low temperature co-fired ceramics can be combined with other materials, such as glass, talman, metal, and stone, and co-fired or post-fired ( PoSt_fired), this technology is fully compatible with thick film and some thin film technologies. Glass can be co-fired or coated with glass powder (g 1 assfrits) and then fired at a lower temperature to combine with low-temperature co-fired ceramics. Ceramics can be co-firing frits, glazes, epoxy resins, or hard Welding technology to combine with low-temperature co-fired ceramics; silicon can be coated with metallic die-attaching pastes and co-fired or post-fired with low-temperature co-fired ceramics.
第23頁 512505 圖式簡單說明 第24頁 512505 式 圖 夠 能 效 功 及 徵 特 的 目 之 明 發 本 對 員 委 查 審 貴 使 為 於 明 說 細 詳 示 圖 列 下 合 配 茲 識 認 與 解 暸 的 步一 進 更·· 有後 示 題 問 面 介 的 間 之 件 元 各 時 裝 封 在 統 系 微 般。 一 圖 為意 圖 - 第 圖 意 〇示。 圖的圖 意法意 示方示 構構的 結結穴 計工空 速加出 風微作 OS裝製 CM封^ 式種陶 熱一燒 丘( 知知溫 習習低 為為為 圖圖圖 二三四 圖 意 示 。法 圖方 意裝 示封 件的 元佳 fc較 Ja一 被種 有一 刷的 印出 内提 板所 基明 載發 承本 為為 圖圖 五六 圖圖圖 意意意 示示示 JJ, TUJ, rnj. 施施施 實實實 二&一一 5AB一一一 一 一 另另另 /ον /^v 勺 AR 圖圖圖 六六六 第第第 為為為 圖圖圖 七八九 第第第 第第第第第第第第第第 另 的 圖 圖 程 。流 。圖造 圖意製 意示的 示例竞 例施陶 施實燒 實種共 種一溫 一另低 勺 ΛΟΗ 圖明 六發 六第本 第為為 為圖圖 圖一二 圖 意 。示 圖例 意施 示實 構器 結測 的感 瓷力 陶壓 燒的 共明 溫發 低本 為為 圖圖 三四 圖 〇 意圖 。 示意圖 的示意 例的示 施例的 實施例 器實施 測器實 感測器 力感測 壓力感 一 壓度 另一速 的另加 勺 勺 /3. 白 白 明明明 發發發 本本本 為為為 圖圖圖 五六七 。示 圖例 意施 示實 Av AMV 例器 施測 實感 一流 另氣 器與 測度 感溫 度、 速度 加濕 勺勺 A3. KpTT 明明 發發 本本。 為為圖 圖圖意 八九 第第第 圖 。圖 意圖塊 示意方 例示體 施例整 實施的 器實組 測器模 感測訊 氣感通 氧波芽 型音藍 微的的 的明例 明發施 發本實 本為為 為圖圖 圖一二 第頁 512505 圖式 5貫穿孔 8 銲墊 12 導電線 17 空穴 2 2 導電線 3 0空白玻璃陶瓷帶 4 0 空白玻璃陶瓷帶 1 0 0 承載基板 1 0 2 環境介面 1 0 4 電器介面 2 0 1 接觸焊墊 2 0 3 凸塊 2 0 5穿孔 2 0 7感測晶片 301 密閉空穴 4 0 1 開放空穴 501 電阻 5 03 電容 6 0 1 承載基板之上層 6 0 3連接器 6 0 5 光通訊模組 7 0 1覆晶凸塊 8 0 1底部填充劑 8 0 3 通孔 8 0 5鍚球 9 0 1 共振結構 111 通道入口 1 2 1 通孔 1 3 1 通孔 空穴 空白玻璃陶瓷帶 貫穿孔 空白玻璃陶瓷帶 貫穿孔 導電線 陶瓷組合 感測元件 電子電路元件The 512505 diagram on page 23 is a simple explanation. The 512505 diagram on page 24 is sufficient for energy efficiency and special purpose. The inspection and review of the commissioner for the detailed description of the map are hereby identified and explained. Step by step more ... There is a post-question question face to face, each piece of fashion is sealed in the system. One picture is intentional-the first diagram means zero. The diagrammatic method of the figure shows the structure of the knot-hole counting machine, the airspeed plus the wind speed, and the micro-OS installation of the CM seal. The type of pottery and a burning mound Illustrations. The original seals of Yuanjia fc, which are intended to display seals, are planted with a brush and printed on the inner tray. The original bearing is as shown in Figures 5-6. JJ, TUJ, rnj. Shi Shi Shi Shi Shi II & one one 5AB one one one one another another / ον / ^ v spoon AR figure figure six hundred sixty-sixth is the figure for the figure figure seventy-eight Ninth, the first, the second, the first, the second, the second, and the other diagrams. Flow. The examples of the maps are intentionally created. The sixth and sixth editions of Mingliufaliu are as shown in Figures 1 and 2. The illustrations are intended to show the temperature of the ceramic porcelain pottery firing and the low temperature of the ceramics are as shown in Figures 3 and 4. The schematic diagram shows the example of the embodiment of the embodiment, the device is implemented, the sensor is a sensor, the force is sensed, the pressure is sensed, and the pressure is increased at another speed. Scoop / 3. Bai Baimingmingfafafa The book is for the purpose of illustrations Figures 567. The illustrations are intended to show the actual Av AMV sampler, which is used to measure the real-world sensor, and to measure the temperature and speed of the spoon. A3. KpTT issued a copy of the book. It is a diagram of the figure. Figure 8 shows the diagram. The figure is a block diagram to illustrate the example of the device. Lanwei's example of the hair is really for the purpose of illustration. Figure 1-2505 Page 512505 Schematic 5 through hole 8 pad 12 conductive wire 17 cavity 2 2 conductive wire 3 0 blank glass ceramic tape 4 0 Blank glass ceramic tape 1 0 0 Carrier substrate 1 0 2 Environmental interface 1 0 4 Electrical interface 2 0 1 Contact pad 2 0 3 Bump 2 0 5 Perforation 2 0 7 Sensor chip 301 Closed cavity 4 0 1 Open air Hole 501 Resistor 5 03 Capacitor 6 0 1 Upper layer of the carrier substrate 6 0 3 Connector 6 0 5 Optical communication module 7 0 1 Flip bump 8 0 1 Underfill 8 0 3 Through hole 8 0 5 Ball 9 0 1 Resonant structure 111 Channel entrance 1 2 1 Through hole 1 3 1 Through hole cavity blank glass ceramic tape through hole White glass-ceramics with the through-hole conductive ceramic compositions sensing element line electronic circuit elements
封裝材料 H 連接電線用銲墊 凸塊框 覆晶 穿孔 密閉空穴 電感 承載基板之底層 RF通訊模組 · 銲墊 被動元件 穿孔 真空 通道出口 第頁Packaging materials H Solder pads for connecting wires Bump frame Flip-holes Perforations Sealed holes Inductors Bottom layer of the carrier substrate RF communication module · Solder pads Passive components Perforation Vacuum Channel exit Page
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8104356B2 (en) | 2008-06-19 | 2012-01-31 | Unimicron Technology Corp. | Pressure sensing device package and manufacturing method thereof |
TWI509273B (en) * | 2014-07-09 | 2015-11-21 | Voltafield Technology Corp | Testing assembly for testing magnetic sensor and method for testing magnetic sensor |
TWI642149B (en) * | 2015-10-21 | 2018-11-21 | 精材科技股份有限公司 | Chip package and method for forming the same |
CN113155348A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Piezoresistive pressure sensor signal processing module and integration method thereof |
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2001
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8104356B2 (en) | 2008-06-19 | 2012-01-31 | Unimicron Technology Corp. | Pressure sensing device package and manufacturing method thereof |
TWI509273B (en) * | 2014-07-09 | 2015-11-21 | Voltafield Technology Corp | Testing assembly for testing magnetic sensor and method for testing magnetic sensor |
TWI642149B (en) * | 2015-10-21 | 2018-11-21 | 精材科技股份有限公司 | Chip package and method for forming the same |
CN113155348A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Piezoresistive pressure sensor signal processing module and integration method thereof |
CN113155348B (en) * | 2021-02-26 | 2023-09-12 | 西安微电子技术研究所 | Piezoresistive pressure sensor signal processing module and integration method thereof |
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