CN106611715A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

Info

Publication number
CN106611715A
CN106611715A CN201610905650.XA CN201610905650A CN106611715A CN 106611715 A CN106611715 A CN 106611715A CN 201610905650 A CN201610905650 A CN 201610905650A CN 106611715 A CN106611715 A CN 106611715A
Authority
CN
China
Prior art keywords
substrate
conductive structure
wafer encapsulation
conductive
passive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201610905650.XA
Other languages
English (en)
Inventor
何彦仕
刘沧宇
李柏汉
廖季昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN106611715A publication Critical patent/CN106611715A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05616—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08265—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1207—Resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括：一基底，基底内具有一感测区或元件区；一第一导电结构，位于基底上，且与感测区或元件区电性连接；以及一无源元件，纵向地堆迭于基底上，且与第一导电结构横向排列。本发明可进一步降低电子产品的尺寸，而且可避免功率及/或信号的衰减，也有效防止噪声的产生，使得电子产品的品质及可靠度提升。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种具有无源元件的晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
一般而言，晶片封装体与其他电子元件(例如，无源元件)各自独立地设置于电路板上，且间接地彼此电性连接。然而如此一来，电路板的尺寸受到限制，进而导致所形成的电子产品的尺寸难以进一步缩小。再者，由于晶片封装体与其他电子元件之间的电性传输路径长，造成电子产品的功率(power)及/或信号(signal)的衰减程度高，也容易产生噪声(noise)，因此降低了电子产品的品质。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明实施例提供一种晶片封装体，包括：一基底，基底内具有一感测区或元件区；一第一导电结构，位于基底上，且与感测区或元件区电性连接；以及一无源元件，纵向地堆迭于基底上，且与第一导电结构横向排列。
本发明实施例提供一种晶片封装体的制造方法，包括：提供一基底，基底内具有一感测区或元件区；在基底上形成一第一导电结构，第一导电结构与感测区或元件区电性连接；以及，将一无源元件纵向地堆迭于基底上。无源元件与第一导电结构横向排列。
本发明可进一步降低电子产品的尺寸，而且可避免功率及/或信号的衰减，也有效防止噪声的产生，使得电子产品的品质及可靠度提升。
附图说明
图1A至1E是绘示出根据本发明某些实施例的晶片封装体的制造方法的剖面示意图。
图2是绘示出根据本发明某些实施例的无源元件的剖面示意图。
其中，附图中符号的简单说明如下：
100：基底；100a：第一表面；100b：第二表面；110：晶片区；120：感测区或元件区；130：绝缘层；140：导电垫；150：光学部件；160：间隔层；170：盖板；180：空腔；190：开口；210：绝缘层；220：重布线层；230：保护层；240：开口；250：开口；260：第一导电结构；270：接合层；300：无源元件；310：元件区；320：接合结构；330：开口；340：绝缘层；350：重布线层；360：保护层；370：开口；380：第二导电结构；A：晶片封装结构；P：平面。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明某些实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System，MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emittingdiodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆迭(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体或系统级封装(System in Package，SIP)的晶片封装体。
请参照图1E及图2，图1E绘示出根据本发明某些实施例的晶片封装体的剖面示意图，且图2是绘示出根据本发明某些实施例的无源元件的剖面示意图。晶片封装体包括具有一基底100的晶片封装结构A。基底100具有一第一表面100a及与其相对的一第二表面100b。在某些实施例中，基底100可为一硅基底或其他半导体基底。
在某些实施例中，基底100内具有一感测区或元件区120。感测区或元件区120可邻近于第一表面100a，且感测区或元件区120内可包括一感测元件及/或一有源元件(例如，晶体管)。在某些实施例中，感测区或元件区120内包括感光元件或其他适合的光电元件。在其他实施例中，感测区或元件区120内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
基底100的第一表面100a上具有一绝缘层130。一般而言，绝缘层130可由层间介电层(interlayer dielectric，ILD)、金属间介电层(inter-metal dielectric，IMD)及覆盖的钝化层(passivation)组成。为简化图式，此处仅绘示出单层绝缘层130。换句话说，晶片封装结构A包括由基底100及绝缘层130所构成的一晶片/晶粒。在某些实施例中，绝缘层130可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在某些实施例中，基底100的第一表面100a上的绝缘层130内具有一个或一个以上的导电垫140。在某些实施例中，导电垫140可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明，并以绝缘层130内的两个导电垫140作为范例说明。在某些实施例中，绝缘层130内包括一个或一个以上的开口，露出对应的导电垫140。在某些实施例中，感测区或元件区120可通过基底100内的内连线结构(未绘示)而与导电垫140电性连接。
在某些实施例中，一光学部件150设置于绝缘层130上，且对应于感测区或元件区120。在某些实施例中，光学部件150可为微透镜阵列、滤光层、其组合或其他适合的光学部件。在某些其他实施例中，晶片封装结构A可不包括光学部件150。
在某些实施例中，一盖板170设置于基底100的第一表面100a上，以保护光学部件150。在某些其他实施例中，晶片封装结构A可不包括盖板170，因而露出绝缘层130及光学部件150。在某些实施例中，盖板170可包括玻璃、石英、透明高分子或其他适合的透明材料。
在某些实施例中，基底100与盖板170之间具有一间隔层(或称作围堰(dam))160，覆盖导电垫140而露出光学部件150。在某些实施例中，间隔层160、盖板170及绝缘层130在感测区或元件区120上共同围绕出一空腔180，使得光学部件150位于空腔180内。在某些其他实施例中，晶片封装结构A可不包括间隔层160。
在某些实施例中，间隔层160大致上不吸收水气。在某些实施例中，间隔层160不具有粘性，因此可通过额外的粘着胶将盖板170贴附于基底100上。在某些其他实施例中，间隔层160可具有粘性，因此可通过间隔层160将盖板170贴附于基底100上，如此一来间隔层160可不与任何的粘着胶接触，以确保间隔层160的位置不因粘着胶而移动。同时，由于不需使用粘着胶，可避免粘着胶溢流而污染光学部件150。
在某些实施例中，间隔层160可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))、光阻材料或其他适合的绝缘材料。
在某些实施例中，多个开口190贯穿基底100且延伸至绝缘层130内，进而自基底100的第二表面100b露出对应的导电垫140。在某些实施例中，开口190邻近于第一表面100a的口径小于其邻近于第二表面100b的口径，因此开口190具有倾斜的侧壁。在某些其他实施例中，开口190邻近于第一表面100a的口径可能等于或大于其邻近于第二表面100b的口径。
在某些实施例中，一绝缘层210设置于基底100的第二表面100b上，且顺应性地延伸至开口190的侧壁上，并露出导电垫140。在某些实施例中，绝缘层210可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
在某些实施例中，一图案化的重布线层220设置于基底100的第二表面100b上，且顺应性地延伸至开口190的侧壁及底部上。重布线层220可通过绝缘层210与基底100电性隔离，且可经由开口190直接电性接触或间接电性连接露出的导电垫140。因此，开口190内的重布线层220也称为硅通孔电极(through silicon via，TSV)。在其他实施例中，重布线层220也可能以T型接触(T-contact)或其他适合的方式电性连接至对应的导电垫140。
在某些实施例中，重布线层220可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
在某些实施例中，一保护层230设置于基底100的第二表面100b上，且填入开口190，以覆盖重布线层220。在某些实施例中，保护层230未填满开口190，使得一孔洞形成于开口190内的重布线层220与保护层230之间。在某些其他实施例中，保护层230填满开口190。在某些实施例中，保护层230具有平坦的表面。在某些其他实施例中，保护层230具有不平坦的表面，例如保护层230的表面具有对应于开口190的凹陷部。
在某些实施例中，保护层230可包括环氧树脂、绿漆(solder mask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
基底100的第二表面100b上的保护层230具有开口240及250，露出重布线层220的一部分。在某些实施例中，开口240的宽度大于开口250的宽度。在某些其他实施例中，开口240的宽度可能等于或小于开口250的宽度。
在某些实施例中，多个第一导电结构260(例如，焊球、凸块或导电柱)设置于保护层230的多个开口240内，以与露出的重布线层220及感测区或元件区120电性连接。在某些实施例中，第一导电结构260可包括锡、铅、铜、金、镍、其他适合的导电材料、或前述的组合。
在某些实施例中，接合层270设置于保护层230的开口250内，而与露出的重布线层220电性连接。在某些实施例中，接合层270可包括锡、铅、铜、金、镍、其他适合的接合材料、或前述的组合。在某些实施例中，接合层270的材料相同于第一导电结构260的材料。在某些其他实施例中，接合层270的材料不同于第一导电结构260的材料。
在某些实施例中，一无源元件300纵向地堆迭于基底100上，无源元件300与基底100并非彼此横向排列。无源元件300与第一导电结构260位于基底100的同一侧，且彼此横向排列。再者，无源元件300与光学部件150位于基底100的相对两侧，无源元件300与盖板170位于基底100的相对两侧。在某些实施例中，多个第一导电结构260非连续地或分散地环绕无源元件300。
在某些实施例中，无源元件300的厚度小于第一导电结构260的厚度。在某些实施例中，无源元件300的尺寸小于基底100的尺寸。再者，当基底100的尺寸足够大或无源元件300的尺寸足够小时，可在基底100的第二表面100b上设置一个以上具有相同或不同功能的无源元件300。在某些实施例中，无源元件300对应于基底100的中心，且完全或局部重迭于感测区或元件区120。在某些其他实施例中，无源元件300可能未重迭于感测区或元件区120。
在某些实施例中，无源元件300可为集成/整合无源元件(integrated passivedevice，IPD)。在某些其他实施例中，无源元件300可为电阻、电容、电感或其他适合的无源元件。如图2所示，无源元件300内具有一元件区310。元件区310内的电路可构成电阻、电容、电感、其他适合的无源元件、或其组合。
在某些实施例中，多个接合结构320设置于无源元件300的上表面上，如图2所示。接合结构320与元件区310电性连接。在某些实施例中，接合结构320与基底100位于无源元件300的同一侧。
在某些实施例中，接合结构320设置于开口250内，且突出于开口250。在某些实施例中，接合结构320直接接触重布线层220，且由接合层270所局部环绕，如图1E所示。在某些其他实施例中，接合结构320嵌入接合层270内。一部分的接合层270可纵向地夹设于接合结构320与重布线层220之间。在某些实施例中，接合结构320与第一导电结构260及/或接合层270皆位于重布线层220上，因此接合结构320与第一导电结构260及/或接合层270位于相同层位。
在某些实施例中，接合结构320的厚度介于大约10μm至大约20μm的范围内，例如15μm。在某些实施例中，接合结构320可包括铜、铝、其他适合的导电材料、或前述的组合。包含铜的接合结构320可在基底100与无源元件300之间提供良好的电性连接路径，降低功率及/或信号的衰减。再者，接合结构320也可为晶片封装结构A提供良好的导热路径。
在某些实施例中，接合结构320的材料不同于第一导电结构260及/或接合层270的材料。在某些其他实施例中，接合结构320的材料相同于第一导电结构260及/或接合层270的材料。在某些实施例中，接合结构320为导电柱、导电层或其他适合的接合结构。
如图2所示，多个开口330延伸于无源元件300内。元件区310经由开口330自无源元件300的下表面局部露出。在某些实施例中，开口330的结构相同或类似于开口190的结构。再者，一绝缘层340设置于无源元件300的下表面，且绝缘层340顺应性地延伸至开口330的侧壁上，并局部露出元件区310。在某些实施例中，绝缘层340的结构及/或材料相同或类似于绝缘层210的结构及/或材料。
图案化的重布线层350设置于无源元件300的下表面，且顺应性地延伸至开口330的侧壁及底部上。重布线层350可经由开口330电性连接露出的元件区310，因此开口330内的重布线层350也称为硅通孔电极。在某些实施例中，重布线层350的结构及/或材料相同或类似于重布线层220的结构及/或材料。再者，一保护层360设置于无源元件300的下表面，且填入开口330，以覆盖重布线层350。在某些实施例中，保护层360的结构及/或材料相同或类似于保护层230的结构及/或材料。
无源元件300的下表面上的保护层360具有开口370，露出重布线层350的一部分。再者，多个第二导电结构380(例如，焊球、凸块或导电柱)设置于保护层360的多个开口370内，以与露出的重布线层350电性连接。第二导电结构380与基底100位于无源元件300的相对两侧。在某些实施例中，第二导电结构380的尺寸小于第一导电结构260的尺寸。在某些实施例中，第二导电结构380的厚度小于接合结构320的厚度。在某些其他实施例中，第二导电结构380的厚度可等于或大于接合结构320的厚度。
在某些实施例中，第二导电结构380可包括锡、铅、铜、金、镍、其他适合的导电材料、或前述的组合。在某些实施例中，第二导电结构380的材料相同于第一导电结构260及/或接合结构320的材料。在某些其他实施例中，第二导电结构380的材料不同于第一导电结构260及/或接合结构320的材料。
如图1E所示，第二导电结构380的顶部(顶表面)与第一导电结构260的顶部(顶表面)大致上对齐于平面P。换句话说，第二导电结构380的顶部与第一导电结构260的顶部大致上共平面。在某些实施例中，接合结构320、无源元件300及第二导电结构380的总厚度大致上相同于第一导电结构260的厚度。
在某些实施例中，基底100及无源元件300可接合于一电路板(未绘示)上。基底100通过第一导电结构260与电路板物理性连接，且基底100内的感测区或元件区120通过第一导电结构260与电路板电性连接。无源元件300通过第二导电结构380与电路板物理性及电性连接。在某些实施例中，通过电路的布局设计，使得晶片封装体经由第二导电结构380传输功率，且经由第一导电结构260传输信号。在某些其他实施例中，晶片封装体经由第二导电结构380及某些第一导电结构260传输功率，且经由其他的第一导电结构260传输信号。由于功率对电磁效应的影响较大，因此经由第二导电结构380传输功率，能够利用无源元件300提供稳定电流的功能，尽可能避免功率的强度降低。
根据本发明的上述实施例，能够将一个或一个以上的无源元件整合于晶片封装体内，而大致上不会增加晶片封装体的尺寸，如此一来晶片封装体所连接的电路板不再需要保留设置无源元件的空间，进而可以缩小电路板的尺寸，因此所形成的电子产品的尺寸能够进一步降低。再者，由于无源元件直接与晶片连接，大幅缩短了无源元件与晶片之间的电性传输路径，因此可避免功率及/或信号的衰减，也有效防止噪声的产生，使得电子产品的品质及可靠度提升。
在上述实施例中，晶片封装体包括前照式(front side illumination，FSI)感测装置，但在某些其他实施例中，晶片封装体亦可包括背照式(back side illumination，BSI)感测装置。另外，虽然上述实施例以光学感测装置作为范例说明，然而本发明并不限定于此，可以应用本发明将无源元件整合于任何适合类型的晶片封装体内。
以下配合图1A至1E及图2说明本发明某些实施例的晶片封装体的制造方法，其中图1A至1E是绘示出根据本发明某些实施例的晶片封装体的制造方法的剖面示意图，且图2是绘示出根据本发明某些实施例的无源元件的剖面示意图。
请参照图1A，提供一基底100，其具有一第一表面100a及与其相对的一第二表面100b，且包括多个晶片区110。为简化图式，此处仅绘示出单一晶片区110。在某些实施例中，基底100可为一硅基底或其他半导体基底。在某些实施例中，基底100为一硅晶圆，以利于进行晶圆级封装制程。
在某些实施例中，每一晶片区110的基底100内具有一感测区或元件区120。感测区或元件区120可邻近于第一表面100a，且感测区或元件区120内可包括一感测元件及/或一有源元件(例如，晶体管)。在某些实施例中，感测区或元件区120内包括感光元件或其他适合的光电元件。在其他实施例中，感测区或元件区120内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
基底100的第一表面100a上具有一绝缘层130。一般而言，绝缘层130可由层间介电层、金属间介电层及覆盖的钝化层组成。为简化图式，此处仅绘示出单层绝缘层130。在某些实施例中，绝缘层130可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在某些实施例中，每一晶片区110的绝缘层130内具有一个或一个以上的导电垫140。在某些实施例中，导电垫140可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明，并以绝缘层130内的两个导电垫140作为范例说明。在某些实施例中，每一晶片区110的绝缘层130内包括一个或一个以上的开口，露出对应的导电垫140。在某些实施例中，感测区或元件区120内的感测元件可通过基底100内的内连线结构(未绘示)而与导电垫140电性连接。
在某些实施例中，可依序进行半导体装置的前段(front end)制程及后段(backend)制程来制作前述结构。例如，在进行前段制程期间，在基底100内制作感测区或元件区120，且在进行后段制程期间，在基底100上制作绝缘层130、内连线结构及导电垫140。换句话说，以下晶片封装体的制造方法用于对完成后段制程的基底进行后续的封装制程。
在某些实施例中，每一晶片区110内具有一光学部件150设置于基底100的第一表面100a上，且对应于感测区或元件区120。在某些实施例中，光学部件150可为微透镜阵列、滤光层、其组合或其他适合的光学部件。
接着，在一盖板170上形成一间隔层160，通过间隔层160将盖板170接合至基底100的第一表面100a上，且间隔层160在每一晶片区110内的基底100与盖板170之间形成一空腔180，使得光学部件150位于空腔180内，并通过盖板170保护空腔180内的光学部件150。在其他实施例中，可先在基底100上形成间隔层160，之后将盖板170接合至基底100上。
在某些实施例中，盖板170可包括玻璃、石英、透明高分子或其他适合的透明材料。在某些实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)形成间隔层160。再者，间隔层160可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。或者，间隔层160可包括光阻材料，且可通过曝光及显影制程而图案化，以露出光学部件150。
请参照图1B，以盖板170作为承载基板，对基底100的第二表面100b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、磨削(grinding)制程或研磨(polishing)制程)，以减少基底100的厚度。
接着，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在每一晶片区110的基底100内形成多个开口190，开口190自基底100的第二表面100b露出绝缘层130。
在某些实施例中，开口190对应于导电垫140而贯穿基底100，且开口190邻近于第一表面100a的口径小于其邻近于第二表面100b的口径，因此开口190具有倾斜的侧壁，进而降低后续形成于开口190内的膜层的制程难度，并提高可靠度。举例来说，由于开口190邻近于第一表面100a的口径小于其邻近于第二表面100b的口径，因此后续形成于开口190内的膜层(例如，绝缘层及重布线层)能够较轻易地沉积于开口190与绝缘层130之间的转角，以避免影响电性连接路径或产生漏电流的问题。
在某些实施例中，可通过微影制程及蚀刻制程，在相邻晶片区110之间的基底100内形成额外的开口(或沟槽)，此额外的开口沿着晶片区110之间的切割道延伸且贯穿基底100，使得多个晶片区110内的基底100的多个部分彼此分离。再者，此额外的开口可具有倾斜的侧壁，亦即多个晶片区110内的基底100的多个部分会具有倾斜的边缘侧壁。
请参照图1C，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底100的第二表面100b上形成一绝缘层210。在某些实施例中，绝缘层210顺应性地沉积于开口190的侧壁及底部上。在某些实施例中，绝缘层210可包括环氧树脂、无机材料、有机高分子材料或其他适合的绝缘材料。
接着，可通过微影制程及蚀刻制程，去除开口190底部的绝缘层210及其下方的绝缘层130，使得开口190延伸至绝缘层130内而露出对应的导电垫140。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在绝缘层210上形成图案化的重布线层220。重布线层220顺应性地延伸至开口190的侧壁及底部。重布线层220可通过绝缘层210与基底100电性隔离，且可经由开口190直接电性接触或间接电性连接露出的导电垫140。在某些实施例中，重布线层220可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料或其他适合的导电材料。
请参照图1D，可通过沉积制程，在基底100的第二表面100b上形成一保护层230，且填入开口190，以覆盖重布线层220。在某些实施例中，保护层230可包括环氧树脂、绿漆、无机材料、有机高分子材料或其他适合的绝缘材料。
在某些实施例中，保护层230仅局部填充开口190，使得一孔洞形成于开口190内的重布线层220与保护层230之间。在某些实施例中，孔洞与保护层230之间的界面具有拱形轮廓。由于保护层230部分填充于开口190而留下孔洞，因此后续制程中遭遇热循环(thermalcycle)时，孔洞能够作为保护层230与重布线层220之间的缓冲，以降低保护层230与重布线层220之间由于热膨胀系数不匹配所引发不必要的应力，且防止外界温度或压力剧烈变化时保护层230会过度拉扯重布线层220，进而可避免靠近导电垫结构的重布线层220剥离甚至断路的问题。
接着，可通过微影制程及蚀刻制程，在基底100的第二表面100b上的保护层230内形成开口240及250，以露出图案化的重布线层220的一部分。在某些实施例中，开口240的宽度大于开口250的宽度。在某些其他实施例中，开口240的宽度可能等于或小于开口250的宽度。
请参照图1D，可通过网版印刷制程或其他适合的制程，在保护层230的开口250内填入接合层270，而与露出的重布线层220电性连接。在某些实施例中，接合层270局部填入开口250。在某些其他实施例中，接合层270全部填满开口250。在某些实施例中，开口250内的接合层270突出于开口250。在某些其他实施例中，开口250内的接合层270进一步延伸至保护层230上。在某些实施例中，接合层270可包括锡、铅、铜、金、镍、其他适合的接合材料、或前述的组合。
接着，可通过网版印刷制程或其他适合的制程，在保护层230的开口240内填入多个第一导电结构260，以与露出的重布线层220及感测区或元件区120电性连接。第一导电结构260填满开口240，且突出于开口240。在某些实施例中，第一导电结构260可包括锡、铅、铜、金、镍、其他适合的导电材料、或前述的组合。在某些实施例中，第一导电结构260的形成方法相同于接合层270的形成方法。
之后，沿着相邻晶片区110之间的切割道(未绘示)切割保护层230、基底100、绝缘层130、间隔层160及盖板170，以形成多个独立的晶片封装结构A。举例来说，可使用切割刀具或激光进行切割制程，其中使用激光切割制程可以避免上下膜层发生位移。
请参照图1E，将一无源元件300放置于晶片封装结构A上，且进行回焊(reflow)制程，使得无源元件300与晶片封装结构A互相接合及电性连接。具体而言，无源元件300接合于基底100的第二表面100b上，使得无源元件300与基底100纵向地堆迭。在某些实施例中，无源元件300的尺寸小于基底100的尺寸。再者，当基底100的尺寸足够大或无源元件300的尺寸足够小时，可在基底100的第二表面100b上接合一个以上具有相同或不同功能的无源元件300。
在某些实施例中，无源元件300与第一导电结构260位于基底100的同一侧，且彼此横向排列。再者，无源元件300与光学部件150及盖板170位于基底100的相对两侧。在某些实施例中，无源元件300可被多个第一导电结构260所环绕。在某些实施例中，无源元件300可为集成/整合无源元件。在某些其他实施例中，无源元件300可为电阻、电容、电感或其他适合的无源元件。
请参照图2，无源元件300内具有一元件区310。元件区310内的电路结构可构成电阻、电容、电感、其他适合的无源元件、或其组合。在某些实施例中，在将无源元件300接合至晶片封装结构A之前，多个接合结构320形成于无源元件300的上表面上，且与元件区310电性连接。在某些实施例中，接合结构320可包括铜、铝、其他适合的导电材料、或前述的组合。
如图2所示，多个开口330形成于无源元件300内且自无源元件300的下表面局部露出元件区310。一绝缘层340形成于无源元件300的下表面，且顺应性地延伸至开口330的侧壁上，并局部露出元件区310。图案化的重布线层350形成于无源元件300的下表面，且顺应性地延伸至开口330的侧壁及底部上。一保护层360形成于无源元件300的下表面，且填入开口330，以覆盖重布线层350。再者，无源元件300的下表面上的保护层360内形成开口370，露出重布线层350的一部分。在某些实施例中，开口330、绝缘层340、重布线层350、保护层360、开口370的配置及形成方法分别相同或类似于开口190、绝缘层210、重布线层220、保护层230、开口240的配置及形成方法，故此处不再重复说明。
在某些实施例中，在形成开口330之前，可先对无源元件300的下表面进行薄化制程(例如，蚀刻制程、铣削制程、磨削制程或研磨制程)，以减少无源元件300的厚度。
接着，可通过网版印刷制程或其他适合的制程，在保护层360的多个开口370内填入多个第二导电结构380，以与露出的重布线层350电性连接。第二导电结构380填满开口370，且突出于开口370。在某些实施例中，第二导电结构380可包括锡、铅、铜、金、镍、其他适合的导电材料、或前述的组合。在某些实施例中，第二导电结构380的形成方法相同于第一导电结构260及/或接合层270的形成方法。
在某些实施例中，无源元件300的基底为晶圆，且通过进行晶圆级封装制程及切割制程，以形成多个无源元件300。可以理解的是，图2所示的无源元件300仅作为范例说明，无源元件300的结构并不限定于此。再者，为简化图式，图1E中未绘示出图2中的开口330、绝缘层340、重布线层350、保护层360、开口370。
如前述，在将无源元件300放置于晶片封装结构A上之后，同时对第一导电结构260、接合层270、第二导电结构380进行回焊制程，使得无源元件300通过接合结构320及接合层270与晶片封装结构A互相接合及电性连接。在某些实施例中，通过将接合结构320埋置于接合层270内，使得接合结构320由接合层270所环绕，进而在无源元件300与基底100之间形成稳固的接合键结。在某些实施例中，一部分的接合层270受到接合结构320挤压而自开口250延伸到保护层230上方。在某些其他实施例中，接合层270可能未延伸到保护层230上方。
在某些实施例中，接合结构320与第一导电结构260及/或接合层270皆位于重布线层220上，因此接合结构320与第一导电结构260及/或接合层270位于相同层位。在某些其他实施例中，一部分的接合层270可夹设于接合结构320与重布线层220之间，因此接合结构320与第一导电结构260及/或接合层270位于不同层位。
如图1E所示，接合结构320嵌入接合层270内，使得第二导电结构380的顶部(顶表面)与第一导电结构260的顶部(顶表面)大致上对齐于平面P。换句话说，第二导电结构380的顶部与第一导电结构260的顶部大致上共平面。在某些实施例中，无源元件300的厚度小于第一导电结构260的厚度。在某些实施例中，接合结构320、无源元件300及第二导电结构380的总厚度大致上相同于第一导电结构260的厚度。
在某些实施例中，通过进行回焊制程，将无源元件300及晶片封装结构A接合于一电路板(未绘示)上，此时基底100通过第一导电结构260与电路板物理性及电性连接，且无源元件300通过第二导电结构380与电路板物理性及电性连接。由于第二导电结构380的顶部与第一导电结构260的顶部大致上共平面，因此无源元件300及晶片封装结构A能顺利地直接接合至电路板上。如此一来，一个或一个以上的无源元件能够直接整合于晶片封装体内，所连接的电路板不再需要保留设置无源元件的空间，因此可以进一步缩小电子产品的尺寸。
再者，由于无源元件300直接与晶片封装结构A连接，大幅缩短了无源元件300与晶片封装结构A之间的电性传输路径，因此可完整地传输功率，避免信号变差，也有效防止噪声的产生，进而提升电子产品的品质及可靠度。
可以理解的是，虽然图1A至1E的实施例为具有前照式感测装置的晶片封装体的制造方法，然而关于晶片的外部电性连接路径(例如，基底内的开口、重布线层、保护层、导电结构等)及无源元件的制作方法亦可应用于背照式感测装置的制程中或是其他类型的晶片封装体的制程中。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一基底，其中该基底内具有一感测区或元件区；
一第一导电结构，其中该第一导电结构位于该基底上，且与该感测区或元件区电性连接；以及
一无源元件，其中该无源元件纵向地堆迭于该基底上，且与该第一导电结构横向排列。
2.根据权利要求1所述的晶片封装体，其特征在于，还包括一第二导电结构，其中该第二导电结构与该基底位于该无源元件的相对两侧。
3.根据权利要求2所述的晶片封装体，其特征在于，该第二导电结构的材料相同于该第一导电结构的材料。
4.根据权利要求2所述的晶片封装体，其特征在于，该第二导电结构的顶部大致上对齐于该第一导电结构的顶部。
5.根据权利要求2所述的晶片封装体，其特征在于，该第二导电结构的尺寸小于该第一导电结构的尺寸。
6.根据权利要求1所述的晶片封装体，其特征在于，该无源元件通过一接合结构接合于该基底上。
7.根据权利要求6所述的晶片封装体，其特征在于，该接合结构与该第一导电结构位于相同层位。
8.根据权利要求6所述的晶片封装体，其特征在于，该接合结构由一接合层所环绕，且该接合层的材料不同于该接合结构的材料。
9.根据权利要求8所述的晶片封装体，其特征在于，该接合层的材料相同于该第一导电结构的材料。
10.根据权利要求1所述的晶片封装体，其特征在于，该无源元件的厚度小于该第一导电结构的厚度。
11.根据权利要求1所述的晶片封装体，其特征在于，该无源元件与该感测区或元件区重迭。
12.一种晶片封装体的制造方法，其特征在于，包括：
提供一基底，其中该基底内具有一感测区或元件区；
在该基底上形成一第一导电结构，其中该第一导电结构与该感测区或元件区电性连接；以及
将一无源元件纵向地堆迭于该基底上，其中该无源元件与该第一导电结构横向排列。
13.根据权利要求12所述的晶片封装体的制造方法，其特征在于，还包括在将该无源元件纵向地堆迭于该基底上之前，在该基底上形成一接合层，其中将具有一接合结构的该无源元件纵向地堆迭于该基底上，使得该接合结构嵌入该接合层内。
14.根据权利要求13所述的晶片封装体的制造方法，其特征在于，通过相同的制程形成该接合层及该第一导电结构。
15.根据权利要求13所述的晶片封装体的制造方法，其特征在于，还包括对该第一导电结构及该接合层进行回焊制程。
16.根据权利要求12所述的晶片封装体的制造方法，其特征在于，还包括：
在将该无源元件纵向地堆迭于该基底上之前，在该无源元件上形成一第二导电结构，其中将具有该第二导电结构的该无源元件纵向地堆迭于该基底上。
17.根据权利要求16所述的晶片封装体的制造方法，其特征在于，该第二导电结构的顶部与该第一导电结构的顶部大致上共平面。
18.根据权利要求16所述的晶片封装体的制造方法，其特征在于，通过相同的制程形成该第二导电结构及第一导电结构。
19.根据权利要求16所述的晶片封装体的制造方法，其特征在于，还包括对该第一导电结构及该第二导电结构进行回焊制程。
20.根据权利要求12所述的晶片封装体的制造方法，其特征在于，还包括在将该无源元件纵向地堆迭于该基底上之前，对该基底进行切割制程。
CN201610905650.XA 2015-10-21 2016-10-18 晶片封装体及其制造方法 Withdrawn CN106611715A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562244593P 2015-10-21 2015-10-21
US62/244,593 2015-10-21

Publications (1)

Publication Number Publication Date
CN106611715A true CN106611715A (zh) 2017-05-03

Family

ID=58559007

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610905650.XA Withdrawn CN106611715A (zh) 2015-10-21 2016-10-18 晶片封装体及其制造方法

Country Status (3)

Country Link
US (1) US20170117242A1 (zh)
CN (1) CN106611715A (zh)
TW (1) TWI642149B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107863363A (zh) * 2017-11-20 2018-03-30 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN108831860A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9943239B2 (en) * 2016-03-07 2018-04-17 Taiwan Semiconductor Manufacturing Company Ltd. Optical sensing system and associated electronic device
CN109411487B (zh) * 2017-08-15 2020-09-08 胜丽国际股份有限公司 堆叠式感测器封装结构
US20190096866A1 (en) * 2017-09-26 2019-03-28 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US11990494B2 (en) 2020-08-06 2024-05-21 Powertech Technology Inc. Package structure and manufacturing method thereof
TWI788903B (zh) * 2020-08-06 2023-01-01 力成科技股份有限公司 封裝結構及其製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1139297A (zh) * 1995-03-27 1997-01-01 摩托罗拉公司 连接衬底的结构和方法
TW200727425A (en) * 2006-01-06 2007-07-16 Advanced Semiconductor Eng Packaging structure of camera module
CN101055866A (zh) * 2006-04-11 2007-10-17 夏普株式会社 光学装置用模块和光学装置用模块的制造方法
CN101335267A (zh) * 2007-06-27 2008-12-31 财团法人工业技术研究院 具晶粒三维堆叠结构的影像感测模块
US20120193789A1 (en) * 2011-01-27 2012-08-02 Unimicron Technology Corporation Package stack device and fabrication method thereof
CN202394956U (zh) * 2011-12-02 2012-08-22 日月光半导体（上海）股份有限公司 半导体封装构造

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225692B1 (en) * 1999-06-03 2001-05-01 Cts Corporation Flip chip package for micromachined semiconductors
US6214644B1 (en) * 2000-06-30 2001-04-10 Amkor Technology, Inc. Flip-chip micromachine package fabrication method
TW512505B (en) * 2001-11-06 2002-12-01 Jian Huei Jiuan Common type packaging method of microsensor
US20080191333A1 (en) * 2007-02-08 2008-08-14 Advanced Chip Engineering Technology Inc. Image sensor package with die receiving opening and method of the same
US7498556B2 (en) * 2007-03-15 2009-03-03 Adavanced Chip Engineering Technology Inc. Image sensor module having build-in package cavity and the method of the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1139297A (zh) * 1995-03-27 1997-01-01 摩托罗拉公司 连接衬底的结构和方法
TW200727425A (en) * 2006-01-06 2007-07-16 Advanced Semiconductor Eng Packaging structure of camera module
CN101055866A (zh) * 2006-04-11 2007-10-17 夏普株式会社 光学装置用模块和光学装置用模块的制造方法
CN101335267A (zh) * 2007-06-27 2008-12-31 财团法人工业技术研究院 具晶粒三维堆叠结构的影像感测模块
US20120193789A1 (en) * 2011-01-27 2012-08-02 Unimicron Technology Corporation Package stack device and fabrication method thereof
CN202394956U (zh) * 2011-12-02 2012-08-22 日月光半导体（上海）股份有限公司 半导体封装构造

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107863363A (zh) * 2017-11-20 2018-03-30 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN108831860A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构

Also Published As

Publication number Publication date
TW201715662A (zh) 2017-05-01
US20170117242A1 (en) 2017-04-27
TWI642149B (zh) 2018-11-21

Similar Documents

Publication Publication Date Title
TWI629759B (zh) 晶片封裝體及其製造方法
CN106611715A (zh) 晶片封装体及其制造方法
TWI597813B (zh) 晶片封裝體及其製造方法
CN104681516B (zh) 晶片封装体及其制造方法
TW201947679A (zh) 晶片封裝體及其製造方法
US9997473B2 (en) Chip package and method for forming the same
US10157875B2 (en) Chip package and method for forming the same
CN106531641B (zh) 晶片封装体及其制造方法
CN105720040B (zh) 晶片封装体及其制造方法
US10153237B2 (en) Chip package and method for forming the same
US9761510B2 (en) Chip package and method for forming the same
TWI611528B (zh) 晶片模組及其製造方法
TWI595618B (zh) 感測模組及其製造方法
TWI717846B (zh) 晶片封裝體及其製造方法
CN106935555A (zh) 晶片封装体及其制造方法
CN107039286A (zh) 感测装置及其制造方法
CN104979426A (zh) 晶片封装体的制造方法
US20150325551A1 (en) Chip package and method for forming the same
TWI845129B (zh) 晶片封裝體及其製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20170503