CN105720040B - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN105720040B
CN105720040B CN201510809457.1A CN201510809457A CN105720040B CN 105720040 B CN105720040 B CN 105720040B CN 201510809457 A CN201510809457 A CN 201510809457A CN 105720040 B CN105720040 B CN 105720040B
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opening
substrate
layer
encapsulation body
wafer encapsulation
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CN105720040A (zh
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刘沧宇
李柏汉
简玮铭
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括：一基底，其具有一第一表面及与其相对的一第二表面；一介电层，设置于基底的第一表面上且包括一导电垫结构；一第一开口，贯穿基底，并露出导电垫结构的一表面；一第二开口，与第一开口连通，且贯穿导电垫结构；以及一重布线层，顺应性设置于第一开口的一侧壁及导电垫结构的表面上，并填入第二开口。本发明不仅能够增加重布线层与导电垫结构的接触面积，还能够增加重布线层与导电垫结构之间的结构强度，因此能够提升晶片封装体的可靠度或品质。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
一般的晶片封装体中，通常将导电层与信号接垫的表面接触，以形成外部电性连接的导电路径。
然而，上述信号接垫与导电层之间的导电性不佳，且结构强度不足，进而影响晶片封装体的品质。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体，包括：一基底，其具有一第一表面及与其相对的一第二表面；一介电层，设置于基底的第一表面上，其中介电层内包括一导电垫结构；一第一开口，贯穿基底，并露出导电垫结构的一表面；一第二开口，与第一开口连通，且贯穿导电垫结构；以及一重布线层，顺应性设置于第一开口的一侧壁及导电垫结构的表面上，并填入第二开口。
本发明还提供一种晶片封装体的制造方法，包括：提供一基底，其具有一第一表面及与其相对的一第二表面，基底的第一表面上具有一介电层，其中介电层内包括一导电垫结构；形成一第一开口，第一开口贯穿基底且露出导电垫结构的一表面；以及形成一第二开口，第二开口与第一开口连通，且贯穿导电垫结构；以及在第一开口的一侧壁及导电垫结构的表面上顺应性形成一重布线层，且重布线层填入第二开口。
本发明不仅能够增加重布线层与导电垫结构的接触面积，还能够增加重布线层与导电垫结构之间的结构强度，因此能够提升晶片封装体的可靠度或品质。
附图说明
图1A至1E是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2及3是绘示出根据本发明各种实施例的晶片封装体的剖面示意图。
其中，附图中符号的简单说明如下：
100、180：基底；100a、180a：第一表面；100b、180b：第二表面；110：元件区；120：晶片区；130：介电层；140：虚线；160：导电垫结构；160a、160b、160c：导电垫；200：光学元件；220：盖板；240：间隔层；260、380：空腔；280：第一开口；300：绝缘层；320：第二开口；340：重布线层；360：钝化保护层；400：导电结构。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System，MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emittingdiodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
请参照图1E，其绘示出根据本发明一实施例的晶片封装体的剖面示意图。为了说明本发明实施例，此处使用背照式(backside illumination，BSI)感测装置作为范例。然而，本发明实施例不限定于任何特定的应用。在本实施例中，晶片封装体包括一基底180、一介电层130、一第一开口280、一第二开口320及一重布线层(redistribution layer，RDL)340。基底180具有一第一表面180a及与其相对的一第二表面180b。在一实施例中，基底180可为一硅基底或其他适合的基底。
介电层130设置于基底180的第一表面180a上，且介电层130内包括一个或一个以上的导电垫结构160。在本实施例中，介电层130可由一层或多层介电材料(例如，二氧化硅、氮化物、氧化物、氮氧化物货其他适合的介电材料)所构成。在一实施例中，导电垫结构160可包括单一导电垫或一个以上垂直堆叠的导电垫，且可由导电材料(例如，铜、铝或其合金)所构成。为简化图式，此处仅以三个垂直堆叠的导电垫160a、160b及160c作为范例说明，且仅绘示出单一介电层130内的两个导电垫结构160作为范例说明。导电垫160a、导电垫160b及导电垫160c可通过介电层130互相绝缘，且通过导电插塞(未绘示)互相电性连接。在本实施例中，导电垫160a、导电垫160b及导电垫160c依序沿着自第二表面180b朝第一表面180a的方向垂直堆叠。
第一开口280自基底180的第二表面180b朝第一表面180a延伸而贯穿基底180，并进一步延伸至介电层130内，因而露出导电垫结构160中的导电垫160a的一表面。在一实施例中，第一开口280的侧壁倾斜于基底180的第一表面180a。在其他实施例中，第一开口280的侧壁可大致上垂直于基底180的第一表面180a。
第二开口320自导电垫160a的表面(即，第一开口280的底部)延伸而贯穿导电垫结构160中的所有导电垫160a、160b及160c，因而露出导电垫结构160的内部。在一实施例中，第二开口320的侧壁大致上垂直于基底180的第一表面180a。在其他实施例中，第二开口320的侧壁可倾斜于基底180的第一表面180a。在本实施例中，第二开口320与第一开口280连通，且第二开口320的直径小于第一开口280的直径。
一绝缘层300顺应性设置于基底180的第二表面180b上，且延伸至第一开口280内，并暴露出导电垫160a的表面。在本实施例中，绝缘层300可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他适合的绝缘材料。
图案化的重布线层340设置于绝缘层300上，且顺应性延伸至第一开口280的侧壁及底部上(亦即，重布线层340延伸至导电垫160a的表面上)，并进一步填满第二开口320。重布线层340可经由第一开口280直接电性接触或间接电性连接露出的导电垫160a，且亦可经由第二开口320直接电性接触或间接电性连接露出的所有导电垫160a、160b及160c的内部。另外，当基底180包括半导体材料(例如，硅)时，第一开口280内的重布线层340也称为硅通孔电极(through silicon via，TSV)，且重布线层340可通过绝缘层300与半导体材料电性隔离。在一实施例中，重布线层340可包括铜、铝、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
一钝化保护层360设置于绝缘层300上，且覆盖重布线层340，并填入第一开口280内。在一实施例中，钝化保护层360与第一开口280内的重布线层340之间具有一空腔380，位于第一开口280的底部。在其他实施例中，钝化保护层360可填满第一开口280。钝化保护层360具有开口(未绘示)，露出位于第二表面180b上的重布线层340的一部分。在本实施例中，钝化保护层360可包括环氧树脂、绿漆(solder mask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他适合的绝缘材料。
一导电结构400设置于钝化保护层360的开口内，以电性连接露出的重布线层340。在本实施例中，导电结构400可为凸块(例如，接合球或导电柱)或其他适合的导电结构，且可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
在本实施例中，晶片封装体还包括另一基底100，设置于介电层130上，基底100具有一第一表面100a(可视为前侧)及与其相对的一第二表面100b(可视为背侧)。在本实施例中，介电层130位于基底100的第一表面100a与基底180的第一表面180a之间，亦即基底100的第一表面100a邻近于导电垫结构160中的导电垫160c(可视为底层导电垫)，而基底180的第一表面180a邻近于导电垫结构160中的导电垫160a(可视为顶层导电垫)。在一实施例中，基底100可为一硅基底或其他半导体基底。
在本实施例中，基底100为一装置基底，且包括一元件区110。元件区110可包括影像感测元件(例如，光电二极管(photodiode)、光晶体管(phototransistor)或其他光感测器)。再者，基底100内可具有控制上述影像感测元件的集成电路(例如，互补型金属氧化物半导体晶体管(complementary metal oxide semiconductor，CMOS)、电阻或其他的半导体元件)，其与介电层130内的导电垫结构160电性连接。为了简化图式，此处仅绘示出平整的元件区110及光学元件200，且仅以虚线140表示元件区110与导电垫结构160之间的电性连接。
一光学元件200(例如，微透镜阵列、滤光层或其他适合的光学元件)可选择性设置于基底100的第二表面100b(即，背侧)上。一盖板220设置于基底100的第二表面100b上，以保护光学元件200。在本实施例中，盖板220可包括玻璃或其他适合的透明材料。再者，基底100与盖板220之间具有一间隔层(或称作围堰(dam))240，其围绕光学元件200，且于基底100与盖板220之间形成一空腔260。在一实施例中，间隔层240大致上不吸收水气。在一实施例中，间隔层240不具有粘性，因此间隔层240可通过额外的粘着胶，以将盖板220贴附于基底100上。在另一实施例中，间隔层240可具有粘性，因此间隔层240可不与任何的粘着胶接触，以确保间隔层240的位置不因粘着胶而移动。同时，由于不需使用粘着胶，可避免粘着胶溢流而污染光学元件200。在本实施例中，间隔层240可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他适合的绝缘材料。
请参照图2及3，其绘示出根据本发明各种实施例的晶片封装体的剖面示意图，其中相同于前述图1E的实施例的部件使用相同的标号并省略其说明。图2及3的实施例使用前照式(frontside illumination，FSI)感测装置作为范例说明。在图2的实施例中，晶片封装体包括一基底100、一介电层130、一第一开口280、一第二开口320及一重布线层340。基底100具有一第一表面100a(可视为前侧)及与其相对的一第二表面100b(可视为背侧)。在本实施例中，基底100为一装置基底，且包括具有影像感测元件的一元件区110。
介电层130设置于基底100的第一表面100a上，且包括导电垫结构160。导电垫结构160由垂直堆叠的导电垫160a(可视为顶层导电垫)、导电垫160b及导电垫160c(可视为底层导电垫)所构成，且与元件区110电性连接(如虚线140所示)。
一光学元件200(例如，微透镜阵列、滤光层或其他适合的光学元件)可选择性设置于介电层130及基底100的第一表面100a(即，前侧)上。一盖板220设置于介电层130上，以保护光学元件200。在本实施例中，介电层130位于盖板220与基底100之间。再者，介电层130与盖板220之间具有一间隔层(或称作围堰)240，其围绕光学元件200，且于介电层130与盖板220之间形成一空腔260。
第一开口280自基底100的第二表面100b朝第一表面100a延伸而贯穿基底100，并进一步延伸至介电层130内，因而露出导电垫结构160中的底层导电垫160c的一表面。第二开口320自底层导电垫160c的表面(即，第一开口280的底部)朝盖板220延伸，且同时贯穿导电垫结构160中的所有导电垫160a、160b及160c，因而露出导电垫结构160的内部。在本实施例中，第二开口320与第一开口280连通，且第二开口320的直径小于第一开口280的直径。
绝缘层300顺应性设置于基底100的第二表面100b上，且延伸至第一开口280内，并暴露出导电垫160c的表面。图案化的重布线层340设置于绝缘层300上，且顺应性延伸至第一开口280的侧壁及底部上(亦即，重布线层340延伸至导电垫160c的表面)，并进一步填满第二开口320。重布线层340可经由第一开口280直接电性接触或间接电性连接露出的导电垫160c，且亦可经由第二开口320直接电性接触或间接电性连接露出的所有导电垫160a、160b及160c的内部。在本实施例中，第一开口280内的重布线层340也称为硅通孔电极。
钝化保护层360设置于绝缘层300上，且覆盖重布线层340，并填入第一开口280内。在本实施例中，钝化保护层360可填满或不填满第一开口280。钝化保护层360具有开口(未绘示)，露出位于第二表面100b上的重布线层340的一部分。导电结构400设置于钝化保护层360的开口内，以电性连接露出的重布线层340。
图3中的晶片封装体的结构类似于图2中的晶片封装体的结构，差异在于图3中的第二开口320朝盖板220延伸而贯穿导电垫结构160及介电层130，并进一步延伸至间隔层240内。
根据本发明的上述实施例，由于基底内具有第二开口，自顶层或底层导电垫的表面(即，第一开口的底部)延伸而贯穿所有导电垫，且露出所有导电垫的内部，因此重布线层不仅直接电性接触顶层或底层导电垫的表面，更能够直接电性接触所有导电垫的内部，进而增加重布线层与导电垫结构的接触面积且提升导电性。
再者，由于重布线层通过第二开口而贯穿且嵌入所有导电垫的内部，进一步增加了重布线层与导电垫结构之间的结构强度，因此能够提升晶片封装体的可靠度或品质。
以下配合图1A至1E说明本发明一实施例的晶片封装体的制造方法，其中图1A至1E是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。为了说明本发明实施例，此处使用背照式(BSI)感测装置作为范例。然而，本发明实施例不限定于任何特定的应用。
请参照图1A，提供一基底100、一基底180及基底100与基底180之间的一介电层130。基底100具有一第一表面100a(可视为前侧)及与其相对的一第二表面100b(可视为背侧)，且包括多个晶片区。为简化图式，此处仅绘示出基底100的单一晶片区120。在一实施例中，基底100可为一硅基底或其他半导体基底。举例来说，基底100可为一硅晶圆，以利于进行晶圆级封装制程。在本实施例中，基底100为一装置基底，且每一晶片区120内的基底100包括一元件区110。元件区110可包括影像感测元件(例如，光电二极管、光晶体管或其他光感测器)。再者，基底100内可具有控制上述影像感测元件的集成电路(例如，互补型金属氧化物半导体晶体管(complementary metal oxide semiconductor，CMOS)、电阻或其他的半导体元件)。为了简化图式，此处仅绘示出平整的元件区110。
基底180具有一第一表面180a及与其相对的一第二表面180b。在一实施例中，基底180可为一硅基底或其他适合的基底。
介电层130位于基底100的第一表面100a与基底180的第一表面180a之间。在本实施例中，介电层130可由一层或多层介电材料(例如，二氧化硅、氮化物、氧化物、氮氧化物货其他适合的介电材料)所构成。在本实施例中，每一晶片区120内的介电层130中具有一个或一个以上的导电垫结构160，与基底100内的集成电路及元件区110电性连接。在一实施例中，导电垫结构160可包括单一导电垫或一个以上垂直堆叠的导电垫，且可由导电材料(例如，铜、铝或其合金)所构成。为简化图式，此处仅以三个垂直堆叠的导电垫160a、160b及160c作为范例说明，且仅绘示出基底100的单一晶片区120内的两个导电垫结构160作为范例说明，并以虚线140表示元件区110与导电垫结构160之间的电性连接。导电垫160a、导电垫160b及导电垫160c可通过介电层130互相绝缘，且通过导电插塞(未绘示)互相电性连接。在本实施例中，导电垫160a、导电垫160b及导电垫160c依序沿着自基底180朝基底100的方向垂直堆叠。因此，基底100的第一表面100a邻近于导电垫结构160中的导电垫160c(可视为底层导电垫)，而基底180的第一表面180a邻近于导电垫结构160中的导电垫160a(可视为顶层导电垫)。
在本实施例中，可选择性在每一晶片区120内的基底100的第二表面100b(即，背侧)上设置一光学元件200(例如，微透镜阵列、滤光层或其他适合的光学元件)。为了简化图式，此处仅绘示出平整的光学元件200。接着，以基底180作为支撑，将一盖板220贴附于基底100的第二表面100b上，以保护光学元件200。在本实施例中，盖板220可包括玻璃或其他适合的透明材料。基底100与盖板220之间具有一间隔层(或称作围堰)240，其围绕光学元件200，且于每一晶片区120内的基底100与盖板220之间形成一空腔260。在一实施例中，间隔层240大致上不吸收水气。在一实施例中，间隔层240不具有粘性，因此间隔层240可通过额外的粘着胶，以将盖板220贴附于基底100上。在另一实施例中，间隔层240可具有粘性，因此间隔层240可不与任何的粘着胶接触，以确保间隔层240的位置不因粘着胶而移动。同时，由于不需使用粘着胶，可避免粘着胶溢流而污染光学元件200。在本实施例中，间隔层240可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他适合的绝缘材料。
请参照图1B，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在每一晶片区120内形成多个第一开口280。第一开口280自基底180的第二表面180b朝第一表面180a延伸而贯穿基底180，并进一步延伸至介电层130内，因而露出导电垫结构160中的顶层导电垫160a的一表面。另外，在形成第一开口280之前，可选择性对基底180的第二表面180b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、机械研磨(mechanical grinding)制程或化学机械研磨(chemicalmechanical polishing)制程)，以减少基底180的厚度。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底180的第二表面180b上顺应性形成一绝缘层300，其延伸至第一开口280的侧壁及底部上。在本实施例中，绝缘层300可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
请参照图1C，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，去除第一开口280的底部上的绝缘层300，以暴露出导电垫160a的表面。接着，可通过激光钻孔(laser drilling)制程，在每一晶片区120内形成多个第二开口320。第二开口320自顶层导电垫160a的表面(即，第一开口280的底部)延伸，并同时贯穿导电垫结构160中的所有导电垫160a、160b及160c，因而露出导电垫结构160的内部。在本实施例中，第二开口320与第一开口280连通，且第二开口320的直径小于第一开口280的直径。
请参照图1D，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在绝缘层300上形成图案化的重布线层340。
重布线层340顺应性延伸至第一开口280的侧壁及底部上(亦即，重布线层340延伸至导电垫160a露出的表面上)，并进一步填满第二开口320。重布线层340可经由第一开口280直接电性接触或间接电性连接露出的导电垫160a，且亦可经由第二开口320直接电性接触或间接电性连接露出的所有导电垫160a、160b及160c的内部。另外，当基底180包括半导体材料(例如，硅)时，第一开口280内的重布线层340也称为硅通孔电极，且重布线层340可通过绝缘层300与半导体材料电性隔离。在一实施例中，重布线层340可包括铜、铝、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
在本实施例中，重布线层通过第二开口而嵌入所有导电垫的内部，进一步增加了重布线层与导电垫结构之间的接合强度，且避免重布线层与导电垫之间发生膜层剥离的问题，因此能够提升晶片封装体的可靠度。
请参照图1E，可通过沉积制程，在绝缘层300上形成一钝化保护层360，其覆盖重布线层340，并填入第一开口280内。在一实施例中，钝化保护层360与第一开口280内的重布线层340之间具有一空腔380，可避免钝化保护层360的应力过大而影响重布线层340。在其他实施例中，钝化保护层360可填满第一开口280。在本实施例中，钝化保护层360可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。在另一实施例中，钝化保护层360可包括光阻材料，且可通过曝光及显影制程，形成露出重布线层340的开口。
接着，可通过微影制程及蚀刻制程，在每一晶片区120中的钝化保护层360内形成开口(未绘示)，露出位于第二表面180b上的重布线层340的一部分。接着，在钝化保护层360的开口内形成导电结构400，以电性连接露出的重布线层340。举例来说，可通过电镀制程、网版印刷制程或其他适合的制程，在钝化保护层360的开口内形成焊料(solder)，且进行回焊(reflow)制程，以形成导电结构400。在本实施例中，导电结构400可为凸块(例如，接合球或导电柱)或其他适合的导电结构，且可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
接着，沿着相邻晶片区120之间的切割道(未绘示)，对盖板220、基底100、介电层130及基底180进行切割制程，以形成多个独立的晶片封装体。
可以理解的是，上述晶片封装体的制造方法并不限定于背照式感测装置，其亦可应用于前照式感测装置(如图2及3所示)或其他感测装置。举例来说，上述形成第二开口的制造方法可应用于具有生物特征感测元件(例如，指纹辨识元件)或环境特征感测元件(例如，温度感测元件、湿度感测元件、压力感测元件)的晶片封装体。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一基底，具有一第一表面及与该第一表面相对的一第二表面；
一介电层，设置于该基底的该第一表面上，其中该介电层内包括一导电垫结构；
一第一开口，贯穿该基底，并露出该导电垫结构的一表面；
一第二开口，与该第一开口连通，且贯穿该导电垫结构；以及
一重布线层，顺应性设置于该第一开口的一侧壁及该导电垫结构的该表面上，并填入该第二开口，其中该重布线层填满该第二开口且该重布线层不填满该第一开口。
2.根据权利要求1所述的晶片封装体，其特征在于，该第二开口的直径小于该第一开口的直径。
3.根据权利要求1所述的晶片封装体，其特征在于，该导电垫结构包括垂直堆叠的多个导电垫，且该第一开口露出该多个导电垫中的一个导电垫的一表面，且该第二开口自该多个导电垫中的一个导电垫的该表面延伸而贯穿该多个导电垫。
4.根据权利要求1所述的晶片封装体，其特征在于，还包括一钝化保护层，该钝化保护层设置于该第一开口内的该重布线层上。
5.根据权利要求4所述的晶片封装体，其特征在于，该钝化保护层与该重布线层之间具有一空腔。
6.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一盖板，其中该介电层位于该盖板与该基底之间；以及
一间隔层，设置于该盖板与该介电层之间。
7.根据权利要求6所述的晶片封装体，其特征在于，该第二开口还延伸至该间隔层内。
8.根据权利要求1所述的晶片封装体，其特征在于，还包括一另一基底，该另一基底具有一元件区，该元件区与该导电垫结构电性连接，其中该介电层位于该另一基底与该基底之间。
9.根据权利要求1所述的晶片封装体，其特征在于，该基底内具有一元件区，该元件区与该导电垫结构电性连接。
10.一种晶片封装体的制造方法，其特征在于，包括：
提供一基底，该基底具有一第一表面及与该第一表面相对的一第二表面，且该基底的该第一表面上具有一介电层，其中该介电层内包括一导电垫结构；
形成一第一开口，该第一开口贯穿该基底且露出该导电垫结构的一表面；
形成一第二开口，该第二开口与该第一开口连通，且贯穿该导电垫结构；以及
在该第一开口的一侧壁及该导电垫结构的该表面上顺应性形成一重布线层，且该重布线层填入该第二开口，其中该重布线层填满该第二开口且该重布线层不填满该第一开口。
11.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该第二开口的直径小于该第一开口的直径。
12.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该导电垫结构包括垂直堆叠的多个导电垫，且该第一开口露出该多个导电垫中的一个导电垫的一表面，且该第二开口自该多个导电垫中的一个导电垫的该表面延伸而贯穿该多个导电垫。
13.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括在该第一开口内的该重布线层上形成一钝化保护层。
14.根据权利要求13所述的晶片封装体的制造方法，其特征在于，一空腔形成于该钝化保护层与该第一开口内的该重布线层之间。
15.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括提供一盖板及一间隔层，其中该介电层位于该盖板与该基底之间，且该间隔层位于该盖板与该介电层之间。
16.根据权利要求15所述的晶片封装体的制造方法，其特征在于，该第二开口还延伸至该间隔层内。
17.根据权利要求10所述的晶片封装体的制造方法，其特征在于，还包括提供一另一基底，该另一基底具有一元件区，该元件区与该导电垫结构电性连接，其中该介电层位于该另一基底与该基底之间。
18.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该基底内具有一元件区，该元件区与该导电垫结构电性连接。
19.根据权利要求10所述的晶片封装体的制造方法，其特征在于，该基底为一晶圆。
20.根据权利要求19所述的晶片封装体的制造方法，其特征在于，还包括在形成该重布线层之后，切割该晶圆，以形成多个晶片封装体。
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