CN104733422B - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN104733422B
CN104733422B CN201410658808.9A CN201410658808A CN104733422B CN 104733422 B CN104733422 B CN 104733422B CN 201410658808 A CN201410658808 A CN 201410658808A CN 104733422 B CN104733422 B CN 104733422B
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substrate
encapsulation body
wafer encapsulation
body according
conductive pad
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CN104733422A (zh
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刘建宏
温英男
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XinTec Inc
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XinTec Inc
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract

本发明揭露一种晶片封装体及其制造方法。该晶片封装体包括：一第一基底，具有一第一表面及与第一表面相对的一第二表面，其中第一基底具有一微电子元件且具有邻近于第一表面的多个导电垫，且第一基底具有多个开口，所述开口分别暴露出每一导电垫的一部分；一第二基底，设置于第一表面上；一密封层，设置于第一表面上，且覆盖第二基底；一重布线层，设置于第二表面上，且延伸至开口内，以与导电垫电性连接。本发明能够进一步缩小晶片封装体的尺寸，且能够降低成本并节省制程时间。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装体及其制造方法，特别为有关于以晶圆级封装制程所形成的晶片封装体。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
制作晶片封装体的过程包括将晶圆基底切割为多个晶片之后，将晶片放置于尺寸大于晶片的导线架(lead frame)上，接着通过金焊线将晶片上的导电垫电性连接至导线架的接合垫，以形成晶片的外部电性连接的路径。
然而，由于使用金焊线及导线架作为外部电性连接的路径，成本较高，且使得晶片封装体的整体尺寸增加，因此难以进一步缩小晶片封装体的尺寸。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明实施例提供一种晶片封装体，包括：一第一基底，具有一第一表面及与第一表面相对的一第二表面，其中第一基底具有一微电子元件且具有邻近于第一表面的多个导电垫，且第一基底具有多个开口，所述开口分别暴露出每一导电垫的一部分；一第二基底，设置于第一表面上；一密封层，设置于第一表面上，且覆盖第二基底；一重布线层，设置于第二表面上，且延伸至开口内，以与导电垫电性连接。
本发明实施例提供一种晶片封装体的制造方法，包括：提供一第一基底，第一基底具有一第一表面及与第一表面相对的一第二表面，且第一基底具有一微电子元件且具有邻近于第一表面的多个导电垫；在第一表面上设置一第二基底；在第一表面上形成一密封层，以覆盖第二基底；在第一基底内形成多个开口，所述开口分别暴露出每一导电垫的一部分；在第二表面上形成一重布线层，其中重布线层延伸至开口内，以与导电垫电性连接。
本发明能够进一步缩小晶片封装体的尺寸，且能够降低成本并节省制程时间。
附图说明
图1A至1F绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2绘示出根据本发明另一实施例的晶片封装体的剖面示意图。
图3A至3D绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图。
图4绘示出根据本发明另一实施例的晶片封装体的剖面示意图。
图5A至5D绘示出根据本发明又另一实施例的晶片封装体的制造方法的剖面示意图。
图6绘示出根据本发明另一实施例的晶片封装体的剖面示意图。
其中，附图中符号的简单说明如下：
100 第一基底；
100a 第一表面；
100b 第二表面；
110 电子元件区；
120 导电垫；
140 间隔层；
150 空腔；
200 第二基底；
220 密封层；
230、232、234、236、238、285 开口；
240、280 绝缘层；
260 重布线层；
300 导电结构；
320 金属层；
340 导线；
400、500、600、700、800、900 晶片封装体；
SC 切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surface acoustic wave devices)、压力感测器(processsensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
请参照图1F，其绘示出根据本发明一实施例的晶片封装体400的剖面示意图。在本实施例中，晶片封装体400包括一第一基底100、一第二基底200、一密封层220及一重布线层260。第一基底100具有一第一表面100a及与其相对的一第二表面100b，且具有至少一微电子元件(未绘示)设置于电子元件区110内。在一实施例中，第一基底100为一硅晶圆，以利于进行晶圆级封装制程。在一实施例中，微电子元件可包括一互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)元件或一微机电系统(microelectro mechanical system，MEMS)元件。在本实施例中，第一基底100具有多个导电垫120，其可邻近于第一表面100a，且第一基底100具有多个开口230，从第二表面100b朝第一表面100a延伸，且分别暴露出每一导电垫120的表面的一部分。在一实施例中，导电垫120可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与电子元件区110内的微电子元件电性连接。
第二基底200可通过一间隔层(或称作围堰(dam))140设置于第一基底100的第一表面100a上。亦即，间隔层140设置于第一基底100与第二基底200之间。在一实施例中，第二基底200可为一晶片而具有至少一CMOS元件或一MEMS元件位于其内。设置于第一基底100与第二基底200之间的间隔层140在其间形成一空腔150，可通过在空腔150内形成金属柱(未绘示)，将第二基底200的CMOS元件或MEMS元件电性连接至第一基底100的电子元件区110内的微电子元件。在另一实施例中，第二基底200可包括一玻璃盖板或一硅盖板，其内不具有任何主动或被动元件。在本实施例中，间隔层140可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他适合的绝缘材料。
密封层220设置于第一基底100的第一表面100a上，且覆盖第二基底200及导电垫120，以提供晶片封装体的保护。在一实施例中，密封层220可包括模塑成型材料(moldingcompound)、密封材料或其他适合的材料。
一绝缘层240设置于第一基底100的第二表面100b上，且延伸至第一基底100的开口230的侧壁，而暴露出每一导电垫120的一部分。在一实施例中，绝缘层240可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
在本实施例中，重布线层260设置于第一基底100的第二表面100b上，且延伸至第一基底100的开口230的底部。重布线层260通过绝缘层240与第一基底100电性隔离并与暴露出的导电垫120直接接触，以电性连接至导电垫120。因此，开口230内的重布线层260也称为硅通孔电极(through silicon via，TSV)。在一实施例中，重布线层260可包括铜、铝、金、铂或其他适合的导电材料。
在本实施例中，晶片封装体400还包括绝缘层280及导电结构300(例如，焊球、凸块或导电柱)，设置于第一基底100的第二表面100b上。绝缘层280填入第一基底100的开口230内，以覆盖重布线层260且具有开口暴露出位于第二表面100b上的重布线层260的一部分。在一实施例中，绝缘层280可包括环氧树脂、绿漆(solder mask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。导电结构300设置于绝缘层280上且填入绝缘层280的开口285，以与重布线层260电性连接。在一实施例中，导电结构300可包括锡、铅、铜、金、镍、或前述的组合。
请参照图2，其绘示出根据本发明另一实施例的晶片封装体500的剖面示意图，其中相同于图1F中的部件使用相同的标号并省略其说明。图2中的晶片封装体500的结构类似于图1F中的晶片封装体400的结构，差异在于晶片封装体500还包括一金属层320，设置于第二基底200上，且通过至少一导线340将金属层320电性连接至导电垫120的其中一个(例如，接地垫)，以作为防止电磁干扰(electromagnetic interference，EMI)的屏蔽结构。
请参照图3D，其绘示出根据本发明又另一实施例的晶片封装体600的剖面示意图，其中相同于图1F中的部件使用相同的标号并省略其说明。在本实施例中，晶片封装体600包括一第一基底100、一第二基底200、一密封层220及一重布线层260。不同于图1F的晶片封装体400，在本实施例中，第一基底100的开口234延伸穿透导电垫120至密封层220，以暴露出导电垫120的内部。
在另一实施例中，第一基底100的开口234未延伸至密封层220内。在本实施例中，绝缘层240设置于第一基底100的第二表面100b上，且延伸至第一基底100的开口234的侧壁，而暴露出密封层220的一部分。
在本实施例中，重布线层260设置于第一基底100的第二表面100b上，且延伸至第一基底100的开口234内。在一实施例中，重布线层260还延伸至密封层220内。重布线层260通过绝缘层240与第一基底100电性隔离并与暴露出的导电垫120的内部直接接触，而以环型接触(ring-contact)的方式电性连接至导电垫120。
请参照图4，其绘示出根据本发明另一实施例的晶片封装体700的剖面示意图，其中相同于图3D中的部件使用相同的标号并省略其说明。图4中的晶片封装体700的结构类似于图3D中的晶片封装体600的结构，差异在于晶片封装体700还包括一金属层320，设置于第二基底200上，且至少一导线340将金属层320电性连接至导电垫120的其中一个(例如，接地垫)，以作为防止电磁干扰的屏蔽结构。
请参照图5D，其绘示出根据本发明又另一实施例的晶片封装体800的剖面示意图，其中相同于图1F中的部件使用相同的标号并省略其说明。在本实施例中，晶片封装体800包括一第一基底100、一第二基底200、一密封层220及一重布线层260。在本实施例中，绝缘层240具有多个开口238，暴露出导电垫120的侧壁。在一实施例中，开口238延伸至密封层220内。
在本实施例中，重布线层260设置于第一基底100的第二表面100b上，且延伸至绝缘层240的开口238内而不穿过第一基底100。重布线层260通过绝缘层240与第一基底100电性隔离并与暴露出的导电垫120的侧壁直接接触，而以T型接触(T-contact)的方式电性连接至导电垫120。在一实施例中，重布线层260还延伸至密封层220内。
请参照图6，其绘示出根据本发明另一实施例的晶片封装体900的剖面示意图，其中相同于图5D中的部件使用相同的标号并省略其说明。图6中的晶片封装体900的结构类似于图5D中的晶片封装体800的结构，差异在于晶片封装体900还包括一金属层320，设置于第二基底200上，且至少一导线340将金属层320电性连接至导电垫120的其中一个(例如，接地垫)，以作为防止电磁干扰的屏蔽结构。
根据本发明的上述实施例，由于使用硅通孔电极、环型接触或T型接触作为具有微电子元件的第一基底100的外部电性连接的路径，而不需使用焊线及导线架，能够节省成本，并使得晶片封装体的尺寸能够进一步缩小。再者，由于形成于第二基底200上的屏蔽结构可电性连接至第一基底100的导电垫120，而不需电性连接至导线架，因此额外形成上述屏蔽结构能够得到防止电磁干扰的效果，而不会增加晶片封装体的尺寸。另外，采用晶圆级制程来制作晶片封装体，可大量生产晶片封装体，进而降低成本并节省制程时间。
以下配合图1A至1F说明本发明一实施例的晶片封装体的制造方法，其中图1A至1F绘示出根据本发明一实施例的晶片封装体400的制造方法的剖面示意图。
请参照图1A，提供一第一基底100，其具有一第一表面100a及与其相对的一第二表面100b，且具有至少一微电子元件(未绘示)设置于电子元件区110内。在一实施例中，第一基底100为一硅晶圆，以利于进行晶圆级封装制程。在一实施例中，微电子元件可包括一CMOS元件或一MEMS元件。在本实施例中，第一基底100具有多个导电垫120，其可邻近于第一表面100a。在一实施例中，导电垫120可为单层导电层或具有多层的导电层结构，且通过内连线结构(未绘示)而与电子元件区110内的微电子元件电性连接。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第一基底100的第一表面100a上形成一间隔层140，且在间隔层140上提供一第二基底200，以在第一基底100与第二基底200之间形成一空腔150。在本实施例中，间隔层140可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。在一实施例中，第二基底200可为一晶片而具有至少一CMOS元件或一MEMS元件位于其内，可通过在空腔150内形成金属柱(未绘示)，将第二基底200的CMOS元件或MEMS元件电性连接至第一基底100的电子元件区110内的微电子元件。在另一实施例中，第二基底200可包括一玻璃盖板或一硅盖板，其内不具有任何主动或被动元件。
请参照图1B，可通过模塑成型制程、印刷制程或其他适合的制程，在第一基底100的第一表面100a上形成一密封层220，以覆盖第二基底200及导电垫120。在一实施例中，密封层220可包括模塑成型材料、密封材料或其他适合的材料。
请参照图1C，将形成于第一基底100的第一表面100a上的密封层220作为承载基板，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在第一基底100内形成多个开口230。开口230从第二表面100b朝第一表面100a延伸，且分别暴露出每一导电垫120的表面的一部分。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第一基底100的第二表面100b上形成一绝缘层240，且延伸至第一基底100的开口230内。接着，可通过微影制程及蚀刻制程，去除开口230的底部上的绝缘层240，以暴露出导电垫120。在一实施例中，绝缘层240可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
请参照图1D，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在第一基底100的第二表面100b上形成图案化的重布线层260。重布线层260延伸至第一基底100的开口230的底部，且通过绝缘层240与第一基底100电性隔离并与暴露出的导电垫120直接接触，以电性连接至导电垫120。在一实施例中，重布线层260可包括铜、铝、金、铂或其他适合的导电材料。
请参照图1E，可通过沉积制程，在第一基底100的第二表面100b上形成绝缘层280，且填入第一基底100的开口230内，以覆盖重布线层260。接着，可通过微影制程及蚀刻制程，在绝缘层280内形成开口285，以暴露出位于第二表面100b上的重布线层260的一部分。在一实施例中，绝缘层280可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
请参照图1F，在绝缘层280上形成导电结构300(例如，焊球、凸块或导电柱)，且填入绝缘层280的开口285，以与图案化的重布线层260电性连接。举例来说，可通过电镀制程、网版印刷制程或其他适合的制程，在绝缘层280的开口285内形成焊料(solder)，且进行回焊(reflow)制程，以形成导电结构300。在一实施例中，导电结构300可包括锡、铅、铜、金、镍、或前述的组合。接着，沿着切割道SC，切割第一基底100及密封层220，以形成多个独立的晶片封装体400。
在另一实施例中，可在形成密封层220之前，通过沉积制程，在第二基底200上形成一金属层320及至少一导线340。通过导线340将金属层320电性连接至导电垫120的其中一个(例如，接地垫)，以作为防止电磁干扰的屏蔽结构。接着，可通过类似于图1B至1F的实施例的晶片封装体的制造方法，依序形成密封层220、绝缘层240、重布线层260、绝缘层280及导电结构300，而完成晶片封装体500的制作，如图2所示。
以下配合图3A至3D说明本发明另一实施例的晶片封装体的制造方法。图3A至3D绘示出根据本发明另一实施例的晶片封装体600的制造方法的剖面示意图，其中相同于图1A至1F中的部件使用相同的标号并省略其说明。
请参照图3A，提供如图1A所示的结构。接着，请参照图3B，可通过模塑成型制程、印刷制程或其他适合的制程，在第一基底100的第一表面100a上形成一密封层220，以覆盖第二基底200及导电垫120。接着，将形成于第一基底100的第一表面100a上的密封层220作为承载基板，通过微影制程及蚀刻制程，在第一基底100内形成多个开口232。开口232从第二表面100b朝第一表面100a延伸，且分别暴露出每一导电垫120的表面的一部分。接着，可通过沉积制程，在第一基底100的第二表面100b上形成一绝缘层240，且延伸至第一基底100的开口232内。
请参照图3C，可通过激光钻孔制程、蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程)或其他适合的制程，将开口232自第一基底100延伸进入密封层220内而形成多个开口234。开口234从第二表面100b朝第一表面100a延伸，且分别暴露出每一导电垫120的一部分。举例来说，开口234延伸穿透开口232底部下方的绝缘层240及导电垫120，以延伸进入密封层220并暴露出导电垫120的内部。在另一实施例中，开口234可延伸至密封层220表面而未延伸进入其内。
接着，可通过沉积制程、微影制程及蚀刻制程，在第一基底100的第二表面100b上形成图案化的重布线层260，且自开口234延伸至密封层220内。在本实施例中，重布线层260通过绝缘层240与第一基底100电性隔离并与暴露出的导电垫120的内部直接接触，而以环型接触(ring-contact)的方式与导电垫120电性连接。在另一实施例中，开口234未延伸进入密封层220内且重布线层260可延伸至密封层220的表面上。
请参照图3D，可通过与图1E至1F相同或相似的步骤，依序形成绝缘层280及导电结构300。接着，沿着切割道SC，切割第一基底100及密封层220，以形成多个独立的晶片封装体600。
在另一实施例中，可在形成密封层220之前，通过沉积制程，在第二基底200上形成一金属层320及至少一导线340，且通过导线340将金属层320电性连接至导电垫120的其中一个(例如，接地垫)，以作为防止电磁干扰的屏蔽结构。接着，可通过类似于图3B至3D的实施例的晶片封装体的制造方法，依序形成密封层220、绝缘层240、重布线层260、绝缘层280及导电结构300，而完成晶片封装体700的制作，如图4所示。
以下配合图5A至5D说明本发明又另一实施例的晶片封装体的制造方法。图5A至5D绘示出根据本发明另一实施例的晶片封装体800的制造方法的剖面示意图，其中相同于图1A至1F中的部件使用相同的标号并省略其说明。
请参照图5A，提供如图1A所示的结构。接着，请参照图5B，可通过模塑成型制程、印刷制程或其他适合的制程，在第一基底100的第一表面100a上形成一密封层220，以覆盖第二基底200及导电垫120。接着，将形成于第一基底100的第一表面100a上的密封层220作为承载基板，通过微影制程及蚀刻制程，在第一基底100内形成多个开口236。开口236从第二表面100b朝第一表面100a延伸，且分别暴露出每一导电垫120的侧壁及表面的一部分。接着，可通过沉积制程，在第一基底100的第二表面100b上形成一绝缘层240，且延伸至第一基底100的开口236内。
请参照图5C，可通过部分切割(Partial dicing/Notch)或微影及蚀刻制程，在绝缘层240内形成多个开口238，以暴露出导电垫120的侧壁。在一实施例中，开口238延伸至密封层220内。接着，可通过沉积制程、微影制程及蚀刻制程，在第一基底100的第二表面100b上形成图案化的重布线层260，且自开口238延伸至密封层220内。在本实施例中，重布线层260通过绝缘层240与第一基底100电性隔离并与暴露出的导电垫120的侧壁直接接触，而以T型接触(T-contact)的方式与导电垫120电性连接。在另一实施例中，开口238未延伸进入密封层220内且重布线层260可延伸至密封层220的表面上。
请参照图5D，可通过沉积制程，在第一基底100的第二表面100b上形成绝缘层280，且填入绝缘层240的开口238内，以覆盖重布线层260。在一实施例中，绝缘层280填入密封层220内。接着，可通过与图1E至1F相同或相似的步骤，依序形成绝缘层280的开口285及导电结构300。接着，沿着切割道SC，切割第一基底100及密封层220，以形成多个独立的晶片封装体800。
在另一实施例中，可在形成密封层220之前，通过沉积制程，在第二基底200上形成一金属层320及至少一导线340，且通过导线340将金属层320电性连接至导电垫120的其中一个(例如，接地垫)，以作为防止电磁干扰的屏蔽结构。接着，可通过类似于图5B至5D的实施例的晶片封装体的制造方法，依序形成密封层220、绝缘层240、重布线层260、绝缘层280及导电结构300，而完成晶片封装体900的制作，如图6所示。
根据本发明的上述实施例，使用硅通孔电极、环型接触或T型接触作为晶片封装体的外部电性连接的路径，能够显著缩减晶片封装体的尺寸，且降低成本与制程时间。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (23)

1.一种晶片封装体，其特征在于，包括：
一第一基底，具有一第一表面及与该第一表面相对的一第二表面，其中该第一基底具有一微电子元件且具有邻近于该第一表面的多个导电垫，且该第一基底具有多个开口，所述开口分别暴露出每一导电垫的一部分；
一第二基底，设置于该第一表面上；
一密封层，设置于该第一表面上，且覆盖该第二基底；以及
一重布线层，设置于该第二表面上，且延伸至所述开口内，以与所述导电垫电性连接。
2.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一金属层，设置于该第二基底上；以及
一导线，将该金属层电性连接至所述导电垫的其中一个。
3.根据权利要求1所述的晶片封装体，其特征在于，所述开口还延伸穿透所述导电垫。
4.根据权利要求3所述的晶片封装体，其特征在于，所述开口还延伸至该密封层内。
5.根据权利要求3所述的晶片封装体，其特征在于，还包括：
一金属层，设置于该第二基底上；以及
一导线，将该金属层电性连接至所述导电垫的其中一个。
6.根据权利要求1所述的晶片封装体，其特征在于，所述开口分别暴露出每一导电垫的一侧壁。
7.根据权利要求6所述的晶片封装体，其特征在于，该重布线层还延伸至该密封层内。
8.根据权利要求6所述的晶片封装体，其特征在于，还包括：
一金属层，设置于该第二基底上；以及
一导线，将该金属层电性连接至所述导电垫的其中一个。
9.根据权利要求1所述的晶片封装体，其特征在于，该微电子元件包括一CMOS元件或一MEMS元件。
10.根据权利要求1所述的晶片封装体，其特征在于，该第二基底具有一CMOS元件或一MEMS元件。
11.根据权利要求1所述的晶片封装体，其特征在于，该第二基底包括一玻璃盖板或一硅盖板。
12.一种晶片封装体的制造方法，其特征在于，包括：
提供一第一基底，该第一基底具有一第一表面及与该第一表面相对的一第二表面，且该第一基底具有一微电子元件且具有邻近于该第一表面的多个导电垫；
在该第一表面上设置一第二基底；
在该第一表面上形成一密封层，以覆盖该第二基底；
在该第一基底内形成多个开口，所述开口分别暴露出每一导电垫的一部分；以及
在该第二表面上形成一重布线层，其中该重布线层延伸至所述开口内，以与所述导电垫电性连接。
13.根据权利要求12所述的晶片封装体的制造方法，其特征在于，还包括：
在该第二基底上形成一金属层；以及
形成一导线，该导线将该金属层电性连接至所述导电垫的其中一个。
14.根据权利要求12所述的晶片封装体的制造方法，其特征在于，所述开口还延伸穿透所述导电垫。
15.根据权利要求12所述的晶片封装体的制造方法，其特征在于，通过激光钻孔制程，形成所述开口。
16.根据权利要求14所述的晶片封装体的制造方法，其特征在于，所述开口还延伸至该密封层内。
17.根据权利要求14所述的晶片封装体的制造方法，其特征在于，还包括：
在该第二基底上形成一金属层；以及
形成一导线，该导线将该金属层电性连接至所述导电垫的其中一个。
18.根据权利要求12所述的晶片封装体的制造方法，其特征在于，所述开口分别暴露出所述导电垫的一侧壁。
19.根据权利要求18所述的晶片封装体的制造方法，其特征在于，该重布线层还延伸至该密封层内。
20.根据权利要求18所述的晶片封装体的制造方法，其特征在于，还包括：
在该第二基底上形成一金属层；以及
形成一导线，该导线将该金属层电性连接至所述导电垫的其中一个。
21.根据权利要求12所述的晶片封装体的制造方法，其特征在于，该微电子元件包括一CMOS元件或一MEMS元件。
22.根据权利要求12所述的晶片封装体的制造方法，其特征在于，该第二基底具有一CMOS元件或一MEMS元件。
23.根据权利要求12所述的晶片封装体的制造方法，其特征在于，该第二基底包括一玻璃盖板或一硅盖板。
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