TWI550802B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TWI550802B
TWI550802B TW103139866A TW103139866A TWI550802B TW I550802 B TWI550802 B TW I550802B TW 103139866 A TW103139866 A TW 103139866A TW 103139866 A TW103139866 A TW 103139866A TW I550802 B TWI550802 B TW I550802B
Authority
TW
Taiwan
Prior art keywords
substrate
chip package
layer
conductive pads
metal layer
Prior art date
Application number
TW103139866A
Other languages
English (en)
Other versions
TW201521171A (zh
Inventor
劉建宏
溫英男
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201521171A publication Critical patent/TW201521171A/zh
Application granted granted Critical
Publication of TWI550802B publication Critical patent/TWI550802B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0064—Packages or encapsulation for protecting against electromagnetic or electrostatic interferences
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝體及其製造方法，特別為有關於以晶圓級封裝製程所形成之晶片封裝體。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
製作晶片封裝體的過程包括將晶圓基底切割為複數晶片之後，將晶片放置於尺寸大於晶片的導線架(lead frame)上，接著透過金焊線將晶片上的導電墊電性連接至導線架的接合墊，以形成晶片的外部電性連接的路徑。
然而，由於使用金焊線及導線架作為外部電性連接的路徑，成本較高，且使得晶片封裝體的整體尺寸增加，因此難以進一步縮小晶片封裝體的尺寸。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一第一基底，具有一第一表面及與其相對的一第二表面，其中第一基底具有一微電子元件且具有複數導電墊鄰近於第一表面，且 其中第一基底具有複數開口，分別暴露出每一導電墊的一部分。一第二基底設置於第一表面上。一密封層設置於第一表面上，且覆蓋第二基底。一重佈線層設置於第二表面上，且延伸至開口內，以與導電墊電性連接。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一第一基底，其具有一第一表面及與其相對的一第二表面，其中第一基底具有一微電子元件且具有複數導電墊鄰近於第一表面。在第一表面上設置一第二基底。在第一表面上形成一密封層，以覆蓋第二基底。在第一基底內形成複數開口，分別暴露出每一導電墊的一部分。在第二表面上形成一重佈線層，其中重佈線層延伸至開口內，以與導電墊電性連接。
100‧‧‧第一基底
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧電子元件區
120‧‧‧導電墊
140‧‧‧間隔層
150‧‧‧空腔
200‧‧‧第二基底
220‧‧‧密封層
230、232、234、236、238、285‧‧‧開口
240、280‧‧‧絕緣層
260‧‧‧重佈線層
300‧‧‧導電結構
320‧‧‧金屬層
340‧‧‧導線
400、500、600、700、800、900‧‧‧晶片封裝體
SC‧‧‧切割道
第1A至1F圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2圖係繪示出根據本發明另一實施例之晶片封裝體的剖面示意圖。
第3A至3D圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖。
第4圖係繪示出根據本發明另一實施例之晶片封裝體的剖面示意圖。
第5A至5D圖係繪示出根據本發明又另一實施例之晶片封裝體的製造方法的剖面示意圖。
第6圖係繪示出根據本發明另一實施例之晶片封裝體的剖 面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參照第1F圖，其繪示出根據本發明一實施例之晶片封裝體400的剖面示意圖。在本實施例中，晶片封裝體400包括一第一基底100、一第二基底200、一密封層220及一重佈線層260。第一基底100具有一第一表面100a及與其相對的一第二表面100b，且具有至少一微電子元件(未繪示)設置於電子元件區110內。在一實施例中，第一基底100為一矽晶圓，以利於進行晶圓級封裝製程。在一實施例中，微電子元件可包括一互補式金屬氧化物半導體(complementary metal-oxide-semiconductor，CMOS)元件或一微機電系統(micro electro mechanical system，MEMS)元件。在本實施例中，第一基底100具有複數導電墊120，其可鄰近於第一表面100a，且第一基底100具有複數開口230，從第二表面100b朝第一表面100a延伸，且分別暴露出每一導電墊120的表面的一部分。在一實施例中，導電墊120可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與電子元件區110內的微電子 元件電性連接。
第二基底200可透過一間隔層(或稱作圍堰(dam))140設置於第一基底100的第一表面100a上。亦即，間隔層140設置於第一基底100與第二基底200之間。在一實施例中，第二基底200可為一晶片而具有至少一CMOS元件或一MEMS元件位於其內。設置於第一基底100與第二基底200之間的間隔層140在其間形成一空腔150，可透過在空腔150內形成金屬柱(未繪示)，將第二基底200的CMOS元件或MEMS元件電性連接至第一基底100的電子元件區110內的微電子元件。在另一實施例中，第二基底200可包括一玻璃蓋板或一矽蓋板，其內不具有任何主動或被動元件。在本實施例中，間隔層140可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。
密封層220設置於第一基底100的第一表面100a上，且覆蓋第二基底200及導電墊120，以提供晶片封裝體的保護。在一實施例中，密封層220可包括模塑成型材料(molding compound)、密封材料或其他適合的材料。
一絕緣層240設置於第一基底100的第二表面100b上，且延伸至第一基底100的開口230的側壁，而暴露出每一導電墊120的一部分。在一實施例中，絕緣層240可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化 物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
在本實施例中，重佈線層260設置於第一基底100的第二表面100b上，且延伸至第一基底100的開口230的底部。重佈線層260透過絕緣層240與第一基底100電性隔離並與暴露出的導電墊120直接接觸，以電性連接至導電墊120。因此，開口230內的重佈線層260也稱為矽通孔電極(through silicon via，TSV)。在一實施例中，重佈線層260可包括銅、鋁、金、鉑或其他適合的導電材料。
在本實施例中，晶片封裝體400更包括絕緣層280及導電結構300(例如，焊球、凸塊或導電柱)，設置於第一基底100的第二表面100b上。絕緣層280填入第一基底100的開口230內，以覆蓋重佈線層260且具有開口暴露出位於第二表面100b上的重佈線層260的一部分。在一實施例中，絕緣層280可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。導電結構300設置於絕緣層280上且填入絕緣層280的開口285，以與重佈線層260電性連接。在一實施例中，導電結構300可包括錫、鉛、銅、金、鎳、或前述之組合。
請參照第2圖，其繪示出根據本發明另一實施例之晶片封裝體500的剖面示意圖，其中相同於第1F圖中的部件係 使用相同的標號並省略其說明。第2圖中的晶片封裝體500之結構類似於第1F圖中的晶片封裝體400之結構，差異在於晶片封裝體500更包括一金屬層320，設置於第二基底200上，且透過至少一導線340將金屬層320電性連接至導電墊120的其中一者(例如，接地墊)，以作為防止電磁干擾(electromagnetic interference，EMI)的屏蔽結構。
請參照第3D圖，其繪示出根據本發明又另一實施例之晶片封裝體600的剖面示意圖，其中相同於第1F圖中的部件係使用相同的標號並省略其說明。在本實施例中，晶片封裝體600包括一第一基底100、一第二基底200、一密封層220及一重佈線層260。不同於第1F圖的晶片封裝體400，在本實施例中，第一基底100的開口234延伸穿透導電墊120至密封層220，以暴露出導電墊120的內部。
在另一實施例中，第一基底100的開口234未延伸至密封層220內。在本實施例中，絕緣層240設置於第一基底100的第二表面100b上，且延伸至第一基底100的開口234的側壁，而暴露出密封層220的一部分。
在本實施例中，重佈線層260設置於第一基底100的第二表面100b上，且延伸至第一基底100的開口234內。在一實施例中，重佈線層260更延伸至密封層220內。重佈線層260透過絕緣層240與第一基底100電性隔離並與暴露出的導電墊120的內部直接接觸，而以環型接觸(ring-contact)的方式電性連接至導電墊120。
請參照第4圖，其繪示出根據本發明另一實施例之 晶片封裝體700的剖面示意圖，其中相同於第3D圖中的部件係使用相同的標號並省略其說明。第4圖中的晶片封裝體700之結構類似於第3D圖中的晶片封裝體600之結構，差異在於晶片封裝體700更包括一金屬層320，設置於第二基底200上，且至少一導線340將金屬層320電性連接至導電墊120的其中一者(例如，接地墊)，以作為防止電磁干擾的屏蔽結構。
請參照第5D圖，其繪示出根據本發明又另一實施例之晶片封裝體800的剖面示意圖，其中相同於第1F圖中的部件係使用相同的標號並省略其說明。在本實施例中，晶片封裝體800包括一第一基底100、一第二基底200、一密封層220及一重佈線層260。在本實施例中，絕緣層240具有複數開口238，暴露出導電墊120的側壁。在一實施例中，開口238延伸至密封層220內。
在本實施例中，重佈線層260設置於第一基底100的第二表面100b上，且延伸至絕緣層240的開口238內而不穿過第一基底100。重佈線層260透過絕緣層240與第一基底100電性隔離並與暴露出的導電墊120的側壁直接接觸，而以T型接觸(T-contact)的方式電性連接至導電墊120。在一實施例中，重佈線層260更延伸至密封層220內。
請參照第6圖，其繪示出根據本發明另一實施例之晶片封裝體900的剖面示意圖，其中相同於第5D圖中的部件係使用相同的標號並省略其說明。第6圖中的晶片封裝體900之結構類似於第5D圖中的晶片封裝體800之結構，差異在於晶片封裝體900更包括一金屬層320，設置於第二基底200上，且至少 一導線340將金屬層320電性連接至導電墊120的其中一者(例如，接地墊)，以作為防止電磁干擾的屏蔽結構。
根據本發明的上述實施例，由於使用矽通孔電極、環型接觸或T型接觸作為具有微電子元件之第一基底100的外部電性連接的路徑，而不需使用焊線及導線架，能夠節省成本，並使得晶片封裝體的尺寸能夠進一步縮小。再者，由於形成於第二基底200上的屏蔽結構可電性連接至第一基底100的導電墊120，而不需電性連接至導線架，因此額外形成上述屏蔽結構能夠得到防止電磁干擾的效果，而不會增加晶片封裝體的尺寸。另外，採用晶圓級製程來製作晶片封裝體，可大量生產晶片封裝體，進而降低成本並節省製程時間。
以下配合第1A至1F圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1F圖係繪示出根據本發明一實施例之晶片封裝體400的製造方法的剖面示意圖。
請參照第1A圖，提供一第一基底100，其具有一第一表面100a及與其相對的一第二表面100b，且具有至少一微電子元件(未繪示)設置於電子元件區110內。在一實施例中，第一基底100為一矽晶圓，以利於進行晶圓級封裝製程。在一實施例中，微電子元件可包括一CMOS元件或一MEMS元件。在本實施例中，第一基底100具有複數導電墊120，其可鄰近於第一表面100a。在一實施例中，導電墊120可為單層導電層或具有多層之導電層結構，且透過內連線結構(未繪示)而與電子元件區110內的微電子元件電性連接。
接著，可透過沉積製程(例如，塗佈製程、物理氣 相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一基底100的第一表面100a上形成一間隔層140，且在間隔層140上提供一第二基底200，以在第一基底100與第二基底200之間形成一空腔150。在本實施例中，間隔層140可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在一實施例中，第二基底200可為一晶片而具有至少一CMOS元件或一MEMS元件位於其內，可透過在空腔150內形成金屬柱(未繪示)，將第二基底200的CMOS元件或MEMS元件電性連接至第一基底100的電子元件區110內的微電子元件。在另一實施例中，第二基底200可包括一玻璃蓋板或一矽蓋板，其內不具有任何主動或被動元件。
請參照第1B圖，可透過模塑成型製程、印刷製程或其他適合的製程，在第一基底100的第一表面100a上形成一密封層220，以覆蓋第二基底200及導電墊120。在一實施例中，密封層220可包括模塑成型材料、密封材料或其他適合的材料。
請參照第1C圖，將形成於第一基底100的第一表面100a上的密封層220作為承載基板，透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在第一基底100內形成複數開口230。開口230從第二表面100b朝第一表面100a延伸，且分別暴露出每一導電墊120的表面的一部分。
接著，可透過沉積製程(例如，塗佈製程、物理氣 相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一基底100的第二表面100b上形成一絕緣層240，且延伸至第一基底100的開口230內。接著，可透過微影製程及蝕刻製程，去除開口230的底部上的絕緣層240，以暴露出導電墊120。在一實施例中，絕緣層240可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
請參照第1D圖，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在第一基底100的第二表面100b上形成圖案化的重佈線層260。重佈線層260延伸至第一基底100的開口230的底部，且透過絕緣層240與第一基底100電性隔離並與暴露出的導電墊120直接接觸，以電性連接至導電墊120。在一實施例中，重佈線層260可包括銅、鋁、金、鉑或其他適合的導電材料。
請參照第1E圖，可透過沉積製程，在第一基底100的第二表面100b上形成絕緣層280，且填入第一基底100的開口230內，以覆蓋重佈線層260。接著，可透過微影製程及蝕刻製程，在絕緣層280內形成開口285，以暴露出位於第二表面100b上的重佈線層260的一部分。在一實施例中，絕緣層280可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙 烯酸酯)或其他適合的絕緣材料。
請參照第1F圖，在絕緣層280上形成導電結構300(例如，焊球、凸塊或導電柱)，且填入絕緣層280的開口285，以與圖案化的重佈線層260電性連接。舉例來說，可透過電鍍製程、網版印刷製程或其他適合的製程，在絕緣層280的開口285內形成焊料(solder)，且進行迴焊(reflow)製程，以形成導電結構300。在一實施例中，導電結構300可包括錫、鉛、銅、金、鎳、或前述之組合。接著，沿著切割道SC，切割第一基底100及密封層220，以形成複數獨立的晶片封裝體400。
在另一實施例中，可在形成密封層220之前，透過沉積製程，在第二基底200上形成一金屬層320及至少一導線340。透過導線340將金屬層320電性連接至導電墊120的其中一者(例如，接地墊)，以作為防止電磁干擾的屏蔽結構。接著，可透過類似於第1B至1F圖的實施例之晶片封裝體的製造方法，依序形成密封層220、絕緣層240、重佈線層260、絕緣層280及導電結構300，而完成晶片封裝體500的製作，如第2圖所示。
以下配合第3A至3D圖說明本發明另一實施例之晶片封裝體的製造方法。第3A至3D圖係繪示出根據本發明另一實施例之晶片封裝體600的製造方法的剖面示意圖，其中相同於第1A至1F圖中的部件係使用相同的標號並省略其說明。
請參照第3A圖，提供如第1A圖所示之結構。接著，請參照第3B圖，可透過模塑成型製程、印刷製程或其他適合的製程，在第一基底100的第一表面100a上形成一密封層220，以 覆蓋第二基底200及導電墊120。接著，將形成於第一基底100的第一表面100a上的密封層220作為承載基板，透過微影製程及蝕刻製程，在第一基底100內形成複數開口232。開口232從第二表面100b朝第一表面100a延伸，且分別暴露出每一導電墊120的表面的一部分。接著，可透過沉積製程，在第一基底100的第二表面100b上形成一絕緣層240，且延伸至第一基底100的開口232內。
請參照第3C圖，可透過雷射鑽孔製程、蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程)或其他適合的製程，將開口232自第一基底100延伸進入密封層220內而形成複數開口234。開口234從第二表面100b朝第一表面100a延伸，且分別暴露出每一導電墊120的一部分。舉例來說，開口234延伸穿透開口232底部下方的絕緣層240及導電墊120，以延伸進入密封層220並暴露出導電墊120的內部。在另一實施例中，開口234可延伸至密封層220表面而未延伸進入其內。
接著，可透過沉積製程、微影製程及蝕刻製程，在第一基底100的第二表面100b上形成圖案化的重佈線層260，且自開口234延伸至密封層220內。在本實施例中，重佈線層260透過絕緣層240與第一基底100電性隔離並與暴露出的導電墊120的內部直接接觸，而以環型接觸(ring-contact)的方式與導電墊120電性連接。在另一實施例中，開口234未延伸進入密封層220內且重佈線層260可延伸至密封層220的表面上。
請參照第3D圖，可透過與第1E至1F圖相同或相似 之步驟，依序形成絕緣層280及導電結構300。接著，沿著切割道SC，切割第一基底100及密封層220，以形成複數獨立的晶片封裝體600。
在另一實施例中，可在形成密封層220之前，透過沉積製程，在第二基底200上形成一金屬層320及至少一導線340，且透過導線340將金屬層320電性連接至導電墊120的其中一者(例如，接地墊)，以作為防止電磁干擾的屏蔽結構。接著，可透過類似於第3B至3D圖的實施例之晶片封裝體的製造方法，依序形成密封層220、絕緣層240、重佈線層260、絕緣層280及導電結構300，而完成晶片封裝體700的製作，如第4圖所示。
以下配合第5A至5D圖說明本發明又另一實施例之晶片封裝體的製造方法。第5A至5D圖係繪示出根據本發明另一實施例之晶片封裝體800的製造方法的剖面示意圖，其中相同於第1A至1F圖中的部件係使用相同的標號並省略其說明。
請參照第5A圖，提供如第1A圖所示之結構。接著，請參照第5B圖，可透過模塑成型製程、印刷製程或其他適合的製程，在第一基底100的第一表面100a上形成一密封層220，以覆蓋第二基底200及導電墊120。接著，將形成於第一基底100的第一表面100a上的密封層220作為承載基板，透過微影製程及蝕刻製程，在第一基底100內形成複數開口236。開口236從第二表面100b朝第一表面100a延伸，且分別暴露出每一導電墊120的側壁及表面的一部分。接著，可透過沉積製程，在第一基底100的第二表面100b上形成一絕緣層240，且延伸至第一基 底100的開口236內。
請參照第5C圖，可透過部分切割(Partial dicing/Notch)或微影及蝕刻製程，在絕緣層240內形成複數開口238，以暴露出導電墊120的側壁。在一實施例中，開口238延伸至密封層220內。接著，可透過沉積製程、微影製程及蝕刻製程，在第一基底100的第二表面100b上形成圖案化的重佈線層260，且自開口238延伸至密封層220內。在本實施例中，重佈線層260透過絕緣層240與第一基底100電性隔離並與暴露出的導電墊120的側壁直接接觸，而以T型接觸(T-contact)的方式與導電墊120電性連接。在另一實施例中，開口238未延伸進入密封層220內且重佈線層260可延伸至密封層220的表面上。
請參照第5D圖，可透過沉積製程，在第一基底100的第二表面100b上形成絕緣層280，且填入絕緣層240的開口238內，以覆蓋重佈線層260。在一實施例中，絕緣層280填入密封層220內。接著，可透過與第1E至1F圖相同或相似之步驟，依序形成絕緣層280的開口285及導電結構300。接著，沿著切割道SC，切割第一基底100及密封層220，以形成複數獨立的晶片封裝體800。
在另一實施例中，可在形成密封層220之前，透過沉積製程，在第二基底200上形成一金屬層320及至少一導線340，且透過導線340將金屬層320電性連接至導電墊120的其中一者(例如，接地墊)，以作為防止電磁干擾的屏蔽結構。接著，可透過類似於第5B至5D圖的實施例之晶片封裝體的製造方法，依序形成密封層220、絕緣層240、重佈線層260、絕緣層 280及導電結構300，而完成晶片封裝體900的製作，如第6圖所示。
根據本發明的上述實施例，使用矽通孔電極、環型接觸或T型接觸作為晶片封裝體的外部電性連接的路徑，能夠顯著縮減晶片封裝體之尺寸，且降低成本與製程時間。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100‧‧‧第一基底
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧電子元件區
120‧‧‧導電墊
140‧‧‧間隔層
150‧‧‧空腔
200‧‧‧第二基底
220‧‧‧密封層
230‧‧‧開口
240、280‧‧‧絕緣層
260‧‧‧重佈線層
300‧‧‧導電結構
400‧‧‧晶片封裝體
SC‧‧‧切割道

Claims (23)

  1. 一種晶片封裝體，包括：一第一基底，具有一第一表面及與其相對的一第二表面，其中該第一基底具有一微電子元件且具有複數導電墊鄰近於該第一表面，且其中該第一基底具有複數開口，分別暴露出每一導電墊的一部分；一第二基底，設置於該第一表面上；一密封層，設置於該第一表面上，且覆蓋該第二基底；以及一重佈線層，設置於該第二表面上，且延伸至該等開口內，以與該等導電墊電性連接。
  2. 如申請專利範圍第1項所述之晶片封裝體，更包括：一金屬層，設置於該第二基底上；以及一導線，將該金屬層電性連接至該等導電墊的其中一者。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該等開口更延伸穿透該等導電墊。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該等開口更延伸至該密封層內。
  5. 如申請專利範圍第3項所述之晶片封裝體，更包括：一金屬層，設置於該第二基底上；以及一導線，將該金屬層電性連接至該等導電墊的其中一者。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該等開口分別暴露出每一導電墊的一側壁。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該重佈線層 更延伸至該密封層內。
  8. 如申請專利範圍第6項所述之晶片封裝體，更包括：一金屬層，設置於該第二基底上；以及一導線，將該金屬層電性連接至該等導電墊的其中一者。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該微電子元件包括一CMOS元件或一MEMS元件。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該第二基底具有一CMOS元件或一MEMS元件。
  11. 如申請專利範圍第1項所述之晶片封裝體，其中該第二基底包括一玻璃蓋板或一矽蓋板。
  12. 一種晶片封裝體的製造方法，包括：提供一第一基底，其具有一第一表面及與其相對的一第二表面，其中該第一基底具有一微電子元件且具有複數導電墊鄰近於該第一表面；在該第一表面上設置一第二基底；在該第一表面上形成一密封層，以覆蓋該第二基底；在該第一基底內形成複數開口，分別暴露出每一導電墊的一部分；以及在該第二表面上形成一重佈線層，其中該重佈線層延伸至該等開口內，以與該等導電墊電性連接。
  13. 如申請專利範圍第12項所述之晶片封裝體的製造方法，更包括：在該第二基底上形成一金屬層；以及形成一導線，將該金屬層電性連接至該等導電墊的其中一 者。
  14. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該等開口更延伸穿透該等導電墊。
  15. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中透過雷射鑽孔製程，形成該等開口。
  16. 如申請專利範圍第14項所述之晶片封裝體的製造方法，其中該等開口更延伸至該密封層內。
  17. 如申請專利範圍第14項所述之晶片封裝體的製造方法，更包括：在該第二基底上形成一金屬層；以及形成一導線，將該金屬層電性連接至該等導電墊的其中一者。
  18. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該等開口分別暴露出該等導電墊的一側壁。
  19. 如申請專利範圍第18項所述之晶片封裝體的製造方法，其中該重佈線層更延伸至該密封層內。
  20. 如申請專利範圍第18項所述之晶片封裝體的製造方法，更包括：在該第二基底上形成一金屬層；以及形成一導線，將該金屬層電性連接至該等導電墊的其中一者。
  21. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該微電子元件包括一CMOS元件或一MEMS元件。
  22. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其 中該第二基底具有一CMOS元件或一MEMS元件。
  23. 如申請專利範圍第12項所述之晶片封裝體的製造方法，其中該第二基底包括一玻璃蓋板或一矽蓋板。
TW103139866A 2013-11-18 2014-11-18 晶片封裝體及其製造方法 TWI550802B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361905470P 2013-11-18 2013-11-18

Publications (2)

Publication Number Publication Date
TW201521171A TW201521171A (zh) 2015-06-01
TWI550802B true TWI550802B (zh) 2016-09-21

Family

ID=53172469

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103139866A TWI550802B (zh) 2013-11-18 2014-11-18 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (1) US9177919B2 (zh)
CN (1) CN104733422B (zh)
TW (1) TWI550802B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014202220B3 (de) * 2013-12-03 2015-05-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung eines Deckelsubstrats und gehäustes strahlungsemittierendes Bauelement
TWI546913B (zh) * 2014-04-02 2016-08-21 精材科技股份有限公司 晶片封裝體及其製造方法
KR20160090972A (ko) * 2015-01-22 2016-08-02 에스케이하이닉스 주식회사 이미지 센서 패키지 및 제조 방법
TWI600125B (zh) * 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI585870B (zh) * 2015-05-20 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
US10131535B2 (en) * 2015-05-22 2018-11-20 Honeywell International Inc. Monolithic fabrication of thermally isolated microelectromechanical system (MEMS) devices
US9741617B2 (en) 2015-11-16 2017-08-22 Amkor Technology, Inc. Encapsulated semiconductor package and method of manufacturing thereof
US20170256496A1 (en) * 2016-03-01 2017-09-07 Xintec Inc. Chip package and method for forming the same
US9960102B2 (en) * 2016-06-13 2018-05-01 Advanced Semiconductor Engineering, Inc. Semiconductor devices and methods of manufacturing the same
US10163813B2 (en) * 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US10005660B1 (en) * 2017-02-15 2018-06-26 Advanced Semiconductor Engineering, Inc. Semiconductor package device including microelectromechanical system
US10269728B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with shielding structure for cross-talk reduction
DE102018109028B4 (de) 2017-06-30 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Abschirmstruktur zur Verringerung von Übersprechen und Verfahren zur Herstellung derselben
CN110723712B (zh) * 2019-10-18 2024-02-13 中国航空工业集团公司西安飞行自动控制研究所 一种mems器件结构及制造方法
JP7433020B2 (ja) * 2019-11-07 2024-02-19 ローム株式会社 チップ部品およびその製造方法
US20230081775A1 (en) * 2021-09-10 2023-03-16 Xintec Inc. Chip package and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200509331A (en) * 2003-08-28 2005-03-01 Advanced Semiconductor Eng Semiconductor chip package and method for making the same
TW200830499A (en) * 2007-01-03 2008-07-16 Advanced Chip Eng Tech Inc Wafer level package with die receiving through-hole and method of the same
TW201250955A (en) * 2011-06-03 2012-12-16 Taiwan Semiconductor Mfg Interposer structure and semiconductor package structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100495699C (zh) * 2007-06-14 2009-06-03 日月光半导体制造股份有限公司 具有电磁屏蔽功能的半导体封装结构及其制造方法
TWI446500B (zh) * 2011-01-27 2014-07-21 Xintec Inc 晶片封裝體及其形成方法
CN102891120B (zh) * 2011-07-22 2016-06-08 精材科技股份有限公司 晶片封装体及其形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200509331A (en) * 2003-08-28 2005-03-01 Advanced Semiconductor Eng Semiconductor chip package and method for making the same
TW200830499A (en) * 2007-01-03 2008-07-16 Advanced Chip Eng Tech Inc Wafer level package with die receiving through-hole and method of the same
TW201250955A (en) * 2011-06-03 2012-12-16 Taiwan Semiconductor Mfg Interposer structure and semiconductor package structure

Also Published As

Publication number Publication date
CN104733422B (zh) 2017-12-26
TW201521171A (zh) 2015-06-01
CN104733422A (zh) 2015-06-24
US9177919B2 (en) 2015-11-03
US20150137341A1 (en) 2015-05-21

Similar Documents

Publication Publication Date Title
TWI550802B (zh) 晶片封裝體及其製造方法
TWI597813B (zh) 晶片封裝體及其製造方法
TWI565015B (zh) 晶片封裝體及其製造方法
TWI512930B (zh) 晶片封裝體及其形成方法
TWI647799B (zh) 半導體封裝及其製造方法
TWI525758B (zh) 晶片封裝體及其製造方法
TWI686907B (zh) 半導體封裝與其製造方法
TWI529892B (zh) 晶片封裝體及其製造方法
TWI569400B (zh) 晶片封裝體及其形成方法
US9337097B2 (en) Chip package and method for forming the same
TWI529821B (zh) 晶片封裝體及其形成方法
CN107221540B (zh) 晶片封装体及其制造方法
TW201543641A (zh) 晶片封裝體及其製造方法
US8674518B2 (en) Chip package and method for forming the same
TWI578411B (zh) 晶片封裝體的製造方法
TWI546913B (zh) 晶片封裝體及其製造方法
TWI717846B (zh) 晶片封裝體及其製造方法
TW201541586A (zh) 晶片堆疊封裝體及其製造方法
US20120193786A1 (en) Chip package and method for forming the same
US20150325551A1 (en) Chip package and method for forming the same
TWI549202B (zh) 晶片封裝體及其製造方法
TWI511266B (zh) 晶片封裝體及其形成方法
TWI543333B (zh) 晶片封裝體及其製造方法