TW201804577A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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TW201804577A
TW201804577A TW105132995A TW105132995A TW201804577A TW 201804577 A TW201804577 A TW 201804577A TW 105132995 A TW105132995 A TW 105132995A TW 105132995 A TW105132995 A TW 105132995A TW 201804577 A TW201804577 A TW 201804577A
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Taiwan
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layer
die
circuit layer
redistribution circuit
metal ring
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TW105132995A
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TWI686907B (zh
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黃育智
陳志華
林志偉
蔡豪益
陳玉芬
鄭余任
戴志軒
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台灣積體電路製造股份有限公司
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
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Abstract

一種半導體封裝，其包括模封半導體裝置、第一重佈線路層、第二重佈線路層及多個層間導通孔。模封半導體裝置包括晶粒。第一重佈線路層設置於模封半導體裝置的第一側。第二重佈線路層設置於模封半導體裝置的相對第一側的第二側，其中第二重佈線路層包括圖案化金屬層以及金屬環。圖案化金屬層具有電性連接至晶粒的連接線路部。金屬環圍繞連接線路部並與連接線路部分離。層間導通孔連接至金屬環的一部分且位於金屬環的下方。層間導通孔延伸穿過模封半導體裝置，以電性連接第一重佈線路層及第二重佈線路層。

Description

半導體封裝
本發明實施例是有關於一種半導體結構，且特別是有關於一種半導體封裝。
半導體元件用於多種電子應用上，像是個人電腦、手機、數位相機以及其他電子設備。半導體元件通常藉由在半導體基底上依序沈積絕緣層或介電層、導體層以及半導體層或半導體材料，並使用微影法圖案化多種材料層以於半導體基底上形成線路組件以及構件來製備。許多積體電路通常被製造在單一個半導體晶圓上。可將所述晶圓（wafer）的晶粒（dies）在晶圓階段（wafer level）處理與封裝，且用於晶圓級封裝的各種技術業已開發。
本發明實施例提供一種半導體封裝，其包括一模封半導體裝置、一第一重佈線路層、一第二重佈線路層以及多個層間導通孔。模封半導體裝置包括一第一晶粒。第一重佈線路層設置於模封半導體裝置的一第一側。第二重佈線路層設置於模封半導體裝置的相對第一側的一第二側，其中第二重佈線路層包括一圖案化金屬層以及一金屬環。圖案化金屬層具有電性連接至第一晶粒的一連接線路部。金屬環圍繞連接線路部並與連接線路部分離。層間導通孔連接至金屬環的一部分且位於金屬環的下方。層間導通孔延伸穿過模封半導體裝置，以電性連接第一重佈線路層及第二重佈線路層。
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
此外，文中所述用語諸如「第一」、「第二」、「第三」、「第四」等，其在文中之使用主要是便於描述圖中所示相似或不同的元件或特徵，並且可以根據敘述出現的順序或上下文的描述而相互調換使用。
圖1是依照本揭露的一些實施例的一種半導體封裝的剖面示意圖。圖2是圖1的半導體封裝的上視示意圖。圖3是圖2的半導體封裝的局部放大示意圖。請同時參考圖1至圖3，請參考圖1，在一些實施例中，半導體封裝100包括一模封半導體裝置110、一第一重佈線路層120、一第二重佈線路層130以及多個層間導通孔140。模封半導體裝置110包括一第一晶粒112以及一封裝膠體114。在一些實施例中，第一晶粒112包括具有多個電性接點112b的一主動表面112a以及相對於主動表面112a的一背面112c。在某些實施例中，第一晶粒112是模封於封裝膠體114且封裝膠體114至少包覆第一晶粒112的側面112d。在一些實施例中，第一重佈線路層120設置於模封半導體裝置110的一第一側S1。第二重佈線路層130設置於模封半導體裝置110的一第二側S2，且第二側S2相對第一側S1。也就是說，第一晶粒112是夾設於第一重佈線路層120以及第二重佈線路層130之間。換句話說，第一晶粒112以及封裝膠體114設置於第一重佈線路層120上，且第二重佈線路層130設置於第一晶粒112以及封裝膠體114上。在一些實施例中，第一重佈線路層120或第二重佈線路層130可包括一或多個圖案化金屬層以及一或多個聚合物基介電層（polymer-based dielectric layers）。聚合物基介電層的材料包括聚醯亞胺（polyimide, PI）、苯環丁烷（benzocyclobutene, BCB）、聚苯並噁唑（polybenzooxazole, PBO）或任何其他適合的聚合物基介電材料。如圖2及圖3所示，在某些實施例中，第二重佈線路層130包括至少一圖案化金屬層131，其包括一連接線路部132、一金屬環134以及選擇性設置的一密封環150。
在一些實施例中，第一晶粒112的主動表面112a背離第一重佈線路層120（意即，第一晶粒112圖1所示之面向上），且第一晶粒112的背面112c接觸第一重佈線路層120。第一晶粒112並未接觸層間導通孔140。在一些實施例中，層間導通孔140延伸穿過模封半導體裝置110以電性連接第一重佈線路層120以及第二重佈線路層130。具體而言，被模封半導體裝置110的封裝膠體114所暴露的層間導通孔140的兩端會電性連接第一重佈線路層120以及第二重佈線路層130。
在一些實施例中，層間導通孔140形成於第一重佈線路層120的多個被暴露的通孔128a上，且層間導通孔140直接連接第一重佈線路層120的通孔128a。在一些實施例中，層間導通孔140為貫穿整合扇出型通孔(through integrated InFO vias)。在某些實施例中，第一重佈線路層120的通孔128a的位置實質上對準或至少部分重疊於層間導通孔140的位置。在一些實施例中，由於層間導通孔140直接連接至第一重佈線路層140的通孔128a，可為晶粒建立較短的電性連接路徑，因而減少半導體封裝100的高度並增進半導體封裝100的電性表現。在一些實施例中，層間導通孔140可經由下列步驟而形成：形成具有多個開口的罩幕圖案（未繪示），其開口分別暴露第一重佈線路層120的通孔128a，並經由電鍍或沉積而形成一金屬材料，使其填充於開口以形成層間導通孔140，之後再移除罩幕圖案。在某些實施例中，層間導通孔140形成於第一重佈線路層120上，並配置於第一晶粒112旁且沿著第一晶粒112的周邊配置，使其不會妨礙第一晶粒112的感測區域。層間導通孔140可依據產品設計而配置於晶粒之間的位置。
在一些實施例中，在第一重佈線路層120上的第一晶粒112以及層間導通孔140被模封於封裝膠體114內。在一些實施例中，封裝膠體114填充於第一晶粒112以及層間導通孔140之間的間隙並覆蓋第一重佈線路層120。在一些實施例中，封裝膠體114形成於第一晶粒112上並覆蓋第一晶粒112的主動表面112a。在一些實施例中，封裝膠體114如圖1所示之至少包覆第一晶粒112的側面112d且暴露第一晶粒112的主動表面112a。舉例而言，封裝膠體114包括環氧樹脂或其他適合的模封材料。在某些實施例中，層間導通孔140更可包括阻障層（未繪示），其位於層間導通孔140與封裝膠體114之間。
在一些實施例中，半導體封裝100更可包括一或多個電性端子160、170，其位於第一重佈線路層120的最上層的圖案化線路層124的接墊124a、124b。電性端子160、170的數量及配置可依據佈局或佈線而調整。在一些實施例中，電性端子160可例如為焊球或是球柵陣列（ball grid array，BGA），其設置於接墊124a、124b上且被第一重佈線路層120的最上層的圖案化線路層124所暴露，而電性端子160下方的接墊124a、124b可作為焊球墊（ball pads）之用。在一些實施例中，電性端子170可例如為用以電性連接另一晶粒180的凸塊，且晶粒180更可包括例如積體被動裝置（integrated passive devices）的其他電子裝置。
在替代實施例中，半導體封裝100更可包括額外的晶粒，其設置於第一晶粒112上及/或第一晶粒112旁，且連接結構可調整以電性連接額外的晶粒。本揭露的結構不受限於僅包括第一晶粒112及第二晶粒180。
請參照圖1、圖2及圖3，在一些實施例中，第二重佈線路層130的連接線路部132如圖1所示之電性連接至第一晶粒112的電性接點112b。在一些實施例中，金屬環134圍繞連接線路部132並與連接線路部132電性絕緣，而密封環150則圍繞金屬環134及連接線路部132並與金屬環134及連接線路部132電性絕緣。詳細而言，在某些實施例中，既然密封環150、金屬環134及連接線路部132是由同一金屬層所形成且同為圖案化金屬層131的一部分，密封環150及金屬環134與連接線路部132延伸於同一水平面。具體而言，在一些實施例中，圖案化金屬層131更包括環繞連接線路部132的一溝槽G1，以定義出連接線路部132及金屬環134，並將金屬環134與連接線路部132分離。在一些實施例中，圖案化金屬層131更包括環繞金屬環134的一溝槽G2，以定義出金屬環134以及密封環150，並使金屬環134與密封環150隔離。層間導通孔140位於金屬環134的正下方，以增進空間利用率並降低封裝結構100的尺寸。
在一些實施例中，圖案化金屬層113更包括至少一第一接墊部134a及至少一第二接墊部134b，其位於金屬環134的跨度區域（span region）內。在一些實施例中，第一接墊部134a與金屬環134連接，且第二接墊部134b與金屬環134隔離。在一些實施例中，層間導通孔140的至少其中之一（例如圖3所示的層間導通孔140a）連接至金屬環134的第一接墊部134a且電性連接至金屬環134。因此，層間導通孔140的至少其中之另一（例如圖3所示的層間導通孔140b）連接至第二連接部134b，並電性連接至連接線路部132。在某些實施例中，金屬環134是以一金屬網格的形式而形成，也就是說金屬環134可如圖3所示的包括多個開口135。相似地，在一些實施例中，連接線路部132包括多條連接線132a以及與連接線132a絕緣的一金屬網格圖案132b。在一些實施例中，至少一連接線132a與第二接墊部134b連接，使層間導通孔140b經由連接線132a及第二接墊部134b而電性連接至連接線路部132。金屬環134的金屬網格及金屬網格圖案132b可作為虛設網格（dummy mesh）之用，並用以減少連接線路部132及金屬環134上的應力，以防止連接線路部132及金屬環134產生翹曲（warpage）。
圖4是依照本揭露的一些實施例的一種半導體封裝的局放大示意圖。在替換實施例中，金屬環134可被塑形為如圖4所示的實心的金屬環，也就是沒有如圖3所示的多個開口。本揭露並不限制金屬環134的形成方式，只要其環繞並絕緣於連接線路部132即可。在某些實施例中，第一晶粒112可為包括一或多個感測裝置的感測晶片。在某些實施例中，第一晶粒112包括至少一指紋感測器，其例如為一光學指紋感測器、一電容指紋感測器或其他適合種類的感測器。在一些實施例中，第一晶粒112是一感測晶片且第二重佈線路層130是正面（front-side）重佈線路層，而第一晶粒112可偵測或感測光或訊號。然而，第一晶粒112可以是具有不同功能的其他種類的晶粒或晶片，以與產品的設計匹配。在某些實施例中，第一晶粒112包括一指紋感測器，且金屬環134經配置以作為電容觸控開關的驅動環之用，當一手指出現時，電容觸控開關啟動或關閉指紋感測器。
在一些實施例中，密封環150可選擇性地形成於模封半導體裝置110的封裝膠體114上並環繞金屬環134，其用以防止不要的水氣及活動離子汙染物穿透第二重佈線路層130及穿透半導體封裝100的側面而進入第一晶粒112的功能性線路區。並且，密封環150可增進半導體封裝100的結構補強，以防止第一晶粒112的運作可靠度下降。
圖5A至圖5F是圖1的半導體封裝的製造過程的各種階段的剖面示意圖。在圖1至圖3中所敘述的相同構件將使用相同標號，且相同構件的某些細節與敘述於此將不再贅述。在例示性實施例中，此半導體製造過程為晶圓級封裝製程的一部分。在一些實施例中，晶粒可表示為晶圓的多個晶粒，而單一個封裝可表示為由後續的半導體製造過程所獲得的多個半導體封裝。
請參照圖5A，在一些實施例中，提供一承載器200，其中承載器200可為用於半導體封裝100的製造過程的一玻璃承載器或其他適合的承載器。在其他實施例中，承載器200可塗佈一脫膠層（debond layer）。脫膠層的材料可以是任何材料，其適用於將承載器200從配置於其上的疊層脫離。接著，一第一重佈線路層120形成於承載器200上。在某些實施例中，形成第一重佈線路層120的步驟包括形成一介電層122於承載器200上，並形成且圖案化一金屬層（未繪示）於介電層122上，以形成圖案化金屬層124。在某些實施例中，圖案化金屬層124包括一或多個接墊124a、124b。在某些實施例中，圖案化金屬層124可由電鍍或沉積而形成。在某些實施例中，第一重佈線路層120的形成更包括形成一介電層126於圖案化金屬層124及介電層122上，再圖案化上述介電層126以暴露圖案化金屬層124並形成一圖案化金屬層128，其連接至暴露的圖案化金屬層124。
在某些實施例中，第一重佈線路層120可經由逐層堆疊介電層122、126及圖案化金屬層124、128而形成。意即，在一些實施例中，第一重佈線路層120可包括多過或少於上述的兩介電層122、126，亦可包括多過或少於如圖5A所示的兩個圖案化金屬層124、128。圖案化金屬層的數量及介電層的數量可分別依據半導體封裝100的佈線需求作調整。在一些實施例中，多個層間導通孔140形成於第一重佈線路層120上並電性連接至第一重佈線路層120。具體來說，在一些實施例中，層間導通孔140可形成於介電層126上且連接至圖案化金屬層128的通孔128a。在一些實施例中，層間導通孔140是透過電鍍、沉積或其他適合的方法而形成。
請參照圖5B，在一些實施例中，至少一第一晶粒112是設置於第一重佈線路層120。在例示性實施例中，第一晶粒112為一感測晶片，其包括一或多個感測裝置。在某些實施例中，第一晶粒112包括至少一指紋感測器，其例如為一光學指紋感測器、電容指紋感測器或其他適合種類的包括感光耦合元件（charge coupled devices, CCDs）的感測器。在一些實施例中，第一晶粒112設置於第一重佈線路層120，以使第一晶粒112的主動表面112a背離第一重佈線路層120（意即，面朝上）。如圖5B所示，第一晶粒112設置於介電層126上且第一晶粒112的背面112c與第一重佈線路層120的介電層126接觸。在一些實施例中，提供一晶粒貼合薄膜（未繪示）於第一晶粒112以及第一重佈線路層120之間。層間導通孔140配置於第一晶粒112旁並環繞第一晶粒112，且第一晶粒112遠離層間導通孔140而配置。
請參照圖5C，在一些實施例中，封裝膠體114形成於第一重佈線路層120上並包覆第一晶粒112及層間導通孔140。換句話說，第一重佈線路層120上的第一晶粒112及層間導通孔140模封於封裝膠體114內。在一些實施例中，封裝膠體114填充於第一晶粒112及層間導通孔140之間的間隙並覆蓋第一重佈線路層120。在一些實施例中，封裝膠體114形成於第一晶粒112上並覆蓋第一晶粒112的主動表面112a。
在一些實施例中，封裝膠體114可被平面化以暴露層間導通孔140。在一些實施例中，過度模封（over-molded）的封裝膠體114及層間導通孔140可被拋磨至第一晶粒112的電性接點112b被暴露出來。在一些實施例中，層間導通孔140的上表面、封裝膠體114以及第一晶粒112在處理過後變成實質上共平面。在一些實施例中，封裝膠體114及/或層間導通孔140透過一研磨製程或一化學機械拋光（chemical mechanical polishing, CMP）而被平面化。在研磨製程之後，可選擇性地執行一清潔步驟，例如清潔及移除由研磨步驟所產生的殘留物。然而，本揭露並不侷限於此，平面化步驟可經由任何適合的方法來執行。
請參照圖5D，第二重佈線路層130形成於封裝膠體114上並位於第一晶粒112上。在一些實施例中，第二重佈線路層130電性連接至層間導通孔140及第一晶粒112。層間導通孔140位於金屬環134的正下方並配置於金屬環134的跨度（跨度區域）內，以增進空間利用率以及降低半導體封裝100的尺寸。第二重佈線路層130的形成包括逐層地接續形成一圖案化第一介電層136、圖案化金屬層131以及一第二介電層138。形成第二重佈線路層130的方法相似於形成第一重佈線路層120的方法。
在某些實施例中，第一介電層是先形成於封裝膠體114以及第一晶粒112上，接著再圖案化以形成圖案化第一介電層136，其具有多個如圖5D所示的開口。上述開口暴露層間導通孔140及第一晶粒112的多個電性接點112b。在一些實施例中，一金屬層形成於圖案化第一介電層136上並填充上述的開口。接著，金屬層被圖案化以形成圖案化金屬層131，其包括如圖3所示的連接線路部132及金屬環134。在一些實施例中，連接線路部132電性連接至層間導通孔140並電性連接至第一晶粒112的電性接點112b。請參照圖3，在一些實施例中，金屬環134圍繞連接線路部132並與連接線路部132隔絕。在某些實施例中，既然連接線路部132及金屬環134是經由一個圖案化製程並由同一金屬層所形成，金屬環134與連接線路部132延伸於同一水平面。在一些實施例中，金屬層被圖案化以形成一溝槽G1，其環繞連接線路部132以定義出連接線路部132以及金屬環134，並隔絕金屬環134與連接線路部132。在一些實施例中，一第二介電層138接續形成以覆蓋圖案化第一介電層136以及圖案化金屬層131。
在某些實施例中，第二重佈線路層130可包括大於或少於上述的兩個介電層136、138以及大於或少於一圖案化金屬層131。在一些實施例中，由於連接線路部132以及金屬環134是由同一金屬層（圖案化金屬層131）所圖案化而得，連接線路層132及金屬環134與第二重佈線路層130位於同一水平面。也就是說，圖案化金屬層的數量以及介電層的數量可依據半導體封裝100的佈線需求而調整。在一些實施例中，金屬環134是以金屬網格的形式呈現，也就是說金屬環134可包括如圖3所示的多個開口135。在一些實施例中，連接線路部132可包括多個連接線132a以及與連接線132a絕緣的一金屬網格圖案132b。金屬環134的金屬網格以及金屬網格圖案132b可作為虛設網格，並用以降低連接線路部132及金屬環134上的應力，以防止連接線路部132及金屬環134產生翹曲。
圖6是依照本揭露的一些實施例的一種半導體封裝的剖面示意圖。請參照圖5D及圖6，在一些實施例中，如圖6所示之一保護層190可設置於第二重佈線路層130上，且保護層190接觸第二介電層138。在一些實施例中，保護層190例如包括一玻璃蓋體、一蓋板、一硬質塗料層或任何其他適合的保護膜。在一些實施例中，保護層190更包括一功能層，例如一偏振膜、一色膜、一抗反射層或一抗眩光層。在某些實施例中，保護層190至少允許特定訊號或某些波長的光通過。一適合的保護層110是基於產品的需求及設計而選擇的。在一些實施例中，如圖6所示的黏著層195可先設置於第二重佈線路層130或保護層190上，之後保護層190再設置於第二重佈線路層130上，以貼附於第二重佈線路層130。黏著層195例如包括一紫外線固化膠、一熱固化膠、一光固化膠或一光熱轉換（light-to-heat conversion, LTHC）膠或其他類似物，當然也可使用其他種類的黏著劑。此外，黏著層195也適於允許光或訊號通過。在某些實施例中，第一晶粒112包括至少一指紋感測器，且金屬環134經配置以作為電容觸控開關的驅動環之用，當一手指F1觸碰保護層190時，電容觸控開關啟動或關閉指紋感測器。如此，第一晶粒112可接收及偵測通過保護層190的訊號。
請參照圖5E，在一些實施例中，承載器200可自第一重佈線路層120脫離。在一些實施例中，半導體封裝100自承載器200上脫離，接著被翻面（上下翻轉）而設置於一治具300上。在一些實施例中，治具300可例如為一承載膠帶（carrier tape），但治具300也可為其他適合種類的承載器，其用以承載自承載器200上脫離的半導體封裝100。如圖5E所示，自承載器200上脫離的剩餘的結構被翻面，以使第一重佈線路層120的表面朝上而變成上表面，且圖案化金屬層124變成最上層的圖案化金屬層。接著，對介電層122進行圖案化以於第一重佈線路層120的介電層122上形成多個開口，且介電層122的開口暴露最上層的圖案化金屬層124的接墊124a。
請參照圖5F及圖6，在一些實施例中，多個電性端子160、170設置於被上述開口所暴露的圖案化金屬層124的接墊124a、124b上。在一些實施例中，第二晶粒180透過電性端子170而接合於第一重佈線路層120的上表面。在一些實施例中，電性端子160電性連接至第一重佈線路層120、第二重佈線路層130以及第一晶粒112。在一些實施例中，第二晶粒180電性連接至第一重佈線路層120並可電性連接至第一晶粒112。接著，在後續的製程中切割半導體封裝100並與治具300分離。在一些實施例中，上述的製造過程是晶圓級封裝製程的一部分，在切割製程之後可得到多個半導體封裝100。在一些實施例中，治具300可在切割製程之前即與半導體封裝100分離。
根據一些實施例，一種半導體封裝包括一模封半導體裝置、一第一重佈線路層、一第二重佈線路層以及多個層間導通孔。模封半導體裝置包括一第一晶粒。第一重佈線路層設置於模封半導體裝置的一第一側。第二重佈線路層設置於模封半導體裝置的相對第一側的一第二側，其中第二重佈線路層包括一圖案化金屬層以及一金屬環。圖案化金屬層具有電性連接至第一晶粒的一連接線路部。金屬環圍繞連接線路部並與連接線路部分離。層間導通孔連接至金屬環的一部分且位於金屬環的下方。層間導通孔延伸穿過模封半導體裝置，以電性連接第一重佈線路層及第二重佈線路層。
根據一些實施例，一種半導體封裝包括一第一重佈線路層、至少一第一晶粒、一封裝膠體、一第二重佈線路層以及多個層間導通孔。第一晶粒設置於並電性連接至第一重佈線路層。封裝膠體設置於第一重佈線路層上並至少包覆第一晶粒的側面。第二重佈線路層設置於封裝膠體以及第一晶粒上，且第二重佈線路層包括電性連接至第一晶粒的一連接線路層以及環繞連接線路層並與連接線路層電性隔離的金屬環。金屬環與連接線路層延伸於同一水平面上。層間導通孔位於金屬環的正下方並貫穿封裝膠體以電性連接第一重佈線路層以及第二重佈線路層。如此配置，可增進空間利用率並降低半導體封裝100的尺寸。
根據一些實施例，一種半導體封裝的製造方法包括下列步驟。提供一承載器。形成一第一重佈線路層於承載器上。形成多個層間導通孔於第一重佈線路層上，其中層間導通孔電性連接至第一重佈線路層。設置至少一第一晶粒於第一重佈線路層上。形成包覆第一晶粒及層間導通孔的一封裝膠體。形成一第二重佈線路層於封裝膠體及第一晶粒上。第二重佈線路層的形成包括形成一圖案化金屬層。圖案化金屬層具有電性連接至第一晶粒的一連接線路層以及環繞連接線路層並與連接線路層電性隔絕的一金屬環。將承載器自第一重佈線路層脫離。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露的精神和範圍內，當可作些許的更動與潤飾，故本揭露的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧半導體封裝
110‧‧‧模封半導體裝置
112‧‧‧第一晶粒
112a‧‧‧主動表面
112b‧‧‧電性接點
112c‧‧‧背面
112d‧‧‧側面
114‧‧‧封裝膠體
120‧‧‧第一重佈線路層
122、126‧‧‧介電層
124、128‧‧‧圖案化金屬層
124a、124b‧‧‧接墊
128a‧‧‧通孔
130‧‧‧第二重佈線路層
131‧‧‧圖案化金屬層
132‧‧‧連接線路部
132a‧‧‧連接線
132b‧‧‧金屬網格圖案
134‧‧‧金屬環
134a‧‧‧第一接墊部
134b‧‧‧第二接墊部
136‧‧‧圖案化第一介電層
138‧‧‧第二介電層
140‧‧‧層間導通孔
150‧‧‧密封環
160、170‧‧‧電性端子
180‧‧‧晶粒、第二晶粒
190‧‧‧保護層
195‧‧‧黏著層
200‧‧‧承載器
300‧‧‧治具
F1‧‧‧手指
G1、G2‧‧‧溝槽
S1‧‧‧第一側
S2‧‧‧第二側
圖1是依照本揭露的一些實施例的一種半導體封裝的剖面示意圖。 圖2是圖1的半導體封裝的上視示意圖。 圖3是圖2的半導體封裝的局部放大示意圖。 圖4是依照本揭露的一些實施例的一種半導體封裝的局放大示意圖。 圖5A至圖5F是圖1的半導體封裝的製造過程的各種階段的剖面示意圖。 圖6是依照本揭露的一些實施例的一種半導體封裝的剖面示意圖。
100‧‧‧半導體封裝
110‧‧‧模封半導體裝置
112‧‧‧第一晶粒
112a‧‧‧主動表面
112b‧‧‧電性接點
112c‧‧‧背面
112d‧‧‧側面
114‧‧‧封裝膠體
120‧‧‧第一重佈線路層
126‧‧‧介電層
124、128‧‧‧圖案化金屬層
124a、124b‧‧‧接墊
128a‧‧‧通孔
130‧‧‧第二重佈線路層
131‧‧‧圖案化金屬層
132‧‧‧連接線路部
134‧‧‧金屬環
134a‧‧‧第一接墊部
140‧‧‧層間導通孔
150‧‧‧密封環
160、170‧‧‧電性端子
180‧‧‧第二晶粒
S1‧‧‧第一側
S2‧‧‧第二側

Claims (1)

  1. 一種半導體封裝，包括： 一模封半導體裝置，包括一第一晶粒； 一第一重佈線路層，設置於該模封半導體裝置的一第一側； 一第二重佈線路層，設置於該模封半導體裝置的相對該第一側的一第二側，其中該第二重佈線路層包括一圖案化金屬層以及一金屬環，該圖案化金屬層具有電性連接至該第一晶粒的一連接線路部，該金屬環圍繞該連接線路部並與該連接線路部分離；以及 多個層間導通孔，連接至該金屬環的一部分且位於該金屬環的下方，該些層間導通孔延伸穿過該模封半導體裝置，以電性連接該第一重佈線路層及該第二重佈線路層。
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