TWI820794B - 晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構 - Google Patents

晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構 Download PDF

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TWI820794B
TWI820794B TW111126109A TW111126109A TWI820794B TW I820794 B TWI820794 B TW I820794B TW 111126109 A TW111126109 A TW 111126109A TW 111126109 A TW111126109 A TW 111126109A TW I820794 B TWI820794 B TW I820794B
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chip
layer
chip packaging
dielectric layer
packaging unit
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TW111126109A
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TW202404013A (zh
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于鴻祺
林俊榮
古瑞庭
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華東科技股份有限公司
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Priority to TW111126109A priority Critical patent/TWI820794B/zh
Priority to JP2023001962U priority patent/JP3243099U/ja
Priority to KR2020230001402U priority patent/KR20240000124U/ko
Priority to US18/220,245 priority patent/US20240021552A1/en
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Publication of TWI820794B publication Critical patent/TWI820794B/zh
Publication of TW202404013A publication Critical patent/TW202404013A/zh

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Abstract

一種晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構，其中該晶片封裝單元更係由一晶圓上進行一切割作業所分別切割形成，各該晶片封裝單元具有一晶片、一第一重佈線層（RDL，Redistribution Layer）及一第二重佈線層（RDL，Redistribution Layer）及至少一第一電路層，各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且位於該晶片之至少一第一側邊、該第一重佈線層之至少一第二側邊及該第二重佈線層之至少一第三側邊上；其中該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結，達成製程簡化及節省能源，以利於製造端降低成本。

Description

晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構
本發明係一種封裝結構，尤指一種由至少二晶片封裝單元所堆疊形成的封裝結構，其中各該晶片封裝單元具有一晶片、一第一重佈線層(RDL，Redistribution Layer)及一第二重佈線層(RDL，Redistribution Layer)及至少一第一電路層，各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且位於該晶片之至少一第一側邊、該第一重佈線層之至少一第二側邊及該第二重佈線層之至少一第三側邊上；其中各該晶片封裝單元之該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結，藉以實現封裝結構中的各該晶片封裝單元得藉由各該晶片封裝單元的表面或背面(相對於各該晶片封裝單元的表面)來對外電性連結。
在習知的晶片封裝結構中，具有一種能由晶片封裝結構的表面電性連結至晶片封裝結構的背面(即相對於表面)的雙層晶片封裝結構，藉以實現晶片封裝結構中的晶片得由晶片封裝結構的表面或背面來對外電性連結，增加產品的市場競爭力；此外，上述的晶片封裝結構係從一個晶圓上去分別切割而形成，即一個晶圓上有多個晶片封裝結構，其中各個晶片封裝結構都對應地位在晶圓的各個晶片作業區中。
上述習知的晶片封裝結構必須在晶片封裝結構的表面往背面貫穿出一矽穿孔(TSV，Through Silicon Via)，以在該矽穿孔內設有與晶片封裝 結構中晶片電性連結的連結線路，藉此實現晶片得藉由晶片封裝結構的表面或背面來對外電性連結的功效。然而，該矽穿孔的構成造成了製造端的製程增加，且晶片封裝結構一般具有金屬的結構層而硬度較硬，這使得該矽穿孔的構成需耗費較多能源，不利於製造端降低成本。此外，在晶圓上構成多個該矽穿孔需在晶圓上各個晶片作業區中進行，各個晶片封裝結構即位在各個晶片作業區內，即各個該矽穿孔的構成增加損傷各個晶片封裝結構內部線路的風險，使得各個晶片封裝結構內部線路的設計需要重新規劃，以迴避各個該矽穿孔的位置來避免損傷，導致製造端的成本增加。
因此，一種有效地解決習知晶片封裝結構之矽穿孔的構成造成了製造端的製程增加及能源耗費的問題，且不需要重新規劃晶片封裝結構內部線路的晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構，為目前相關產業之迫切期待者。
本發明之主要目的在於提供一種晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構，其中該晶片封裝單元更係由一晶圓上進行一切割作業所分別切割形成，各該晶片封裝單元具有一晶片、一第一重佈線層(RDL，Redistribution Layer)及一第二重佈線層(RDL，Redistribution Layer)及至少一第一電路層，各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且位於該晶片之至少一第一側邊、該第一重佈線層之至少一第二側邊及該第二重佈線層之至少一第三側邊上；其中該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結，有效地解決習知晶片封裝結構之矽 穿孔的構成造成了製造端的製程增加及能源耗費的問題，且不需要重新規劃晶片封裝結構內部線路。
為達成上述目的，本發明提供一種晶片封裝單元，該晶片封裝單元具有一第一表面及一第二表面相對於該第一表面，該晶片封裝單元包含一晶片、一第一重佈線層(RDL，Redistribution Layer)、一第二重佈線層(RDL，Redistribution Layer)及至少一第一電路層；其中該晶片具有一第三表面、一第四表面及至少一第一側邊，該第三表面上設有至少一晶墊(Die Pad)及至少一晶片保護層，該第四表面係相對於該第三表面；其中該第一重佈線層位於該晶片之該第三表面上，該第一重佈線層由該第三表面依序包含至少一第一介電層、至少一凸塊、至少一第三介電層、至少一第一導接線路及至少一第二側邊，其中各該第一介電層係對應地覆蓋設於該晶片之該第三表面上，且具有一表面及至少一凹槽，各該凹槽係與該晶片之各該晶墊位置對應；其中各該凸塊係設於各該第一介電層之各該凹槽內，且各該凸塊係電性連結地設於該晶片之各該晶墊上，其中各該第三介電層係設於各該第一介電層之該表面上，且具有一表面，其中各該第一導接線路係設於各該第一介電層之該表面上並與各該凸塊電性連結，且具有對外露出之一表面；其中該第二重佈線層(RDL，Redistribution Layer)位於該晶片之該第四表面上，該第二重佈線層由該第四表面依序包含至少一第二介電層、至少一第二導接線路及至少一第三側邊，其中各該第二介電層係對應地覆蓋設於該晶片之該第四表面上，且具有一表面，其中各該第二導接線路係設於各該第二介電層之該表面上，且具有對外露出之一表面；其中各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且各該第一電路層係位於該晶片之各該第一側邊、該第一重佈線層之各該第二 側邊及該第二重佈線層之各該第三側邊上；其中該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結；其中該晶片封裝單元更係由一晶圓上進行一切割作業所分別切割形成，該晶圓具有一第七表面及一第八表面相對於該第七表面，其中該晶圓上具有多個該晶片封裝單元陣列地相鄰排列，相鄰二各該晶片封裝單元之間具有一切割區，各該切割區上具有由該第七表面軸向貫穿至該第八表面的至少一導通孔，各該導通孔係位於各該晶片封裝單元之該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊的外緣處，各該導通孔內包含有一軸向連結線路，且各軸向連結線路係與各該晶片封裝單元之各該第一導接線路及各該第二導接線路電性連結，其中該切割作業為切割工具沿著該晶圓之各該切割區切割該晶圓，各該切割區上在切割後形成一寬徑小於各該切割區的切割道，且各該切割道形成的同時將一部分的各該導通孔及一部分的各該軸向連結線路一同切除，未被切除的一部分的各該軸向連結線路連同未被切除的一部分的各該導通孔保留在各該晶片封裝單元的外緣處並藉此構成各該晶片封裝單元之各該第一電路層，達成製程簡化及節省能源，以利於製造端降低成本。
在本發明一較佳實施例中，該第一重佈線層進一步包含至少一第一保護層，各該第一保護層係設於各該第一導接線路之該表面上。
在本發明一較佳實施例中，該第二重佈線層進一步包含至少一第二保護層，各該第二保護層係設於各該第二導接線路之該表面上。
在本發明一較佳實施例中，該第一重佈線層進一步包含至少一第五介電層，各該第五介電層係設於各該第三介電層之該表面上，各該第五介電層具有至少一第一開口供各該第一導接線路對外露出。
在本發明一較佳實施例中，該第二重佈線層進一步包含至少一第四介電層，各該第四介電層係設於各該第二介電層之該表面上，各該第四介電層具有至少一第二開口供各該第二導接線路對外露出。
在本發明一較佳實施例中，該第一重佈線層進一步包含至少一第一錫球，各該第一錫球係設於各該第五介電層之各該第一開口上。
在本發明一較佳實施例中，該第二重佈線層進一步包含至少一第二錫球，各該第二錫球係設於各該第四介電層之各該二第開口上。
在本發明一較佳實施例中，該晶圓上的各該導通孔之孔徑進一步係大於各該切割道之寬徑。
本發明更提供一種晶片封裝單元之製造方法，該製造方法包含下列步驟：步驟S1：提供一晶圓，該晶圓具有一第七表面及一第八表面相對於該第七表面，且該晶圓上具有多個該晶片封裝單元陣列地相鄰排列，各該晶片封裝單元具有一晶片、一第一重佈線層(RDL，Redistribution Layer)及一第二重佈線層(RDL，Redistribution Layer)，其中各該晶片具有一第三表面、一第四表面及至少一第一側邊，該第三表面上設有至少一晶墊(Die Pad)及至少一晶片保護層，該第四表面係相對於該第三表面，其中各該第一重佈線層位於各該晶片之該第三表面上，各該第一重佈線層由該第三表面依序包含至少一第一介電層、至少一凸塊、至少一第三介電層、至少一第一導接線路及至少一第二側邊，其中各該第一介電層係對應地覆蓋設於各該晶片之該第三表面上，且具有一表面及至少一凹槽，各該凹槽係與各該晶片之各該晶墊位置對應，其中各該凸塊係設於各該第一介電層之各該凹槽內，且各該凸塊係電性連結地設於各該晶片之各該晶墊上，其中各該第三介電層係設於各該第一介電層之該表面上， 且具有一表面，其中各該第一導接線路係設於各該第一介電層之該表面上並與各該凸塊電性連結，且具有對外露出之一表面，其中各該第二重佈線層位於各該晶片之該第四表面上，各該第二重佈線層由該第四表面依序包含至少一第二介電層、至少一第二導接線路及至少一第三側邊，其中各該第二介電層係對應地覆蓋設於各該晶片之該第四表面上，且具有一表面，其中各該第二導接線路係設於各該第二介電層之該表面上，且具有對外露出之一表面，其中相鄰二各該晶片封裝單元之間具有一切割區，各該切割區上具有由該第七表面軸向貫穿至該第八表面的至少一導通孔，各該導通孔係位於各該晶片封裝單元之該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊的外緣處，各該導通孔內包含有一軸向連結線路，且各軸向連結線路係與各該晶片封裝單元之各該第一導接線路及各該第二導接線路電性連結；步驟S2：利用切割工具沿著該晶圓之各該切割區切割該晶圓，各該切割區上在切割後形成一寬徑小於各該切割區的切割道，且各該切割道形成的同時將一部分的各該導通孔及一部分的各該軸向連結線路一同切除，未被切除的一部分的各該軸向連結線路連同未被切除的一部分的各該導通孔保留在各該晶片封裝單元的外緣處並藉此構成各該晶片封裝單元之之至少第一電路層，其中各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且各該第一電路層係位於該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊上，其中該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結；及步驟S3：該晶圓切割完成後形成多個各該晶片封裝單元。
在本發明一較佳實施例中，在步驟S1之中進一步包含：各該晶片封裝單元的各該第一導接線路及各該第三介電層係同時將多餘的部分以線路研磨之技藝移除，以使各該第一導接線路之該表面與各該第三介電層之一表面齊平；其中各該晶片封裝單元的各該第二導接線路及各該第二介電層係同時將多餘的部分以線路研磨之技藝移除，以使各該第二導接線路之該表面與各該第二介電層之一表面齊平。
本發明更提供一種由晶片封裝單元所堆疊形成的封裝結構，該封裝結構包含至少一基板、至少一第二電路層、至少一第三導接線路、至少二晶片封裝單元及至少一絕緣層；其中各該基板具有一第五表面及相對之一第六表面，各該基板之該第五表面上成型設有至少一盲孔；其中各該第二電路層係設在各該基板之該第六面上並能延伸設在各該基板之各該盲孔之內壁面上；其中各該第三導接線路係電性連結地設於各該第二電路層上；其中各該晶片封裝單元係形成一上一下的對應關係而堆疊在一起，其中上一各該晶片封裝單元及下一各該晶片封裝單元之間係藉由至少一第四導接線路而互相電性連結，其中各該第四導接線路係電性連結地設於上一各該晶片封裝單元的各該第二導接線路上、及下一各該晶片封裝單元的各該第一導接線路上；其中各該絕緣層係設於各該基板上，且各該絕緣層係包覆各該晶片封裝單元；其中各該晶片封裝單元得藉由各該第二電路層向外電性連結。
在本發明一較佳實施例中，該封裝結構之底部進一步包含一底部外護層。
在本發明一較佳實施例中，該封裝結構之頂部進一步包含一頂部外護層。
在本發明一較佳實施例中，該封裝結構進一步係具有三個各該晶片封裝單元。
1:晶圓
1a:晶片封裝單元
1b:切割道
1c:導通孔
1d:切割區
1e:軸向連結線路
1f:第一表面
1g:第二表面
1h:第七表面
1i:第八表面
10:晶片
11:第三表面
12:第四表面
13:晶墊
14:晶片保護層
15:第一側邊
20:第一重佈線層
21:第一介電層
211:表面
212:凹槽
22:凸塊
23:第一導接線路
231:表面
24:第二側邊
25:第一錫球
26:第一保護層
27:第三介電層
271:表面
28:第五介電層
281:第一開口
30:第二重佈線層
31:第二介電層
311:表面
32:第二導接線路
321:表面
33:第三側邊
34:第二保護層
35:第四介電層
351:第二開口
36:第二錫球
40:第一電路層
50:基板
51:第五表面
52:第六表面
53:盲孔
60:第二電路層
70:第三導接線路
80:第四導接線路
90:絕緣層
100:底部外護層
110:頂部外護層
2:封裝結構
圖1為本發明之晶片封裝單元的側面剖視的平面示意圖。
圖2為本發明之晶圓的側面剖視的平面示意圖。
圖3為圖2的局部放大示意圖。
圖4為本發明之晶片封裝單元不包含錫球的側面剖視的平面示意圖。
圖5為本發明之晶圓的上視的平面示意圖。
圖6為圖5的局部放大示意圖。
圖7為本發明之晶片封裝單元(第一重佈線層以實線表示)的上視的平面示意圖。
圖8為本發明之晶片封裝單元(第二重佈線層以虛線表示)的上視的平面示意圖。
圖9為本發明之封裝結構的側面剖視的平面示意圖。
圖10為本發明之封裝結構具有三個晶片封裝單元的側面剖視的平面示意圖。
配合圖示，將本發明的結構及其技術特徵詳述如後，其中各圖示只用以說明本發明的結構關係及相關功能，因此各圖示中各元件的尺寸並非依實際比例畫製且非用以限制本發明。
參考圖1及4，本發明提供一種晶片封裝單元1a，該晶片封裝單元1a具有一第一表面1f及一第二表面1g相對於該第一表面1f，該晶片封裝單元1a包含一晶片10、一第一重佈線層(RDL，Redistribution Layer)20、一第二重佈線層(RDL，Redistribution Layer)30及至少一第一電路層40；其中所述重佈線層(RDL，Redistribution Layer)之技藝係一種運用於晶片封裝領域中的習知技術，重佈線層之技藝能製作出較高品質的精細線路而提升產品的良率，增加產品的市場競爭力，而且，重佈線層之技藝中一般採用高分子聚合物的材料(如薄膜材料)，以取代傳統的較厚之介質層或載板，有利於節省製造端成本，且能讓封裝結構厚度降低。
該晶片10具有一第三表面11、一第四表面12及至少一第一側邊15，該第三表面11上設有至少一晶墊(Die Pad)13及至少一晶片保護層14，該第四表面12係相對於該第三表面11如圖1及4所示。
該第一重佈線層20位於該晶片10之該第三表面11上，該第一重佈線層20由該第三表面11依序包含至少一第一介電層21、至少一凸塊22、至少一第三介電層27、至少一第一導接線路23及至少一第二側邊24如圖1及4所示，有利於節省製造端成本，且能讓封裝結構厚度降低；其中各該第一介電層21係對應地覆蓋設於該晶片10之該第三表面11上，且具有一表面211及至少一凹槽212，各該凹槽212係與該晶片10之各該晶墊13位置對應如圖1及4所示；其中各該凸塊22係設於各該第一介電層21之各該凹槽212內，且各該凸塊22係電性連結地設於該晶片10之各該晶墊13上；其中各該第三介電層27係設於各該第一介電層21之該表面211上，且具有一表面271如圖1及4所示；其中各該第一導接線路23係設於各該第一介電層21之該表面上211並與各該凸塊22電性連結，且具有對外露出之一表面231如圖1及4所示，藉以對外電性連結。
該第二重佈線層30位於該晶片10之該第四表面12上，該第二重佈線層30由該第四表面12依序包含至少一第二介電層31、至少一第二導接線路32及至少一第三側邊33如圖1及4所示，有利於節省製造端成本，且能讓封裝結構厚度降低；其中各該第二介電層31係對應地覆蓋設於該晶片10之該第四表面12上，且具有一表面311如圖1及4所示；其中各該第二導接線路32係設於各該第二介電層31之該表面311上，且具有對外露出之一表面321如圖1及4所示，藉以對外電性連結。
其中，參考圖1及4，該第一重佈線層20係相對地設於該第二重佈線層30另一面的對應關係但不限制，即當該第一重佈線層20位於該晶片封裝單元1a的表面(如該第一表面1f)上時如圖7所示，則該第二重佈線層30位於該晶片封裝單元1a的表面(如該第一表面1f)的另一面上如圖8所示。
各該第一電路層40係電性連結地設於各該第一導接線路23與各該第二導接線路32之間，且各該第一電路層40係位於該晶片10之各該第一側邊15、該第一重佈線層20之各該第二側邊24及該第二重佈線層30之各該第三側邊33上如圖1及4所示。
該晶片10得藉由各該第一導接線路23或各該第二導接線路32向外電性連結如圖1及4所示。
參考圖1及4，該第一重佈線層20進一步包含至少一第一保護層26但不限制，各該第一保護層26係設於各該第一導接線路23之該表面231上以增加產品的使用壽命。
參考圖1及4，該第二重佈線層30進一步包含至少一第二保護層34但不限制，各該第二保護層34係設於各該第二導接線路32之該表面321上以增加產品的使用壽命。
參考圖1及4，該第一重佈線層20進一步包含至少一第五介電層28但不限制，各該第五介電層28係設於各該第三介電層27之該表面271上，各該第五介電層28具有至少一第一開口281供各該第一導接線路23對外露出，藉以對外電性連結。
參考圖1及4，該第二重佈線層30進一步包含至少一第四介電層35，各該第四介電層35係設於各該第二介電層31之該表面311上，各該第四介電層35具有至少一第二開口351供各該第二導接線路32對外露出，藉以對外電性連結。
參考圖1，該第一重佈線層20進一步包含至少一第一錫球25但不限制，各該第一錫球25係設於各該第五介電層28之各該第一開口281上以供該晶片封裝單元1a藉各該第一錫球25與外部的電子元件電性連結地銲接在一起。
參考圖1，該第二重佈線層30進一步包含至少一第一錫球36但不限制，各該第二錫球36係設於各該第四介電層35之各該第二開口351上以供該晶片封裝單元1a藉各該第二錫球36與外部的電子元件電性連結地銲接在一起。
參考圖2至8，本發明更提供一種晶片封裝單元之製造方法，其包含下列步驟：
步驟S1：提供一晶圓1，該晶圓1具有一第七表面1h及一第八表面1i相對於該第七表面1h(如圖2所示)，且該晶圓1上具有多個該晶片封裝單元1a陣列地相鄰排列(如圖5所示)，各該晶片封裝單元1a具有一晶片10、一第一重佈線層(RDL，Redistribution Layer)20及一第二重佈線層(RDL，Redistribution Layer)30(如圖4所示)；其中各該晶片10具有一第三表面11、一第四表面12及至少一第一側邊15，該第三表面11上設有至少一晶墊(Die Pad)13及至少一晶片保護層14，該第四表面12係相對於該第三表面11如圖4所示；其中各該第一重佈線層20位於各該晶片10之該第三表面11上，各該第一重佈線層20由該第三 表面11依序包含至少一第一介電層21、至少一凸塊22、至少一第三介電層27、至少一第一導接線路23及至少一第二側邊24，其中各該第一介電層21係對應地覆蓋設於各該晶片10之該第三表面11上，且具有一表面211及至少一凹槽212，各該凹槽212係與各該晶片10之各該晶墊13位置對應，其中各該凸塊22係設於各該第一介電層21之各該凹槽212內，且各該凸塊22係電性連結地設於各該晶片10之各該晶墊13上，其中各該第三介電層27係設於各該第一介電層21之該表面211上，且具有一表面271，其中各該第一導接線路23係設於各該第一介電層21之該表面上211並與各該凸塊22電性連結，且具有對外露出之一表面231如圖4所示；其中各該第二重佈線層30位於各該晶片10之該第四表面12上，各該第二重佈線層30由該第四表面12依序包含至少一第二介電層31、至少一第二導接線路32及至少一第三側邊33，其中各該第二介電層31係對應地覆蓋設於各該晶片10之該第四表面12上，且具有一表面311，其中各該第二導接線路32係設於各該第二介電層31之該表面311上，且具有對外露出之一表面321如圖4所示；其中相鄰二各該晶片封裝單元1a之間具有一切割區1d(如圖2、3及5所示)，各該切割區1d上具有由該第七表面1h軸向貫穿至該第八表面1i的至少一導通孔1c(如圖2及3所示)，各該導通孔1c係位於各該晶片封裝單元1a之該晶片10之各該第一側邊15、該第一重佈線層20之各該第二側邊24及該第二重佈線層30之各該第三側邊33的外緣處(如圖2及3所示)，各該導通孔1c內包含有一軸向連結線路1e(如圖2、3、5及6所示)，且各軸向連結線路1e係與各該晶片封裝單元1a之各該第一導接線路23及各該第二導接線路32電性連結(如圖2及3所示)。
步驟S2：利用切割工具(未圖示)沿著該晶圓1之各該切割區1d切割該晶圓1(如圖5及6所示)，各該切割區1d上在切割後形成一寬徑小於各該切割區1d的切割道1b(如圖2、3、5及6所示)，且各該切割道1b形成的同時將一部分的各該導通孔1c及一部分的各該軸向連結線路1e一同切除，未被切除的一 部分的各該軸向連結線路1e連同未被切除的一部分的各該導通孔1c保留在各該晶片封裝單元1a的外緣處並藉此構成各該晶片封裝單元1a之至少一第一電路層40(如圖4、7及8所示)，其中各該第一電路層40係電性連結地設於各該第一導接線路23與各該第二導接線路32之間，且各該第一電路層40係位於該晶片10之各該第一側邊15、該第一重佈線層20之各該第二側邊24及該第二重佈線層30之各該第三側邊33上(如圖4所示)，其中該晶片10得藉由各該第一導接線路23(如圖7所示)或各該第二導接線路32(如圖8所示)向外電性連結(如圖4所示)。
步驟S3：該晶圓1切割完成後形成多個各該晶片封裝單元1a。
其中，在步驟S1之中進一步包含：各該晶片封裝單元1a的各該第一導接線路23及各該第三介電層27係同時將多餘的部分以線路研磨之技藝移除，以使各該第一導接線路23之該表面231與各該第三介電層27之一表面272齊平但不限制(未圖示)，此為重佈線層(RDL，Redistribution Layer)之技藝技藝中常見之步驟，故在此不再贅述；其中各該晶片封裝單元1a的各該第二導接線路32及各該第二介電層31係同時將多餘的部分以線路研磨之技藝移除，以使各該第二導接線路32之該表面321與各該第二介電層31之一表面311齊平(未圖示)但不限制，此為重佈線層(RDL，Redistribution Layer)之技藝技藝中常見之步驟，故在此不再贅述。
參考圖3及6，該晶圓1上的各該導通孔1c之孔徑進一步係大於各該切割道1b之寬徑但不限制，以能在各該切割道1b形成的同時將一部分的各該導通孔1c及一部分的各該軸向連結線路1e一同保留，以利於減少製程。
參考圖9，本發明更提供一種由晶片封裝單元所堆疊形成的封裝結構2，該封裝結構2包含至少一基板50、至少一第二電路層60、至少一第三導接線路70、至少二個各該晶片封裝單元1a及至少一絕緣層90。
各該基板50具有一第五表面51及相對之一第六表面52，各該基板50之該第五表面51上成型設有至少一盲孔53如圖9所示。
各該第二電路層60係設在各該基板50之該第六面52上並能延伸設在各該基板50之各該盲孔53之內壁面上如圖9所示。
各該第三導接線路70係電性連結地設於各該第二電路層60上如圖9所示。
各該晶片封裝單元1a係形成一上一下的對應關係而堆疊在一起，其中上一各該晶片封裝單元1a及下一各該晶片封裝單元1a之間係藉由至少一第四導接線路80而互相電性連結，其中各該第四導接線路80係電性連結地設於上一各該晶片封裝單元1a的各該第二導接線路32上、及下一各該晶片封裝單元1a的各該第一導接線路23上如圖9所示。
各該絕緣層90係設於各該基板50上，且各該絕緣層90係包覆各該晶片封裝單元1a如圖9所示。
各該晶片封裝單元1a得藉由各該第二電路層60向外電性連結如圖9所示。
參考圖9，該封裝結構2之底部進一步包含一底部外護層100但不限制，以增加該封裝結構2的結構強度。
參考圖9，該封裝結構2之頂部進一步包含一頂部外護層110但不限制，以增加該封裝結構2的結構強度。
參考圖10，該封裝結構2進一步係具有三個各該晶片封裝單元1a但不限制，藉以增加總體運算的效能，以利於增加產品的市場競爭力。
本發明的該晶片封裝單元1a及其製造方法及由其所堆疊形成的該封裝結構2具有以下優點：
(1)本發明的該晶片封裝單元1a係由該晶圓1上進行該切割作業所分別切割形成，各該晶片封裝單元1a具有該晶片10、該第一重佈線層20及該第二重佈線層30及各該第一電路層40，各該第一電路層40係電性連結地設於各該第一導接線路23與各該第二導接線路32之間，且位於該晶片10之各該第一側邊15、該第一重佈線層20之各該第二側邊24及該第二重佈線層30之各該第三側邊33上；其中該晶片10得藉由各該第一導接線路23或各該第二導接線路32向外電性連結；其中該晶圓1上的相鄰二各該晶片封裝單元1a之間具有該切割區1d(如圖2、3及5所示)，各該切割區1d上具有由該第七表面1h軸向貫穿至該第八表面1i的各該導通孔1c(如圖2及3所示)，其中各該切割區1d不位在各該晶片封裝單元1a上，即各該切割區1d不位在該晶圓1之各個晶片作業區內，因此，各該導通孔1c的構成不會對各該晶片封裝單元1a本體造成損壞，有效地解決習知晶片封裝結構之矽穿孔(TSV，Through Silicon Via)的構成造成了製造端的製程增加及能源耗費的問題，且不需要重新規劃晶片封裝結構內部線路來迴避穿孔的構成，達成製程簡化及節省能源，以利於製造端降低成本。此外，目前人類所使用的能源大都仍取自大自然，大自然用以產生能源的材料並非都是取之不盡而用之不竭的，且部分產生能源的方式伴隨著污染，可知能源的使用與地球環境的保護息息相關，本發明因具備上述節省能源的功效，亦有利於地球環境的保護。
(2)本發明的該封裝結構2之各該晶片封裝單元1a係形成一上一下的對應關係而堆疊在一起，其中上一各該晶片封裝單元1a及下一各該晶片封裝單元1a之間係藉由至少一第四導接線路80而互相電性連結，其中各該第四導接線路80係電性連結地設於上一各該晶片封裝單元1a的各該第二導接線路32上、及下一各該晶片封裝單元1a的各該第一導接線路23上如圖9所示，藉此堆疊模式以形成該封裝結構2，以使各該晶片10之間能藉其中一各該晶片10對其他各 該晶片10進行指令操作，或藉各該晶片10之間的運算功能疊加而能加乘增加總體運算的效能，以利於晶片封裝產品面積能縮小化且降低製造端成本。
以上該僅為本發明的優選實施例，對本發明而言僅是說明性的，而非限制性的；本領域普通技術人員理解，在本發明權利要求所限定的精神和範圍內可對其進行許多改變，修改，甚至等效變更，但都將落入本發明的保護範圍內。
1a:晶片封裝單元
1f:第一表面
1g:第二表面
10:晶片
11:第三表面
12:第四表面
13:晶墊
14:晶片保護層
15:第一側邊
20:第一重佈線層
21:第一介電層
211:表面
212:凹槽
22:凸塊
23:第一導接線路
231:表面
24:第二側邊
25:第一錫球
26:第一保護層
27:第三介電層
271:表面
28:第五介電層
281:第一開口
30:第二重佈線層
31:第二介電層
311:表面
32:第二導接線路
321:表面
33:第三側邊
34:第二保護層
35:第四介電層
351:第二開口
36:第二錫球
40:第一電路層

Claims (14)

  1. 一種晶片封裝單元，該晶片封裝單元具有一第一表面及一第二表面相對於該第一表面，該晶片封裝單元包含：一晶片，其具有一第三表面、一第四表面及至少一第一側邊，該第三表面上設有至少一晶墊(Die Pad)及至少一晶片保護層，該第四表面係相對於該第三表面；一第一重佈線層(RDL，Redistribution Layer)，其位於該晶片之該第三表面上，該第一重佈線層由該第三表面依序包含至少一第一介電層、至少一凸塊、至少一第三介電層、至少一第一導接線路及至少一第二側邊；其中各該第一介電層係對應地覆蓋設於該晶片之該第三表面上，且具有一表面及至少一凹槽，各該凹槽係與該晶片之各該晶墊位置對應；其中各該凸塊係設於各該第一介電層之各該凹槽內，且各該凸塊係電性連結地設於該晶片之各該晶墊上；其中各該第三介電層係設於各該第一介電層之該表面上，且具有一表面；其中各該第一導接線路係設於各該第一介電層之該表面上並與各該凸塊電性連結，且具有對外露出之一表面；一第二重佈線層(RDL，Redistribution Layer)，其位於該晶片之該第四表面上，該第二重佈線層由該第四表面依序包含至少一第二介電層、至少一第二導接線路及至少一第三側邊；其中各該第二介電層係對應地覆蓋設於該晶片之該第四表面上，且具有一表面；其中各該第二導接線路係設於各該第二介電層之該表面上，且具有對外露出之一表面；及至少一第一電路層，各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且各該第一電路層係位於該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊上； 其中該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結；其中該晶片封裝單元更係由一晶圓上進行一切割作業所分別切割形成，該晶圓具有一第七表面及一第八表面相對於該第七表面；其中該晶圓上具有多個該晶片封裝單元陣列地相鄰排列，相鄰二各該晶片封裝單元之間具有一切割區，各該切割區上具有由該第七表面軸向貫穿至該第八表面的至少一導通孔，各該導通孔係位於各該晶片封裝單元之該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊的外緣處，各該導通孔內包含有一軸向連結線路，且各軸向連結線路係與各該晶片封裝單元之各該第一導接線路及各該第二導接線路電性連結；其中該切割作業為切割工具沿著該晶圓之各該切割區切割該晶圓，各該切割區上在切割後形成一寬徑小於各該切割區的切割道，且各該切割道形成的同時將一部分的各該導通孔及一部分的各該軸向連結線路一同切除，未被切除的一部分的各該軸向連結線路連同未被切除的一部分的各該導通孔保留在各該晶片封裝單元的外緣處並藉此構成各該晶片封裝單元之各該第一電路層。
  2. 如請求項1所述之晶片封裝單元，其中該第一重佈線層進一步包含至少一第一保護層，各該第一保護層係設於各該第一導接線路之該表面上。
  3. 如請求項1所述之晶片封裝單元，其中該第二重佈線層進一步包含至少一第二保護層，各該第二保護層係設於各該第二導接線路之該表面上。
  4. 如請求項1所述之晶片封裝單元，其中該第一重佈線層進一步包含至少一第五介電層，各該第五介電層係設於各該第三介電層之該表面上，各該第五介電層具有至少一第一開口供各該第一導接線路對外露出。
  5. 如請求項1所述之晶片封裝單元，其中該第二重佈線層進一步包含至少一第四介電層，各該第四介電層係設於各該第二介電層之該表面上，各該第四介電層具有至少一第二開口供各該第二導接線路對外露出。
  6. 如請求項4所述之晶片封裝單元，其中該第一重佈線層進一步包含至少一第一錫球，各該第一錫球係設於各該第五介電層之各該第一開口上。
  7. 如請求項5所述之晶片封裝單元，其中該第二重佈線層進一步包含至少一第二錫球，各該第二錫球係設於各該第四介電層之各該第二開口上。
  8. 如請求項1所述之晶片封裝單元，其中該晶圓上的各該導通孔之孔徑進一步係大於各該切割道之寬徑。
  9. 一種晶片封裝單元之製造方法，其包含下列步驟：步驟S1：提供一晶圓，該晶圓具有一第七表面及一第八表面相對於該第七表面，且該晶圓上具有多個該晶片封裝單元陣列地相鄰排列，各該晶片封裝單元具有一晶片、一第一重佈線層(RDL，Redistribution Layer)及一第二重佈線層(RDL，Redistribution Layer)；其中各該晶片具有一第三表面、一第四表面及至少一第一側邊，該第三表面上設有至少一晶墊(Die Pad)及至少一晶片保護層，該第四表面係相對於該第三表面；其中各該第一重佈線層位於各該晶片之該第三表面上，各該第一重佈線層由該第三表面依序包含至少一第一介電層、至少一凸塊、至少一第三介電層、至少一第一導接線路及至少一第二側邊，其中各該第一介電層係對應地覆蓋設於各該晶片之該第三表面上，且具有一表面及至少一凹槽，各該凹槽係與各該晶片之各該晶墊位置對應，其中各該凸塊係設於各該第一介電層之各該凹槽內，且各該凸塊係電性連結地設於各該晶片之各該晶墊上，其中各該第三介電層係設於各該第一介電層之該表面上，且具有一表面， 其中各該第一導接線路係設於各該第一介電層之該表面上並與各該凸塊電性連結，且具有對外露出之一表面；其中各該第二重佈線層位於各該晶片之該第四表面上，各該第二重佈線層由該第四表面依序包含至少一第二介電層、至少一第二導接線路及至少一第三側邊，其中各該第二介電層係對應地覆蓋設於各該晶片之該第四表面上，且具有一表面，其中各該第二導接線路係設於各該第二介電層之該表面上，且具有對外露出之一表面；其中相鄰二各該晶片封裝單元之間具有一切割區，各該切割區上具有由該第七表面軸向貫穿至該第八表面的至少一導通孔，各該導通孔係位於各該晶片封裝單元之該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊的外緣處，各該導通孔內包含有一軸向連結線路，且各軸向連結線路係與各該晶片封裝單元之各該第一導接線路及各該第二導接線路電性連結；步驟S2：利用切割工具沿著該晶圓之各該切割區切割該晶圓，各該切割區上在切割後形成一寬徑小於各該切割區的切割道，且各該切割道形成的同時將一部分的各該導通孔及一部分的各該軸向連結線路一同切除，未被切除的一部分的各該軸向連結線路連同未被切除的一部分的各該導通孔保留在各該晶片封裝單元的外緣處並藉此構成各該晶片封裝單元之至少第一電路層，其中各該第一電路層係電性連結地設於各該第一導接線路與各該第二導接線路之間，且各該第一電路層係位於該晶片之各該第一側邊、該第一重佈線層之各該第二側邊及該第二重佈線層之各該第三側邊上，其中該晶片得藉由各該第一導接線路或各該第二導接線路向外電性連結；及步驟S3：該晶圓切割完成後形成多個各該晶片封裝單元。
  10. 如請求項9所述之製造方法，其中在步驟S1之中進一步包含：各該晶片封裝單元的各該第一導接線路及各該第三介電層係同時將多餘的部分以線路研磨之技藝移除，以使各該第一導接線路之該表面與各該第三介電 層之一表面齊平；其中各該晶片封裝單元的各該第二導接線路及各該第二介電層係同時將多餘的部分以線路研磨之技藝移除，以使各該第二導接線路之該表面與各該第二介電層之一表面齊平。
  11. 一種由晶片封裝單元所堆疊形成的封裝結構，其包含：至少一基板，各該基板具有一第五表面及相對之一第六表面，各該基板之該第五表面上成型設有至少一盲孔；至少一第二電路層，各該第二電路層係設在各該基板之該第六面上並能延伸設在各該基板之各該盲孔之內壁面上；至少一第三導接線路，各該第三導接線路係電性連結地設於各該第二電路層上；至少二晶片封裝單元，各該晶片封裝單元係如申請專利範圍請求項1至請求項5中任一項所述的該晶片封裝單元，且各該晶片封裝單元係形成一上一下的對應關係而堆疊在一起，其中上一各該晶片封裝單元及下一各該晶片封裝單元之間係藉由至少一第四導接線路而互相電性連結，其中各該第四導接線路係電性連結地設於上一各該晶片封裝單元的各該第二導接線路上、及下一各該晶片封裝單元的各該第一導接線路上；及至少一絕緣層，各該絕緣層係設於各該基板上，且各該絕緣層係包覆各該晶片封裝單元；其中各該晶片封裝單元得藉由各該第二電路層向外電性連結。
  12. 如請求項11所述之封裝結構，其中該封裝結構之底部進一步包含一底部外護層。
  13. 如請求項11所述之封裝結構，其中該封裝結構之頂部進一步包含一頂部外護層。
  14. 如請求項11所述之封裝結構，其中該封裝結構進一步係具有三個各該晶片封裝單元。
TW111126109A 2022-07-12 2022-07-12 晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構 TWI820794B (zh)

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CN102956588A (zh) * 2011-08-09 2013-03-06 马克西姆综合产品公司 具有穿衬底通孔的半导体器件
TW201804577A (zh) * 2016-07-20 2018-02-01 台灣積體電路製造股份有限公司 半導體封裝
WO2019027278A1 (ko) * 2017-08-04 2019-02-07 주식회사 네패스 칩 패키지 및 그 제조방법
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CN102956588A (zh) * 2011-08-09 2013-03-06 马克西姆综合产品公司 具有穿衬底通孔的半导体器件
TW201804577A (zh) * 2016-07-20 2018-02-01 台灣積體電路製造股份有限公司 半導體封裝
WO2019027278A1 (ko) * 2017-08-04 2019-02-07 주식회사 네패스 칩 패키지 및 그 제조방법
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