TWI649848B - 具有凸塊下層金屬的半導體結構及其製作方法 - Google Patents

具有凸塊下層金屬的半導體結構及其製作方法 Download PDF

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TWI649848B
TWI649848B TW103145829A TW103145829A TWI649848B TW I649848 B TWI649848 B TW I649848B TW 103145829 A TW103145829 A TW 103145829A TW 103145829 A TW103145829 A TW 103145829A TW I649848 B TWI649848 B TW I649848B
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Prior art keywords
metal
bump
pad
semiconductor structure
shallow trench
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TW103145829A
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TW201624652A (zh
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何凱光
王振孝
徐一峯
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聯華電子股份有限公司
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Priority to TW103145829A priority Critical patent/TWI649848B/zh
Priority to US14/609,412 priority patent/US9502366B2/en
Publication of TW201624652A publication Critical patent/TW201624652A/zh
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Publication of TWI649848B publication Critical patent/TWI649848B/zh

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Abstract

本發明提供一種具有凸塊下層金屬的半導體結構，半導體結構至少包含一基底、一金屬墊設於基底上、一絶緣層覆蓋基底以及覆蓋金屬墊之邊緣、至少一淺溝渠設於該絶緣層中和一第一凸塊下層金屬接觸金屬墊，前述淺溝渠鄰近金屬墊，並且淺溝渠為環狀，此外前述第一凸塊下層金屬貼覆部分之淺溝渠。

Description

具有凸塊下層金屬的半導體結構及其製作方法
本發明係關於一種具有凸塊下層金屬的半導體結構及其製作方法，尤其是關於一種避免凸塊下層金屬產生孔洞的結構及其製作方法。
在半導體封裝製程中，晶片朝尺寸小、高接腳數的趨勢發展，並漸漸由覆晶接合(Flip Chip bonding)的技術來取代打線接合(wire bonding)的技術。覆晶接合技術乃將多個金屬墊配置於晶片的主動表面(active surface)上，並在金屬墊上形成凸塊(bump)，接著將晶片翻覆之後，再利用這些凸塊分別電性連接至一線路載板，並經由線路載板的線路而電性連接至外界之電子裝置。在金屬墊上形成凸塊之前，必須金屬墊上在製作凸塊下層金屬(Under Bump Metallurgy,UBM)，凸塊下層金屬層可防止錫鉛凸塊與晶片的銲墊接合性不佳而脫離，然而傳統上製作凸塊下層金屬層的方法往往會在凸塊下層金屬和金屬墊之間產生孔洞，因而降低可靠度。
有鑑於此，本發明提供一種具有凸塊下層金屬的半導體結構的製作方法及其結構，以改善上述問題。
根據本發明之一較佳實施例，一種具有凸塊下層金屬的半導體結構，包含一基底，一金屬墊設於基底上，一絶緣層覆蓋基底以及覆蓋金屬墊之邊緣，至少一淺溝渠設於絶緣層中，淺溝渠鄰近金屬墊，並且淺溝渠為環狀，一第一凸塊下層金屬接觸金屬墊，並且第一凸塊下層金屬貼覆部分之淺溝渠。
根據本發明之另一較佳實施例，一種具有凸塊下層金屬的半導體結構的製作方法，包含首先提供一基底，然後形成一金屬墊於基底上，之後形成一絶緣層覆蓋基底和金屬墊，接著進行一第一圖案化步驟，移除部分之絶緣層，使得金屬墊由絶緣層曝露出來，接續進行一第二圖案化步驟，移除部分之絶緣層，以在絶緣層上形成至少一淺溝渠與金屬墊相鄰，並且淺溝渠為封閉環狀，最後形成一凸塊下層金屬接觸金屬墊並且填入部分之淺溝渠。
根據本發明之另一較佳實施例，一種具有凸塊下層金屬的半導體結構的製作方法，包含首先提供一基底，接著形成一金屬層覆蓋基底，然後圖案化金屬層，形成一金屬墊以及至少一金屬圈環繞金屬墊，其中金屬墊和金屬圈之間定義出一第一溝渠，之後形成一絶緣層順應地覆蓋基底、金屬墊、金屬圈和第一溝渠，部分之絶緣層形成一淺溝渠與第一溝渠重疊，接續圖案化絶緣層，曝露出金屬墊，最後形成一凸塊下層金屬接觸金屬墊並且填入部分之淺溝渠。
10‧‧‧基底
12‧‧‧金屬層
14‧‧‧金屬墊
16‧‧‧絶緣層
18‧‧‧淺渠溝
20‧‧‧側壁
22‧‧‧側壁
24‧‧‧底部
26‧‧‧第一凸塊下層金屬
28‧‧‧第二凸塊下層金屬
30‧‧‧金屬圈
32‧‧‧第一溝渠
34‧‧‧第二溝渠
100‧‧‧具有凸塊下層金屬的半導體結構
200‧‧‧具有凸塊下層金屬的半導體結構
300‧‧‧具有凸塊下層金屬的半導體結構
400‧‧‧具有凸塊下層金屬的半導體結構
第1圖至第7圖為根據本發明之第一較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法。
第8圖和第9圖為根據本發明之第二較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法。
第1圖、第10圖至第13圖繪示的是根據本發明之第三較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法。
第14圖和第15圖為根據本發明之第四較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法。
第1圖至第7圖為根據本發明之第一較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法，其中第4圖為第5圖沿切線AA’的剖 面示意圖，第6圖為第7圖沿切線BB’的剖面示意圖。如第1圖所示，提供一基底10。接著在基底10上全面形成一金屬層12，基底10可以包含已完成的金屬內連線，而金屬層12在後續圖案化之後會作為金屬銲墊(bonding pad)。此外基底10也可以為一中間介層(interposer)。根據本發明之較佳實施例，金屬層為鋁，但不限於此，其它具導電性質的材料亦可以使用。如第2圖所示，圖案化金屬層，形成一金屬墊14，前述的金屬墊14具有連續的輪廓。如第3圖所示，形成一絶緣層16順應地覆蓋基底10和金屬墊14，之後利用第一圖案化步驟，例如一微影暨蝕刻製程，移除部分的絶緣層16使得金屬墊14曝露出來，剩餘的絶緣層16可以選擇性地部分覆蓋金屬墊14。如第4圖和第5圖所示，接著進行第二圖案化步驟，例如另一微影暨蝕刻製程，在剩餘的絶緣層16上形成至少一淺溝渠18(在圖示中以粗線標示)，前述的淺渠溝18較佳為封閉環狀，並且淺渠溝18較佳形成在與金屬墊14相鄰的絶緣層16上，甚至是與金屬墊14邊緣重疊的絶緣層16上。如第5圖所示，淺渠溝18可以為矩形環狀，但不限於此，淺渠溝18亦可以為圓形環或八角形環等其它形狀。在蝕刻淺溝渠18時，必須控制淺溝渠18的深度，使得淺溝渠18完全由絶緣層16定義出來，也就是說淺溝渠18的側壁20/22、底部24都是由絶緣層16構成，如此可避免底下的金屬墊14由淺溝渠18曝露出來。根據本發明之較佳實施例，淺溝渠的深度d為約為0.1微米，其底部寬度W約為0.2微米。
如第6圖所示，形成一第一凸塊下層金屬26接觸金屬墊14並且由金屬墊14延伸至覆蓋部分之淺溝渠18，詳細來說淺溝渠18包含一底部24和二側壁20/22，第一凸塊下層金屬26貼覆其中之一的側壁22以及部分之底部24，又或者第一凸塊下層金屬26可以貼覆二個側壁20/22以及全部的底部24，根據本發明之較佳實施例，第一凸塊下層金屬26貼覆至少二分之一的淺溝渠18之底部寬度W。形成第一凸塊下層金屬26的方式可以利用傳統的無電鍍技術進行，例如使用適合的金屬鹽作為電鍍液，視情況需要可選擇性地 搭配還原劑進行無電鍍，在本發明中第一凸塊下層金屬26較佳為鎳。由於本發明額外製作了至少一個淺溝渠18，因此第一凸塊下層金屬26不僅會貼覆絶緣層16的上表面，更會延伸至淺溝渠18的側壁20/22以及底部24，使得第一凸塊下層金屬26和絶緣層16的接觸面積增加，另外，因為第一凸塊下層金屬26和絶緣層16物理性質的差異，所以第一凸塊下層金屬26和絶緣層16之間的貼附性會比金屬和金屬之間的貼附性差，而增加第一凸塊下層金屬26和絶緣層16的接觸面積則可以使第一凸塊下層金屬26較能夠附著在絶緣層16上。請再度參閱第6圖，第一凸塊下層金屬26為一完整且連續的金屬結構。在完成第一凸塊下層金屬26之後，形成一第二凸塊下層金屬28順應地貼覆第一凸塊下層金屬26，第二凸塊下層金屬28貼覆了部分的淺溝渠18底部24，同樣地，第二凸塊下層金屬28可以利用傳統的無電鍍技術進行，例如使用適合的金屬鹽作為電鍍液，視情況需要可選擇性地搭配還原劑進行無電鍍，在本發明中第二凸塊下層金屬28較佳為鈀，此外如第7圖所示，第二凸塊下層金屬28在淺溝渠18的環形中是連續的，因此被第二凸塊下層金屬28順應覆蓋的第一凸塊下層金屬26在淺溝渠18的環形中也是連續的，因此在淺溝渠18中的第一凸塊下層金屬26也形成了一個封閉環狀。接著同樣地利用無電鍍技術形成一第三凸塊下層金屬(圖未示)，第三凸塊下層金屬較佳為金，因此在形成第三凸塊下層金屬時，第二凸塊下層金屬28需浸泡在含金的金屬鹽溶液中，由於金的原子小，所以金原子容易經由鈀和絶緣層16的介面鑽入之後接觸到第一凸塊下層金屬26，例如鎳，接著金原子會和鎳反應使得第一凸塊下層金屬26和絶緣層16之間的介面形成孔洞，最後造成完成的凸塊下層金屬電性上的損害。然而由於本發明額外製作了至少一個淺溝渠18造成金原子要先通過淺溝渠18的底部24和側壁20/22才會到達第一凸塊下層金屬26會影響電性的部分，使得金原子進入不易，此外，就算在第一凸塊下層金屬26位在淺溝渠18的內的部分中形成孔洞，對後續完成的凸塊下層金屬電性也不會有影響。再者，在完成第三凸塊下層金屬之後，可以在第三 凸塊下層金屬上形成一錫鉛凸塊。
第8圖和第9圖為根據本發明之第二較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法，其中具有相同功能的元件將以相同的符號標示，第8圖為第9圖沿切線CC’的剖面示意圖，但為了圖示清楚，第9圖只標示出絶緣層16和金屬墊14的位置，其它元件則予以省略，請參閱第8圖和第9圖，和第一較佳實施例不同的地方在於：本發明之第二較佳實施例，在第二圖案化步驟時，係形成多個如第4圖和第5圖所示的環狀淺溝渠18，較遠離金屬墊14之淺溝渠18環繞較接近金屬墊14之淺溝渠18，每個淺 溝渠18都具有一底部24和兩側壁20/22，在後續利用無電鍍形成的第一凸塊下層金屬26貼覆至少一個底部20和一個側壁22，但最遠離金屬墊26之淺溝渠18的其中之一側壁20未被第一凸塊下層金屬26貼覆，又或者第一凸塊下層金屬26可以貼覆每個淺溝渠18的底部24和側壁20/22，在第二較佳實施例中，多個淺溝渠18更使得金原子需要沿著淺溝渠18的輪廓到達第一凸塊下層金屬26會影響電性的部分，也就是說金原子要到達影響電性的位置，其路徑被拉長，此外，就算在第一凸塊下層金屬26位在各個淺溝渠18的內的部分中形成孔洞，對後續完成的凸塊下層金屬電性也不會有影響。
第1圖、第10圖至第13圖繪示的是根據本發明之第三較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法，其中具有相同功能的元件將以相同的標號標示，第10圖為第11圖沿切線DD’的剖面示意圖。如第1圖所示，提供一基底10，接著在基底10上全面形成一金屬層12，根據本發明之較佳實施例，金屬層12為鋁，但不限於此，其它具導電性質的材料亦可以使用。接著如第10圖和第11圖所示，圖案化金屬層12形成一金屬墊14以及至少一金屬圈30環繞金屬墊14，其中金屬墊14和金屬圈30之間定義出一第一溝渠32。金屬圈30為封閉環狀，例如圓形環、矩形環、八角形環或其它環狀，因此第一溝渠32也是封閉環狀。如第12圖所示，形成一絶緣層16順應地覆蓋基底10、金屬墊14和金屬圈30，值得注意的是絶緣層 16填入第一溝渠32後使得絶緣層16的表面形成一淺溝渠18，也就是說淺溝渠18和第一溝渠32重疊，根據本發明之較佳實施例，淺溝渠的深度d約為0.1微米，其底部寬度W約為0.2微米，接著進行一圖案化步驟，例如一微影暨蝕刻製程，移除部分的絶緣層16使得金屬墊14曝露出來，剩餘的絶緣層16可以選擇性地部分覆蓋金屬墊14，此外在本實施例中，由於淺溝渠18對應第一溝渠32的形狀，因此淺溝渠18亦像第一溝渠32般呈封閉環狀，淺溝渠18的形狀就如同第5圖中的淺溝渠18形狀，並且淺渠溝18較佳形成在與金屬墊14相鄰的絶緣層16上。
請同時參閱第7圖和第13圖，第13圖為第7圖沿切線BB’的剖面示意圖，利用前述的無電鍍技術在金屬墊14上形成一第一凸塊下層金屬26接觸金屬墊14並且由金屬墊14延伸至覆蓋部分之淺溝渠18，之後再利用另一無電鍍技術形成一第二凸塊下層金屬28順應地覆蓋在第一凸塊下層金屬26上，第一凸塊下層金屬26和第二凸塊下層金屬28所在的位置、材料以及形成方式大置上和第6圖和第7圖所示的相同，請參閱前文在此不再贅述。在第一凸塊下層金屬26和第二凸塊下層金屬28完成後，同樣形成一第三凸塊下層金屬(圖未示)，第三凸塊下層金屬較佳為金。由於本發明額外製作了至少一個淺溝渠18造成路徑的拉長，因而降低了金原子到達第一凸塊下層金屬26會影響電性的部分之機會。
第14圖和第15圖為根據本發明之第四較佳實施例所繪示的具有凸塊下層金屬的半導體結構的製作方法，其中具有相同功能的元件將以相同的符號標示，第14圖為第15圖沿切線EE’的剖面示意圖，但為了圖示清楚，第15圖只標示出基底、金屬墊14和金屬圈30的位置，其它元件則予以省略，如第14圖和第15圖所示，在圖案化金屬層時除了如第三較佳實施例所述的形成一金屬墊14以及至少一金屬圈30環繞金屬墊14之外，在第四較佳實施例中，更可以在圖案化金屬層12時形成多個金屬圈30，各個金屬圈30環繞金屬墊14，並且較遠離金屬墊14之金屬圈30環繞較接近金屬墊14之金屬 圈30，相鄰的金屬圈30之間定義出一第二溝渠34，之後形成絶緣層18順應地覆蓋基底10、金屬墊14、各個金屬圈30並且填入第一溝渠32和第二溝渠34，絶緣層16填入第一溝渠32和第二溝渠34之後，後使得絶緣層16的表面形成多個淺溝渠18，在本實施例中，各個淺溝渠18具有相同的深度d和底部寬度W，然而在不同的情況下，各個淺溝渠18的底部寬度W和深度d可以不同，只要調整金屬圈30之間的距離即可。
之後如前文所述的移除部分的絶緣層16使得金屬墊14曝露出來，再用無電鍍技術形成第一凸塊下層金屬26、第二凸塊下層金屬28以及第三凸塊下層金屬(圖未示)。第一凸塊下層金屬26和第二凸塊下層金屬28所在的位置、材料以及形成方式大置上和第8圖和第9圖所示的相同，請參閱前文在此不再贅述。
根據本發明之第五較佳實施例，本發明提供一種具有凸塊下層金屬的半導體結構，如第6圖和第7圖所示，一種具有凸塊下層金屬的半導體結構100，包含：一基底10，一金屬墊14設於基底10上，一絶緣層16覆蓋基底10以及覆蓋金屬墊14之邊緣，至少一淺溝渠18設於絶緣層16中，淺溝渠18鄰近金屬墊14，甚至是與金屬墊14邊緣重疊的絶緣層16上。如第5圖所示，淺渠溝18可以為矩形環狀，但不限於此，淺渠溝18亦可以為圓形環或八角形環等其它形狀。根據本發明之較佳實施例，淺溝渠18的深度d約為0.1微米，其底部寬度W約為0.2微米。基底10可以為一矽(Silicon)基底、一鍺(Germanium)基底、一砷化鎵(Gallium Arsenide)基底、一矽鍺(Silicon Germanium)基底、一磷化銦(Indium Phosphide)基底、一氮化鎵(Gallium Nitride)基、一碳化矽(Silicon Carbide)基底或是一矽覆絕緣(silicon on insulator,SOI)基底，金屬墊14較佳為鋁。
一第一凸塊下層金屬26接觸金屬墊14並且由金屬墊14延伸至貼覆部分之淺溝渠18。詳細來說淺溝渠18包含一底部24和二側壁20/22，第一凸塊下層金屬26貼覆其中之一的側壁22以及部分之底部24，又或者第一 凸塊下層金屬26可以貼覆二個側壁22/24以及全部的底部24，根據本發明之較佳實施例，第一凸塊下層金屬26貼覆至少二分之一的淺溝渠18之底部寬度W。此外，一第二凸塊下層金屬28順應地貼覆第一凸塊下層金屬26並且第二凸塊下層金屬28也貼覆了部分的淺溝渠18之底部24。此外如第7圖所示，第二凸塊下層金屬28在淺溝渠18的環形中是連續的，因此被第二凸塊下層金屬28順應覆蓋的第一凸塊下層金屬26在淺溝渠18的環形中也是連續的，換句話說，在淺溝渠18中的第一凸塊下層金屬26也形成了一個封閉環狀。再者，第一凸塊下層金屬26為一完整且連續的金屬結構。第一凸塊下層金屬26較佳為鎳、第二凸塊下層金屬28較佳為鈀。
根據本發明之第六較佳實施例，如第13圖所示，本發明之一種具有凸塊下層金屬的半導體結構200其在金屬墊14之外圍可以另設有一金屬圈30，其中金屬墊14和金屬圈30之間定義出一第一溝渠32，金屬圈30之材料較佳和金屬墊14相同，如第11圖所示，金屬圈30為封閉環狀，例如圓形環、矩形環、八角形環或其它環狀，因此第一溝渠32也是封閉環狀，淺溝渠18和第一溝渠32重疊。金屬墊14、第一凸塊下層金屬26、第二凸塊下層金屬28等其它元件的位置和材料，請參閱第五較佳實施例中的描述，在此不再贅述。
根據本發明之第七較佳實施例，如第8圖和第9圖所示，本發明之一種具有凸塊下層金屬的半導體結構300在絶緣層16中也可以設置有複數個淺溝渠18，較遠離金屬墊14之淺溝渠18環繞較接近金屬墊14之淺溝渠18，每個淺溝渠18都具有一底部24和兩側壁20/22，第一凸塊下層金屬26貼覆至少一個底部24和和一個側壁22，但最遠離金屬墊14之淺溝渠18的其中之一側壁20未被第一凸塊下層金屬26貼覆，又或者第一凸塊下層金屬26可以貼覆每個淺溝渠18的底部24和側壁20/22。各個淺溝渠18可以具有相同的深度d和底部寬度W，然而在不同的情況下，各個淺溝渠18的底部寬度W和深度d可以不同。本實施例中，金屬墊14、第一凸塊下層金屬26、 第二凸塊下層金屬28等其它元件的位置和材料，請參閱第五較佳實施例中的描述，在此不再贅述。
根據本發明之第八較佳實施例，本發明之一種具有凸塊下層金屬的半導體結構400其複數個淺溝渠18可以利用下層金屬圈30的輪廓而造成，如第14圖和第15圖所示，在絶緣層16下方可以設置有複數個金屬圈30，各個金屬圈30環繞金屬墊14，並且較遠離金屬墊14之金屬圈30環繞接近金屬墊14之金屬圈3，此外，離金屬墊14最近金屬圈30和金屬墊14之間形成一第一溝渠，32相鄰的金屬圈30之間形成一第二溝渠34，第二溝渠34各別和一淺溝渠18重疊，第一溝渠32也和一淺溝渠18重疊，也就是說第一溝渠32和第二溝渠34的輪廓使得上層的絶緣層16形成了淺溝渠18。本實施例中，金屬墊14、第一凸塊下層金屬26、第二凸塊下層金屬28等其它元件的位置和材料，請參閱第五和第七較佳實施例中的描述，在此不再贅述。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (19)

  1. 一種具有凸塊下層金屬的半導體結構，包含：一基底；一金屬墊設於該基底上；一絶緣層覆蓋該基底以及覆蓋該金屬墊之邊緣；至少一淺溝渠設於該絶緣層中，該淺溝渠鄰近該金屬墊，並且該淺溝渠為環狀；一第一凸塊下層金屬接觸該金屬墊以及填入該淺溝渠，並且該第一凸塊下層金屬接觸該淺溝渠，其中填入該淺溝渠的該第一凸塊下層金屬不接觸該金屬墊。
  2. 如請求項1所述之具有凸塊下層金屬的半導體結構，其中該淺溝渠包含一底部和二側壁，該第一凸塊下層金屬貼覆其中之一的該等側壁以及部分之該底部。
  3. 如請求項2所述之具有凸塊下層金屬的半導體結構，其中該第一凸塊下層金屬貼覆該等側壁以及全部的該底部。
  4. 如請求項1所述之具有凸塊下層金屬的半導體結構，其中該第一凸塊下層金屬為連續的金屬結構。
  5. 如請求項1所述之具有凸塊下層金屬的半導體結構，另包含複數個該淺溝渠設於該絶緣層中。
  6. 如請求項5所述之具有凸塊下層金屬的半導體結構，其中該等淺溝渠中，較遠離該金屬墊之該淺溝渠環繞較接近該金屬墊之該淺溝渠。
  7. 如請求項5所述之具有凸塊下層金屬的半導體結構，其中各該淺溝渠包含一底部和二側壁，該第一凸塊下層金屬貼覆全部的該等底部和全部的該等側壁。
  8. 如請求項5所述之具有凸塊下層金屬的半導體結構，其中各該淺溝渠包含一底部和二側壁，該第一凸塊下層金屬貼覆部分的該等底部和部分的該等側壁，最遠離該金屬墊之該淺溝渠的其中之一該側壁未被該第一凸塊下層金屬覆蓋。
  9. 如請求項5所述之具有凸塊下層金屬的半導體結構，另包含複數個金屬圈設於該絶緣層下方，各該金屬圈環繞該金屬墊，並且較遠離該金屬墊之該金屬圈環繞較接近該金屬墊之該金屬圈。
  10. 如請求項9所述之具有凸塊下層金屬的半導體結構，其中各個金屬圈之間定義出一第二溝渠，各該第二溝渠各別和其中之一的該等淺溝渠重疊。
  11. 如請求項1所述之具有凸塊下層金屬的半導體結構，另包含至少一金屬圈設於該絶緣層下方，該金屬圈環繞該金屬墊。
  12. 如請求項9所述之具有凸塊下層金屬的半導體結構，其中在該金屬圈和該金屬墊之間定義出一第一溝渠，該第一溝渠和該淺溝渠重疊。
  13. 如請求項9所述之具有凸塊下層金屬的半導體結構，另包含一第二凸塊下層金屬覆蓋該第一凸塊下層金屬。
  14. 一種具有凸塊下層金屬的半導體結構的製作方法，包含： 提供一基底；形成一金屬墊於該基底上；形成一絶緣層覆蓋該基底和該金屬墊；進行一第一圖案化步驟，移除部分之該絶緣層，使得該金屬墊由該絶緣層曝露出來；進行一第二圖案化步驟，移除部分之該絶緣層，以在該絶緣層上形成至少一淺溝渠與該金屬墊相鄰，並且該淺溝渠為封閉環狀；以及形成一凸塊下層金屬接觸該金屬墊並且填入該淺溝渠，其中填入該淺溝渠中的該凸塊下層金屬不接觸該金屬墊。
  15. 如請求項14所述之具有凸塊下層金屬的半導體結構的製作方法，其中在進行該第二圖案化步驟時，在該絶緣層上形成複數個該淺溝渠與該金屬墊相鄰，該等淺溝渠中，較遠離該金屬墊之該淺溝渠環繞較接近該金屬墊之該淺溝渠。
  16. 如請求項14所述之具有凸塊下層金屬的半導體結構的製作方法，其中該凸塊下層金屬覆蓋該等淺溝渠。
  17. 一種具有凸塊下層金屬的半導體結構的製作方法，包含：提供一基底；形成一金屬層覆蓋該基底；圖案化該金屬層，形成一金屬墊以及至少一金屬圈環繞該金屬墊，其中該金屬墊和該金屬圈之間定義出一第一溝渠；形成一絶緣層順應地覆蓋該基底、該金屬墊、該金屬圈和該第一溝渠，部分之該絶緣層形成一淺溝渠與該第一溝渠重疊；圖案化該絶緣層，曝露出該金屬墊；以及 形成一凸塊下層金屬接觸該金屬墊並且填入部分之該淺溝渠。
  18. 如請求項17所述之具有凸塊下層金屬的半導體結構的製作方法，其中在圖案化該金屬層時，形成複數個該金屬圈，較遠離該金屬墊之該金屬圈環繞較接近該金屬墊之該金屬圈，相鄰的各該金屬圈之間定義出一第二溝渠，該絶緣層順應覆蓋各該第二溝渠，形成複數個該淺溝渠。
  19. 如請求項18所述之具有凸塊下層金屬的半導體結構的製作方法，其中該凸塊下層金屬覆蓋該等淺溝渠。
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