CN107644847A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN107644847A
CN107644847A CN201610891674.4A CN201610891674A CN107644847A CN 107644847 A CN107644847 A CN 107644847A CN 201610891674 A CN201610891674 A CN 201610891674A CN 107644847 A CN107644847 A CN 107644847A
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China
Prior art keywords
road floor
becket
certain embodiments
die
connection line
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Granted
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CN201610891674.4A
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CN107644847B (zh
Inventor
黄育智
陈志华
林志伟
蔡豪益
陈玉芬
郑余任
戴志轩
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明实施例提供一种半导体封装，包括模封半导体器件、第一重布线路层、第二重布线路层及多个层间导通孔。模封半导体器件包括管芯。第一重布线路层设置于模封半导体器件的第一侧。第二重布线路层设置于模封半导体器件的相对第一侧的第二侧。第二重布线路层包括图案化金属层以及金属环。图案化金属层具有电性连接至管芯的连接线路部。金属环围绕连接线路部并与连接线路部分离。层间导通孔连接至金属环的一部分且位于金属环的下方。层间导通孔延伸穿过模封半导体器件，以电性连接第一重布线路层及第二重布线路层。

Description

半导体封装
技术领域
本发明实施例涉及一种半导体结构，尤其涉及一种半导体封装。
背景技术
半导体元件用于多种电子应用上，像是个人计算机、手机、数字相机以及其他电子设备。半导体元件通常是通过在半导体衬底上依序沉积绝缘层或介电层、导体层以及半导体层或半导体材料，并使用光刻法图案化多种材料层以于半导体衬底上形成线路组件以及构件来制备。许多集成电路通常被制造在单一个半导体芯片上。可将所述晶片(wafer)的管芯(dies)在晶片阶段(wafer level)处理与封装，且用于晶片级封装(wafer levelpackaging)的各种技术业已开发。
发明内容
本发明实施例是针对一种半导体封装，其具有较高的空间利用率及较小的半导体封装尺寸。
本发明实施例提供一种半导体封装，包括模封半导体器件、第一重布线路层、第二重布线路层及多个层间导通孔。模封半导体器件包括第一管芯(die)。第一重布线路层设置于所述模封半导体器件的第一侧。第二重布线路层设置于所述模封半导体器件的相对所述第一侧的第二侧，其中所述第二重布线路层包括图案化金属层以及金属环，所述图案化金属层具有电性连接至所述第一管芯的连接线路部，所述金属环围绕所述连接线路部并与所述连接线路部分离。层间导通孔连接至所述金属环的一部分且位于所述金属环的下方，所述层间导通孔延伸穿过所述模封半导体器件，以电性连接所述第一重布线路层及所述第二重布线路层。
为让本发明实施例的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
包含附图以便进一步理解本发明实施例，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明实施例，并与描述一起用于解释本发明实施例的原理。
图1是依照本揭露的一些实施例的一种半导体封装的剖面示意图；
图2是图1的半导体封装的上视示意图；
图3是图2的半导体封装的局部放大示意图；
图4是依照本揭露的一些实施例的一种半导体封装的局放大示意图；
图5A至图5F是图1的半导体封装的制造过程的各种阶段的剖面示意图；
图6是依照本揭露的一些实施例的一种半导体封装的剖面示意图。
附图标号说明
100：半导体封装；
110：模封半导体器件；
112：第一管芯；
112a：有源表面；
112b：电性接点；
112c：背面；
112d：侧面；
114：模塑料；
120：第一重布线路层；
122、126：介电层；
124、128：图案化金属层；
124a、124b：接垫；
128a：通孔；
130：第二重布线路层；
131：图案化金属层；
132：连接线路部；
132a：连接线；
132b：金属网格图案；
134：金属环；
134a：第一接垫部；
134b：第二接垫部；
136：图案化第一介电层；
138：第二介电层；
140：层间导通孔；
150：密封环；
160、170：电性端子；
180：第二管芯；
190：保护层；
195：黏着层；
200：承载器；
300：固定件；
F1：手指；
G1、G2：沟槽；
S1：第一侧；
S2：第二侧。
具体实施方式
以下发明内容提供用于实施所提供的标的不同特征的许多不同实施例或实例。以下所描述的构件及设置的具体实例是为了以简化的方式传达本发明实施例为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明实施例在各种实例中可使用相同的元件符号和/或字母来指代相同或类似的部件。元件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例和/或设置本身之间的关系。
另外，为了易于描述附图中所显示的一个构件或特征与另一组件或特征的关系，本文中可使用例如“在...下”、“在...下方”、“下部”、“在…上”、“在…上方”、“上部”及类似术语的空间相对术语。除了附图中所显示的定向之外，所述空间相对术语意欲涵盖元件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
图1是依照本揭露的一些实施例的一种半导体封装的剖面示意图。图2是图1的半导体封装的上视示意图。图3是图2的半导体封装的局部放大示意图。请同时参考图1至图3，请参考图1，在一些实施例中，半导体封装100包括模封半导体器件110、第一重布线路层120、第二重布线路层130以及多个层间导通孔140。模封半导体器件110包括第一管芯(die)112以及模塑料114。在一些实施例中，第一管芯112包括具有多个电性接点112b的有源表面112a以及相对于有源表面112a的背面112c。在某些实施例中，第一管芯112是模封于模塑料114且模塑料114至少包覆第一管芯112的侧面112d。在一些实施例中，第一重布线路层120设置于模封半导体器件110的第一侧S1。第二重布线路层130设置于模封半导体器件110的第二侧S2，且第二侧S2相对第一侧S1。也就是说，第一管芯112是夹设于第一重布线路层120以及第二重布线路层130之间。换句话说，第一管芯112以及模塑料114设置于第一重布线路层120上，且第二重布线路层130设置于第一管芯112以及模塑料114上。在一些实施例中，第一重布线路层120或第二重布线路层130可包括一或多个图案化金属层以及一或多个聚合物基介电层(polymer-based dielectric layers)。聚合物基介电层的材料包括聚酰亚胺(polyimide,PI)、苯环丁烷(benzocyclobutene,BCB)、聚苯并恶唑(polybenzooxazole,PBO)或任何其他适合的聚合物基介电材料。如图2及图3所示，在某些实施例中，第二重布线路层130包括至少一个图案化金属层131，其包括连接线路部132、金属环134以及选择性设置的密封环150。
在一些实施例中，第一管芯112的有源表面112a背离第一重布线路层120(意即，第一管芯112如图1所示的面向上)，且第一管芯112的背面112c接触第一重布线路层120。第一管芯112并未接触层间导通孔140。在一些实施例中，层间导通孔140延伸穿过模封半导体器件110以电性连接第一重布线路层120以及第二重布线路层130。具体而言，被模封半导体器件110的模塑料114所暴露的层间导通孔140的两端会电性连接第一重布线路层120以及第二重布线路层130。
在一些实施例中，层间导通孔140形成于第一重布线路层120的多个被暴露的通孔128a上，且层间导通孔140直接连接第一重布线路层120的通孔128a。在一些实施例中，层间导通孔140为贯穿整合扇出型通孔(through integrated InFO vias)。在某些实施例中，第一重布线路层120的通孔128a的位置实质上对准或至少部分重迭于层间导通孔140的位置。在一些实施例中，由于层间导通孔140直接连接至第一重布线路层140的通孔128a，可为管芯建立较短的电性连接路径，因而减少半导体封装100的高度并增进半导体封装100的电性表现。在一些实施例中，层间导通孔140可经由下列步骤而形成：形成具有多个开口的掩模图案(未绘示)，其开口分别暴露第一重布线路层120的通孔128a，并经由电镀或沉积而形成金属材料，使其填充于开口以形成层间导通孔140，之后再移除掩模图案。在某些实施例中，层间导通孔140形成于第一重布线路层120上，并配置于第一管芯112旁且沿着第一管芯112的周边配置，使其不会妨碍第一管芯112的传感区域。层间导通孔140可依据产品设计而配置于管芯之间的位置。
在一些实施例中，在第一重布线路层120上的第一管芯112以及层间导通孔140被模封于模塑料114内。在一些实施例中，模塑料114填充于第一管芯112以及层间导通孔140之间的间隙并覆盖第一重布线路层120。在一些实施例中，模塑料114形成于第一管芯112上并覆盖第一管芯112的有源表面112a。在一些实施例中，模塑料114如图1所示的至少包覆第一管芯112的侧面112d且暴露第一管芯112的有源表面112a。举例而言，模塑料114包括环氧树脂或其他适合的模封材料。在某些实施例中，层间导通孔140更可包括阻障层(未绘示)，其位于层间导通孔140与模塑料114之间。
在一些实施例中，半导体封装100更可包括一或多个电性端子160、170，其位于第一重布线路层120的最上层的图案化线路层124的接垫124a、124b。电性端子160、170的数量及配置可依据布局或布线而调整。在一些实施例中，电性端子160可例如为焊球或是球栅阵列(ball grid array，BGA)，其设置于接垫124a、124b上且被第一重布线路层120的最上层的图案化线路层124所暴露，而电性端子160下方的接垫124a、124b可作为焊球垫(ballpads)的用途。在一些实施例中，电性端子170可例如为用以电性连接另一管芯180的凸块，且管芯180更可包括例如积体被动器件(integrated passive devices)的其他电子器件。
在替代实施例中，半导体封装100更可包括额外的管芯，其设置于第一管芯112上及/或第一管芯112旁，且连接结构可调整以电性连接额外的管芯。本揭露的结构不受限于仅包括第一管芯112及第二管芯180。
请参照图1、图2及图3，在一些实施例中，第二重布线路层130的连接线路部132如图1所示的电性连接至第一管芯112的电性接点112b。在一些实施例中，金属环134围绕连接线路部132并与连接线路部132电性绝缘，而密封环150则围绕金属环134及连接线路部132并与金属环134及连接线路部132电性绝缘。详细而言，在某些实施例中，既然密封环150、金属环134及连接线路部132是由同一金属层所形成且同为图案化金属层131的一部分，密封环150及金属环134与连接线路部132延伸于同一水平面。具体而言，在一些实施例中，图案化金属层131更包括环绕连接线路部132的沟槽G1，以定义出连接线路部132及金属环134，并将金属环134与连接线路部132分离。在一些实施例中，图案化金属层131更包括环绕金属环134的沟槽G2，以定义出金属环134以及密封环150，并使金属环134与密封环150隔离。层间导通孔140位于金属环134的正下方，以增进空间利用率并降低封装结构100的尺寸。
在一些实施例中，图案化金属层113更包括至少一个第一接垫部134a及至少一个第二接垫部134b，其位于金属环134的跨度区域(span region)内。在一些实施例中，第一接垫部134a与金属环134连接，且第二接垫部134b与金属环134隔离。在一些实施例中，层间导通孔140的至少其中之一(例如图3所示的层间导通孔140a)连接至金属环134的第一接垫部134a且电性连接至金属环134。因此，层间导通孔140的至少其中之另一(例如图3所示的层间导通孔140b)连接至第二连接部134b，并电性连接至连接线路部132。在某些实施例中，金属环134是以金属网格的形式而形成，也就是说金属环134可如图3所示的包括多个开口135。相似地，在一些实施例中，连接线路部132包括多条连接线132a以及与连接线132a绝缘的金属网格图案132b。在一些实施例中，至少一个连接线132a与第二接垫部134b连接，使层间导通孔140b经由连接线132a及第二接垫部134b而电性连接至连接线路部132。金属环134的金属网格及金属网格图案132b可作为虚设网格(dummymesh)的用途，并用以减少连接线路部132及金属环134上的应力，以防止连接线路部132及金属环134产生翘曲(warpage)。
图4是依照本揭露的一些实施例的一种半导体封装的局放大示意图。在替换实施例中，金属环134可被塑形为如图4所示的实心的金属环，也就是没有如图3所示的多个开口。本揭露并不限制金属环134的形成方式，只要其环绕并绝缘于连接线路部132即可。在某些实施例中，第一管芯112可为包括一或多个传感器件的传感芯片。在某些实施例中，第一管芯112包括至少一个指纹传感器，其例如为光学指纹传感器、电容指纹传感器或其他适合种类的传感器。在一些实施例中，第一管芯112是传感芯片且第二重布线路层130是正面(front-side)重布线路层，而第一管芯112可检测或感测光或信号。然而，第一管芯112可以是具有不同功能的其他种类的管芯或芯片，以与产品的设计匹配。在某些实施例中，第一管芯112包括指纹传感器，且金属环134经配置以作为电容触控开关的驱动环的用途，当手指出现时，电容触控开关启动或关闭指纹传感器。
在一些实施例中，密封环150可选择性地形成于模封半导体器件110的模塑料114上并环绕金属环134，其用以防止不要的水气及活动离子污染物穿透第二重布线路层130及穿透半导体封装100的侧面而进入第一管芯112的功能性线路区。并且，密封环150可增进半导体封装100的结构补强，以防止第一管芯112的运作可靠度下降。
图5A至图5F是图1的半导体封装的制造过程的各种阶段的剖面示意图。在图1至图3中所叙述的相同构件将使用相同标号，且相同构件的某些细节与叙述于此将不再赘述。在例示性实施例中，此半导体制造过程为晶片级封装工艺的一部分。在一些实施例中，管芯可表示为晶片的多个管芯，而单一个封装可表示为由后续的半导体制造过程所获得的多个半导体封装。
请参照图5A，在一些实施例中，提供承载器200，其中承载器200可为用于半导体封装100的制造过程的玻璃承载器或其他适合的承载器。在其他实施例中，承载器200可涂布脱黏层(debond layer)。脱黏层的材料可以是任何材料，其适用于将承载器200从配置于其上的迭层脱离。接着，第一重布线路层120形成于承载器200上。在某些实施例中，形成第一重布线路层120的步骤包括形成介电层122于承载器200上，并形成金属层(未绘示)于介电层122上，且对所述金属层进行图案化工艺，以形成图案化金属层124。在某些实施例中，图案化金属层124包括一或多个接垫124a、124b。在某些实施例中，图案化金属层124可由电镀或沉积而形成。在某些实施例中，第一重布线路层120的形成更包括形成介电层126于图案化金属层124及介电层122上，再图案化上述介电层126以暴露图案化金属层124并形成图案化金属层128，其连接至暴露的图案化金属层124。
在某些实施例中，第一重布线路层120可经由逐层堆栈介电层122、126及图案化金属层124、128而形成。意即，在一些实施例中，第一重布线路层120可包括多过或少于上述的两介电层122、126，亦可包括多过或少于如图5A所示的两个图案化金属层124、128。图案化金属层的数量及介电层的数量可分别依据半导体封装100的布线需求作调整。在一些实施例中，多个层间导通孔140形成于第一重布线路层120上并电性连接至第一重布线路层120。具体来说，在一些实施例中，层间导通孔140可形成于介电层126上且连接至图案化金属层128的通孔128a。在一些实施例中，层间导通孔140是通过电镀、沉积或其他适合的方法而形成。
请参照图5B，在一些实施例中，至少一个第一管芯112是设置于第一重布线路层120。在例示性实施例中，第一管芯112为传感芯片，其包括一或多个传感器件。在某些实施例中，第一管芯112包括至少一个指纹传感器，其例如为光学指纹传感器、电容指纹传感器或其他适合种类的包括电荷耦合组件(charge coupled devices,CCDs)的传感器。在一些实施例中，第一管芯112设置于第一重布线路层120，以使第一管芯112的有源表面112a背离第一重布线路层120(意即，面朝上)。如图5B所示，第一管芯112设置于介电层126上且第一管芯112的背面112c与第一重布线路层120的介电层126接触。在一些实施例中，提供管芯贴合薄膜(未绘示)于第一管芯112以及第一重布线路层120之间。层间导通孔140配置于第一管芯112旁并环绕第一管芯112，且第一管芯112远离层间导通孔140而配置。
请参照图5C，在一些实施例中，模塑料114形成于第一重布线路层120上并包覆第一管芯112及层间导通孔140。换句话说，第一重布线路层120上的第一管芯112及层间导通孔140模封于模塑料114内。在一些实施例中，模塑料114填充于第一管芯112及层间导通孔140之间的间隙并覆盖第一重布线路层120。在一些实施例中，模塑料114形成于第一管芯112上并覆盖第一管芯112的有源表面112a。
在一些实施例中，模塑料114可被平面化以暴露层间导通孔140。在一些实施例中，过度模封(over-molded)的模塑料114及层间导通孔140可被抛磨至第一管芯112的电性接点112b被暴露出来。在一些实施例中，层间导通孔140的上表面、模塑料114以及第一管芯112在处理过后变成实质上共平面。在一些实施例中，模塑料114及/或层间导通孔140通过研磨工艺或化学机械抛光(chemical mechanical polishing,CMP)而被平面化。在研磨工艺之后，可选择性地执行清洁步骤，例如清洁及移除由研磨步骤所产生的残留物。然而，本揭露并不局限于此，平面化步骤可经由任何适合的方法来执行。
请参照图5D，第二重布线路层130形成于模塑料114上并位于第一管芯112上。在一些实施例中，第二重布线路层130电性连接至层间导通孔140及第一管芯112。层间导通孔140位于金属环134的正下方并配置于金属环134的跨度(跨度区域)内，以增进空间利用率以及降低半导体封装100的尺寸。第二重布线路层130的形成包括逐层地接续形成图案化第一介电层136、图案化金属层131以及第二介电层138。形成第二重布线路层130的方法相似于形成第一重布线路层120的方法。
在某些实施例中，第一介电层是先形成于模塑料114以及第一管芯112上，接着再图案化以形成图案化第一介电层136，其具有多个如图5D所示的开口。上述开口暴露层间导通孔140及第一管芯112的多个电性接点112b。在一些实施例中，金属层形成于图案化第一介电层136上并填充上述的开口。接着，金属层被图案化以形成图案化金属层131，其包括如图3所示的连接线路部132及金属环134。在一些实施例中，连接线路部132电性连接至层间导通孔140并电性连接至第一管芯112的电性接点112b。请参照图3，在一些实施例中，金属环134围绕连接线路部132并与连接线路部132隔绝。在某些实施例中，既然连接线路部132及金属环134是经由一个图案化工艺并由同一金属层所形成，金属环134与连接线路部132延伸于延伸于同一水平面。在一些实施例中，金属层被图案化以形成沟槽G1，其环绕连接线路部132以定义出连接线路部132以及金属环134，并隔绝金属环134与连接线路部132。在一些实施例中，接续形成第二介电层138以覆盖图案化第一介电层136以及图案化金属层131。
在某些实施例中，第二重布线路层130可包括大于或少于上述的两个介电层136、138以及大于或少于图案化金属层131。在一些实施例中，由于连接线路部132以及金属环134是由同一金属层(图案化金属层131)所图案化而得，连接线路层132及金属环134与第二重布线路层130位于同一水平面。也就是说，图案化金属层的数量以及介电层的数量可依据半导体封装100的布线需求而调整。在一些实施例中，金属环134是以金属网格的形式呈现，也就是说金属环134可包括如图3所示的多个开口135。在一些实施例中，连接线路部132可包括多个连接线132a以及与连接线132a绝缘的金属网格图案132b。金属环134的金属网格以及金属网格图案132b可作为虚设网格，并用以降低连接线路部132及金属环134上的应力，以防止连接线路部132及金属环134产生翘曲。
图6是依照本揭露的一些实施例的一种半导体封装的剖面示意图。请参照图5D及图6，在一些实施例中，如图6所示的保护层190可设置于第二重布线路层130上，且保护层190接触第二介电层138。在一些实施例中，保护层190例如包括玻璃盖体、盖板、硬质涂料层或任何其他适合的保护膜。在一些实施例中，保护层190更包括功能层，例如偏振膜、色膜、抗反射层或抗眩光层。在某些实施例中，保护层190至少允许特定信号或某些波长的光通过。适合的保护层110是基于产品的需求及设计而选择的。在一些实施例中，如图6所示的黏着层195可先设置于第二重布线路层130或保护层190上，之后，保护层190再设置于第二重布线路层130上，以贴附于第二重布线路层130。黏着层195例如包括紫外线固化胶、热固化胶、光固化胶或光热转换(light-to-heat conversion,LTHC)胶或其他类似物，当然也可使用其他种类的黏着剂。此外，黏着层195也适于允许光或信号通过。在某些实施例中，第一管芯112包括至少一个指纹传感器，且金属环134经配置以作为电容触控开关的驱动环的用途，当手指F1触碰保护层190时，电容触控开关启动或关闭指纹传感器。如此，第一管芯112可接收及检测通过保护层190的信号。
请参照图5E，在一些实施例中，承载器200可从第一重布线路层120脱离。在一些实施例中，半导体封装100从承载器200上脱离，接着被翻面(上下翻转)而设置于固定件300上。在一些实施例中，固定件300可例如为承载胶带(carrier tape)，但固定件300也可为其他适合种类的承载器，其用以承载从承载器200上脱离的半导体封装100。如图5E所示，从承载器200上脱离的剩余的结构被翻面，以使第一重布线路层120的表面朝上而变成上表面，且图案化金属层124变成最上层的图案化金属层。接着，对介电层122进行图案化以于第一重布线路层120的介电层122上形成多个开口，且介电层122的开口暴露最上层的图案化金属层124的接垫124a。
请参照图5F及图6，在一些实施例中，多个电性端子160、170设置于被所述开口所暴露的图案化金属层124的接垫124a、124b上。在一些实施例中，第二管芯180通过电性端子170而接合于第一重布线路层120的上表面。在一些实施例中，电性端子160电性连接至第一重布线路层120、第二重布线路层130以及第一管芯112。在一些实施例中，第二管芯180电性连接至第一重布线路层120并可电性连接至第一管芯112。接着，在后续的工艺中切割半导体封装100并与固定件300分离。在一些实施例中，上述的制造过程是晶片级封装工艺的一部分，在切割工艺之后可得到多个半导体封装100。在一些实施例中，固定件300可在切割工艺之前即与半导体封装100分离。
根据一些实施例，一种半导体封装包括模封半导体器件、第一重布线路层、第二重布线路层以及多个层间导通孔。模封半导体器件包括第一管芯。第一重布线路层设置于模封半导体器件的第一侧。第二重布线路层设置于模封半导体器件的相对第一侧的第二侧，其中第二重布线路层包括图案化金属层以及金属环。图案化金属层具有电性连接至第一管芯的连接线路部。金属环围绕连接线路部并与连接线路部分离。层间导通孔连接至金属环的一部分且位于金属环的下方。层间导通孔延伸穿过模封半导体器件，以电性连接第一重布线路层及第二重布线路层。
根据一些实施例，一种半导体封装包括第一重布线路层、至少一个第一管芯、模塑料、第二重布线路层以及多个层间导通孔。第一管芯设置于并电性连接至第一重布线路层。模塑料设置于第一重布线路层上并至少包覆第一管芯的侧面。第二重布线路层设置于模塑料以及第一管芯上，且第二重布线路层包括电性连接至第一管芯的连接线路层以及环绕连接线路层并与连接线路层电性隔离的金属环。金属环与连接线路层延伸于同一水平面上。层间导通孔位于金属环的正下方并穿过模塑料以电性连接第一重布线路层以及第二重布线路层。如此配置，可增进空间利用率并降低半导体封装100的尺寸。
根据一些实施例，一种半导体封装的制造方法包括下列步骤。提供承载器。形成第一重布线路层于承载器上。形成多个层间导通孔于第一重布线路层上，其中层间导通孔电性连接至第一重布线路层。设置至少一个第一管芯于第一重布线路层上。形成包覆第一管芯及层间导通孔的模塑料。形成第二重布线路层于模塑料及第一管芯上。第二重布线路层的形成包括形成图案化金属层。图案化金属层具有电性连接至第一管芯的连接线路层以及环绕连接线路层并与连接线路层电性隔绝的金属环。将承载器从第一重布线路层脱离。
以上概述了数个实施例的特征，使本领域普通技术人员可更佳了解本发明实施例的态样。本领域普通技术人员应理解，其可轻易地使用本发明实施例作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的和/或达到相同优点。本领域普通技术人员还应理解，这种等效的设置并不悖离本发明实施例的精神与范畴，且本领域普通技术人员在不悖离本发明实施例的精神与范畴的情况下可对本文做出各种改变、置换以及改变。
最后应说明的是：以上各实施例仅用以说明本发明实施例的技术方案，而非对其限制；尽管参照前述各实施例对本发明实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (1)

1.一种半导体封装，其特征在于，包括：
模封半导体器件，包括第一管芯；
第一重布线路层，设置于所述模封半导体器件的第一侧；
第二重布线路层，设置于所述模封半导体器件的相对所述第一侧的第二侧，其中所述第二重布线路层包括图案化金属层以及金属环，所述图案化金属层具有电性连接至所述第一管芯的连接线路部，所述金属环围绕所述连接线路部并与所述连接线路部分离；以及
多个层间导通孔，连接至所述金属环的一部分且位于所述金属环的下方，所述层间导通孔延伸穿过所述模封半导体器件，以电性连接所述第一重布线路层及所述第二重布线路层。
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