CN112786551B - 重布线层结构与半导体封装 - Google Patents
重布线层结构与半导体封装 Download PDFInfo
- Publication number
- CN112786551B CN112786551B CN201911281915.3A CN201911281915A CN112786551B CN 112786551 B CN112786551 B CN 112786551B CN 201911281915 A CN201911281915 A CN 201911281915A CN 112786551 B CN112786551 B CN 112786551B
- Authority
- CN
- China
- Prior art keywords
- pad
- coupled
- conductive
- layer
- layer structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 46
- 239000004020 conductor Substances 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims description 18
- 238000005538 encapsulation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- 239000010949 copper Substances 0.000 description 11
- 239000010931 gold Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000008393 encapsulating agent Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明提供一种重布线层结构,包括第一接垫、第二接垫、第三接垫、第四接垫、第一开关元件、第二开关元件、第三开关元件与第四开关元件。第一接垫、第二接垫、第三接垫与第四接垫彼此分离。第一开关元件包括彼此分离的第一导体层与第二导体层。第二开关元件包括彼此分离的第三导体层与第四导体层。第三开关元件包括彼此分离的第五导体层与第六导体层。第四开关元件包括彼此分离的第七导体层与第八导体层。上述重布线层结构可有效地降低生产成本。
Description
技术领域
本发明涉及一种半导体结构,尤其涉及一种重布线层(redistribution layer,RDL)结构与半导体封装。
背景技术
为了使电子产品设计实现轻薄、短小的特征,半导体封装技术不断进步以试图开发出体积更小、重量更轻、整合性更高以及在市场上竞争力更高的产品。举例来说,在一些产品中,如果封装需要多晶粒的堆叠,则通常需要多个不同的重布线层来提供连结。然而,由于不同的重布线层需要使用多个不同的光罩来进行制作,因此会造成生产成本提高。
发明内容
本发明提供一种重布线层结构与半导体封装,其可有效地降低生产成本。
本发明提出一种重布线层结构,包括第一接垫、第二接垫、第三接垫、第四接垫、第一开关元件、第二开关元件、第三开关元件与第四开关元件。第一接垫、第二接垫、第三接垫与第四接垫彼此分离。第一开关元件包括彼此分离的第一导体层与第二导体层。第一导体层耦接至第一接垫。第二导体层耦接至第三接垫。第二开关元件包括彼此分离的第三导体层与第四导体层。第三导体层耦接至第一接垫。第四导体层耦接至第四接垫。第三开关元件包括彼此分离的第五导体层与第六导体层。第五导体层耦接至第二接垫。第六导体层耦接至第三接垫。第四开关元件包括彼此分离的第七导体层与第八导体层。第七导体层耦接至第二接垫。第八导体层耦接至第四接垫。
依照本发明的一实施例所述,在上述重布线层结构中,还可包括第一导线、第二导线、第三导线、第四导线、第五导线、第六导线、第七导线与第八导线。第一导线耦接在第一导体层与第一接垫之间。第二导线耦接在第二导体层与第三接垫之间。第三导线耦接在第三导体层与第一接垫之间。第四导线耦接在第四导体层与第四接垫之间。第五导线耦接在第五导体层与第二接垫之间。第六导线耦接在第六导体层与第三接垫之间。第七导线耦接在第七导体层与第二接垫之间。第八导线耦接在第八导体层与第四接垫之间。
依照本发明的一实施例所述,在上述重布线层结构中,第一导线、第一导体层与第一接垫可为一体成形。第二导线、第二导体层与第三接垫可为一体成形。第三导线、第三导体层与第一接垫可为一体成形。第四导线、第四导体层与第四接垫可为一体成形。第五导线、第五导体层与第二接垫可为一体成形。第六导线、第六导体层与第三接垫可为一体成形。第七导线、第七导体层、第二接垫可为一体成形。第八导线、第八导体层与第四接垫可为一体成形。
依照本发明的一实施例所述,在上述重布线层结构中,还可包括第五接垫与第六接垫。第五接垫耦接至第三接垫。第六接垫耦接至第四接垫。
依照本发明的一实施例所述,在上述重布线层结构中,还可包括第九导线与第十导线。第九导线耦接在第三接垫与第五接垫之间。第十导线耦接在第四接垫与第六接垫之间。
依照本发明的一实施例所述,在上述重布线层结构中,第九导线、第三接垫与第五接垫可为一体成形。第十导线、第四接垫与第六接垫可为一体成形。
依照本发明的一实施例所述,在上述重布线层结构中,还可包括至少一个虚拟接垫。虚拟接垫可分离于第一接垫、第二接垫、第三接垫、第四接垫、第一开关元件、第二开关元件、第三开关元件与第四开关元件。
本发明提出一种半导体封装,包括第一晶粒、第二晶粒、第一重布线层结构与第二重布线层结构。第一重布线层结构设置在第一晶粒上。第二重布线层结构设置在第二晶粒上。第一重布线层结构与第二重布线层结构分别包括上述重布线层结构。第一重布线层结构与第二重布线层结构位于第一晶粒与第二晶粒之间且彼此耦接。
依照本发明的一实施例所述,在上述半导体封装中,第一重布线层结构的第三接垫可耦接至第二重布线层结构的第四接垫。第一重布线层结构的第四接垫可耦接至第二重布线层结构的第三接垫。
依照本发明的一实施例所述,在上述半导体封装中,还可包括第一导电连接件与第二导电连接件。第一导电连接件耦接在第一重布线层结构的第三导体层与第一重布线层结构的第四导体层之间。第二导电连接件耦接在第一重布线层结构的第五导体层与第一重布线层结构的第六导体层之间。
依照本发明的一实施例所述,在上述半导体封装中,还可包括第三导电连接件与第四导电连接件。第三导电连接件耦接在第二重布线层结构的第一导体层与第二重布线层结构的第二导体层之间。第四导电连接件耦接在第二重布线层结构的第七导体层与第二重布线层结构的第八导体层之间。
依照本发明的一实施例所述,在上述半导体封装中,还可包括第五导电连接件与第六导电连接件。第五导电连接件耦接在第一重布线层结构的第三接垫与第二重布线层结构的第四接垫之间。第六导电连接件耦接在第一重布线层结构的第四接垫与第二重布线层结构的第三接垫之间。
依照本发明的一实施例所述,在上述半导体封装中,重布线层结构还可包括第一导线、第二导线、第三导线、第四导线、第五导线、第六导线、第七导线与第八导线。第一导线耦接在第一导体层与第一接垫之间。第二导线耦接在第二导体层与第三接垫之间。第三导线耦接在第三导体层与第一接垫之间。第四导线耦接在第四导体层与第四接垫之间。第五导线耦接在第五导体层与第二接垫之间。第六导线耦接在第六导体层与第三接垫之间。第七导线耦接在第七导体层与第二接垫之间。第八导线耦接在第八导体层与第四接垫之间。
依照本发明的一实施例所述,在上述半导体封装中,第一导线、第一导体层与第一接垫可为一体成形。第二导线、第二导体层与第三接垫可为一体成形。第三导线、第三导体层与第一接垫可为一体成形。第四导线、第四导体层与第四接垫可为一体成形。第五导线、第五导体层与第二接垫可为一体成形。第六导线、第六导体层与第三接垫可为一体成形。第七导线、第七导体层、第二接垫可为一体成形。第八导线、第八导体层与第四接垫可为一体成形。
依照本发明的一实施例所述,在上述半导体封装中,重布线层结构还可包括第五接垫与第六接垫。第五接垫耦接至第三接垫。第六接垫耦接至第四接垫。
依照本发明的一实施例所述,在上述半导体封装中,重布线层结构还可包括第九导线与第十导线。第九导线耦接在第三接垫与第五接垫之间。第十导线耦接在第四接垫与第六接垫之间。
依照本发明的一实施例所述,在上述半导体封装中,第九导线、第三接垫与第五接垫可为一体成形。第十导线、第四接垫与第六接垫可为一体成形。
依照本发明的一实施例所述,在上述半导体封装中,重布线层结构还可包括至少一个虚拟接垫。虚拟接垫可分离于第一接垫、第二接垫、第三接垫、第四接垫、第一开关元件、第二开关元件、第三开关元件与第四开关元件。
依照本发明的一实施例所述,在上述半导体封装中,还可包括基底。第一晶粒与第二晶粒可堆叠在基底上。第二晶粒可位于第一晶粒与基底之间。
依照本发明的一实施例所述,在上述半导体封装中,还可包括包封体。包封体包封第一晶粒与第二晶粒。
基于上述,本发明所提出的重布线层结构包括第一开关元件、第二开关元件、第三开关元件与第四开关元件。因此,可通过将第一开关元件、第二开关元件、第三开关元件与第四开关元件分别设定为“开启状态(on state)”或“关闭状态(off state)”来决定接垫之间的耦接关系。如此一来,可以通过相同的重布线层结构来实现多种重布线层的接线方式。此外,在本发明所提出的半导体封装中,由于重布线层结构可用以实现多种重布线层的接线方式,所以第一晶粒与第二晶粒可通过具有相同重布线层布局图案(RDL layoutpattern)的第一重布线层结构与第二重布线层结构而彼此耦接,因此可有效地减少光罩的数量,且可降低生产成本。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1为本发明一实施例的重布线层结构的上视图;
图2为本发明一实施例的半导体封装的侧视图;
图3为图2中的设置在晶粒上的重布线层结构的上视图;
图4为将图3的其中一个晶粒进行翻转后的重布线层结构的示意图。
附图标记说明
10:半导体封装
100、100a、100b:重布线层结构
102a~102f:接垫
104a~104d:开关元件
106a~106h:导体层
108a~108j:导线
110a~110d:虚拟接垫
112a、112b:晶粒
114a~114f:导电连接件
116:基板
118a、118b:接合线
120:包封体
S1:第一面
S2:第二面
具体实施方式
图1为本发明一实施例的重布线层结构的上视图。
请参照图1,重布线层结构100包括接垫102a、接垫102b、接垫102c、接垫102d、开关元件104a、开关元件104b、开关元件104c与开关元件104d。重布线层结构100例如是重布线层布局图案。
接垫102a、接垫102b、接垫102c与接垫102d彼此分离。在本实施例中,接垫102a与接垫102b可用以作为晶粒接垫(die pad),且接垫102c与接垫102d可用以作为焊垫(solderpad),但本发明并不以此为限。此外,接垫102a与接垫102b例如是位于接垫102c与接垫102d之间,但本发明并不以此为限。所属技术领域技术人员可根据产品设计来调整接垫102a、接垫102b、接垫102c与接垫102d的设置方式。接垫102a~102d的材料例如是铜(Cu)、铝(Al)、镍(Ni)或金(Au)。
开关元件104a包括彼此分离的导体层106a与导体层106b。导体层106a耦接至接垫102a。导体层106b耦接至接垫102c。开关元件104b包括彼此分离的导体层106c与导体层106d。导体层106c耦接至接垫102a。导体层106d耦接至接垫102d。开关元件104c包括彼此分离的导体层106e与导体层106f。导体层106e耦接至接垫102b。导体层106f耦接至接垫102c。开关元件104d包括彼此分离的导体层106g与导体层106h。导体层106g耦接至接垫102b。导体层106h耦接至接垫102d。在本实施例中,用语“耦接(coupled)”可为“直接耦接(directlycoupled)”或“间接耦接(indirectly coupled)”。导体层106a~106h的材料例如是铜(Cu)、铝(Al)、镍(Ni)或金(Au)。
开关元件104a可用以决定接垫102a与接垫102c之间的耦接关系。开关元件104b可用以决定接垫102a与接垫102d之间的耦接关系。开关元件104c可用以决定接垫102b与接垫102c之间的耦接关系。开关元件104d可用以决定接垫102b与接垫102d之间的耦接关系。
以下,以开关元件104a为例来进行说明。当导体层106a与导体层106b未彼此耦接时,开关元件104a为“关闭状态”,且接垫102a与接垫102c未彼此耦接。当导体层106a与导体层106b通过导电连接件(如,焊球(solder ball))而彼此耦接时,开关元件104a为“开启状态”,且接垫102a与接垫102c彼此耦接。
此外,重布线层结构100还可包括导线108a、导线108b、导线108c、导线108d、导线108e、导线108f、导线108g与导线108h。导线108a耦接在导体层106a与接垫102a之间。导线108a、导体层106a与接垫102a可为一体成形。导线108b耦接在导体层106b与接垫102c之间。导线108b、导体层106b与接垫102c可为一体成形。导线108c耦接在导体层106c与接垫102a之间。导线108c、导体层106c与接垫102a可为一体成形。导线108d耦接在导体层106d与接垫102d。导线108d、导体层106d与接垫102d可为一体成形。导线108e耦接在导体层106e与接垫102b之间。导线108e、导体层106e与接垫102b可为一体成形。导线108f耦接在导体层106f与接垫102c之间。导线108f、导体层106f与接垫102c可为一体成形。导线108g耦接在导体层106g与接垫102b之间。导线108g、导体层106g与接垫102b可为一体成形。导线108h耦接在导体层106h与接垫102d之间。导线108h、导体层106h与接垫102d可为一体成形。导线108a~108h的材料例如是铜(Cu)、铝(Al)、镍(Ni)或金(Au)。
耦接至相同接垫的导线可为彼此分离或具有共用部分(shared portion)。以下,以导线108a、108c、108e、108g为例来进行说明。在本实施例中,导线108a与导线108c耦接至相同接垫102a且彼此分离,但本发明并不以此为限。在其他实施例中,耦接至相同接垫102a的导线108a与导线108c可具有共用部分。在本实施例中,导线108e与导线108g耦接至相同接垫102b且具有共用部分,但本发明并不以此为限。在其他实施例中,耦接至相同接垫102b的导线108e与导线108g可彼此分离。
此外,重布线层结构100还可包括接垫102e与接垫102f。接垫102e耦接至接垫102c。接垫102f耦接至接垫102d。接垫102e与接垫102f可用以作为接合垫(bond pad)。接垫102e与接垫102f的材料例如是铜(Cu)、铝(Al)、镍(Ni)或金(Au)。
另外,重布线层结构100还可包括导线108i与导线108j。导线108i耦接在接垫102c与接垫102e之间。导线108i、接垫102c与接垫102e可为一体成形。导线108j耦接在接垫102d与接垫102f之间。导线108j、接垫102d与接垫102f可为一体成形。导线108i与导线108j的材料例如是铜(Cu)、铝(Al)、镍(Ni)或金(Au)。
另一方面,重布线层结构100还可包括至少一个虚拟接垫。举例来说,重布线层结构100可包括虚拟接垫110a、虚拟接垫110b、虚拟接垫110c与虚拟接垫110d,但本发明并不以此为限。虚拟接110a~110d分离于接垫102a~102f、开关元件104a~104d与导线108a~108j。虚拟接垫110a~110d可用以支撑导电连接件(如,焊球)(未示出)。
基于上述,在上述实施例的重布线层结构100中,可通过将开关元件104a、开关元件104b、开关元件104c与开关元件104d分别设定为“开启状态(on state)”或“关闭状态(off state)”来决定接垫之间的耦接关系。如此一来,可以通过相同的重布线层结构100来实现多种重布线层的接线方式,因此可有效地减少光罩的数量,进而降低生产成本。
图2为本发明一实施例的半导体封装的侧视图。在图2中省略部分构件与符号,以清楚地说明导电连接件114a、114b、114e、114f以及耦接至导电连接件114a、114b、114e、114f的构件之间的配置关系。图3为图2中的设置在晶粒上的重布线层结构的上视图。图4为将图3的其中一个晶粒进行翻转后的重布线层结构的示意图。
请参照图1至图4,半导体封装10包括晶粒112a、晶粒112b、重布线层结构100a与重布线层结构100b。在本实施例中,上述重布线层结构100是以应用于半导体封装10为例来进行说明,但本发明并不以此为限。
重布线层结构100可应用于任何半导体封装10,以弹性地设计重布线层的接线方式。半导体封装10例如是双晶粒封装(dual die package,DDP),但本发明并不以此为限。在本实施例中,半导体封装10是以覆晶封装(flip chip package,FCP)为例来进行说明。
重布线层结构100a设置在晶粒112a上。重布线层结构100b设置在晶粒112b上。重布线层结构100a与重布线层结构100b分别包括上述重布线层结构100。亦即,重布线层结构100a与重布线层结构100b包括重布线层结构100的所有构件。重布线层结构100a的接垫102a与重布线层结构100a的接垫102b可耦接至晶粒112a。重布线层结构100b的接垫102a与重布线层结构100b的接垫102b可耦接至晶粒112b。此外,重布线层结构100中的各构件的材料、设置方式与功效已于上述实施例进行详尽地说明,于此不再说明。
重布线层结构100a与重布线层结构100b位于晶粒112a与晶粒112b之间且彼此耦接。举例来说,重布线层结构100a的接垫102c可耦接至重布线层结构100b的接垫102d,且重布线层结构100a的接垫102d可耦接至重布线层结构100b的接垫102c。
半导体封装10还可包括导电连接件114a、导电连接件114b、导电连接件114c、导电连接件114d、导电连接件114e、导电连接件114f、基板116、接合线118a、接合线118b与包封体120中的至少一者。导电连接件114a~114f例如是焊球、导电柱(conductive pillars)(如,铜柱(copper pillar))或其组合等。在本实施例中,导电连接件114a~114f是以焊球为例来进行说明,但本发明并不以此为限。
导电连接件114a耦接在重布线层结构100a的导体层106c与重布线层结构100a的导体层106d之间。藉此,在重布线层结构100a中,开关元件104b为“开启状态”,且接垫102a与接垫102d彼此耦接。导电连接件114b耦接在重布线层结构100a的导体层106e与重布线层结构100a的导体层106f之间。藉此,在重布线层结构100a中,开关元件104c为“开启状态”,且接垫102b与接垫102c彼此耦接。此外,在重布线层结构100a中,由于开关元件104a与开关元件104d为“关闭状态”,因此接垫102a与接垫102c未彼此耦接,且接垫102b与接垫102d未彼此耦接。
导电连接件114c耦接在重布线层结构100b的导体层106a与重布线层结构100b的导体层106b之间。藉此,在重布线层结构100b中,开关元件104a为“开启状态”,且接垫102a与接垫102c彼此耦接。导电连接件114d耦接在重布线层结构100b的导体层106g与重布线层结构100b的导体层106h之间。藉此,在重布线层结构100b中,开关元件104d为“开启状态”,且接垫102b与接垫102d彼此耦接。此外,在重布线层结构100b中,由于开关元件104b与开关元件104c为“关闭状态”,因此接垫102a与接垫102d未彼此耦接,且接垫102b与接垫102c未彼此耦接。
导电连接件114e耦接在重布线层结构100a的接垫102c与重布线层结构100b的接垫102d之间。导电连接件114f耦接在重布线层结构100a的接垫102d与重布线层结构100b的接垫102c之间。藉此,重布线层结构100a与重布线层结构100b可彼此耦接。
如此一来,重布线层结构100a的接垫102a与重布线层结构100b的接垫102a可彼此耦接,且重布线层结构100a的接垫102b与重布线层结构100b的接垫102b可彼此耦接。此外,由于重布线层结构100可用以实现多种重布线层的接线方式,所以晶粒112a与晶粒112b可通过具有相同重布线层布局图案的重布线层结构100a与重布线层结构100b而彼此耦接,因此可有效地减少光罩的数量,且可降低生产成本。
此外,重布线层结构100a的虚拟接垫110b可用以支撑导电连接件114c。重布线层结构100a的虚拟接垫110c可用以支撑导电连接件114d。重布线层结构100b的虚拟接垫110a可用以支撑导电连接件114a。重布线层结构100b的虚拟接垫110d可用以支撑导电连接件114b。
晶粒112a与晶粒112b可堆叠在基板116上。晶粒112b可位于晶粒112a与基板116之间,但本发明并不以此为限。此外,基板116可具有彼此相对的第一面S1与第二面S2。晶粒112a与晶粒112b可位于第一面S1上。基板116例如是封装基板(package substrate),如印刷电路板(printed circuit board,PCB)。
接合线118a与接合线118b可用以将重布线层结构100b耦接至基板116,但本发明并不以此为限。举例来说,接合线118a可耦接在重布线层结构100b的接垫102e与基板116之间,且接合线118b可耦接在重布线层结构100b的接垫102f与基板116之间。
包封体120包封晶粒112a与晶粒112b。因此,包封体120可用以保护晶粒112a与晶粒112b。包封体120包括模制化合物(molding compound)、树脂(如,环氧树脂(epoxy))或其组合等。
在本实施例中,半导体封装10是以包括一个重布线层结构100a与一个重布线层结构100b为例来进行说明,但本发明并不以此为限。在其他实施例中,半导体封装10可包括设置在晶粒112a上的多个重布线层结构100a与设置在晶粒112b上的多个重布线层结构100b。
在一些实施例中,半导体封装10还可包括所属技术领域所周知的其他构件(如,凸块下金属(under bump metallization,UBM)层(未示出)或位于基底116的第二面S2上的至少一个导电连接件(未示出)),于此不再说明。
基于上述,在上述实施例的半导体封装10中,由于重布线层结构100可用以实现多种重布线层的接线方式,所以晶粒112a与晶粒112b可通过具有相同重布线层布局图案的重布线层结构100a与重布线层结构100b而彼此耦接,因此可有效地减少光罩的数量,且可降低生产成本。
综上所述,在上述实施例的重布线层结构与半导体封装中,可通过相同的重布线层结构来实现多种重布线层的接线方式,因此可有效地减少光罩的数量,进而降低生产成本。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的更改与润饰,故本发明的保护范围当视权利要求所界定的为准。
Claims (18)
1.一种重布线层结构,包括:
彼此分离的第一接垫、第二接垫、第三接垫与第四接垫;
第一开关元件,包括彼此分离的第一导体层与第二导体层,其中所述第一导体层耦接至所述第一接垫,且所述第二导体层耦接至所述第三接垫;
第二开关元件,包括彼此分离的第三导体层与第四导体层,其中所述第三导体层耦接至所述第一接垫,且所述第四导体层耦接至所述第四接垫;
第三开关元件,包括彼此分离的第五导体层与第六导体层,其中所述第五导体层耦接至所述第二接垫,且所述第六导体层耦接至所述第三接垫;
第四开关元件,包括彼此分离的第七导体层与第八导体层,其中所述第七导体层耦接至所述第二接垫,且所述第八导体层耦接至所述第四接垫;
第五接垫,耦接至所述第三接垫;以及
第六接垫,耦接至所述第四接垫。
2.根据权利要求1所述的重布线层结构,还包括:
第一导线,耦接在所述第一导体层与所述第一接垫之间;
第二导线,耦接在所述第二导体层与所述第三接垫之间;
第三导线,耦接在所述第三导体层与所述第一接垫之间;
第四导线,耦接在所述第四导体层与所述第四接垫之间;
第五导线,耦接在所述第五导体层与所述第二接垫之间;
第六导线,耦接在所述第六导体层与所述第三接垫之间;
第七导线,耦接在所述第七导体层与所述第二接垫之间;以及
第八导线,耦接在所述第八导体层与所述第四接垫之间。
3.根据权利要求2所述的重布线层结构,其中
所述第一导线、所述第一导体层与所述第一接垫为一体成形,
所述第二导线、所述第二导体层与所述第三接垫为一体成形,
所述第三导线、所述第三导体层与所述第一接垫为一体成形,
所述第四导线、所述第四导体层与所述第四接垫为一体成形,
所述第五导线、所述第五导体层与所述第二接垫为一体成形,
所述第六导线、所述第六导体层与所述第三接垫为一体成形,
所述第七导线、所述第七导体层、所述第二接垫为一体成形,且
所述第八导线、所述第八导体层与所述第四接垫为一体成形。
4.根据权利要求1所述的重布线层结构,还包括:
第九导线,耦接在所述第三接垫与所述第五接垫之间;以及
第十导线,耦接在所述第四接垫与所述第六接垫之间。
5.根据权利要求4所述的重布线层结构,其中
所述第九导线、所述第三接垫与所述第五接垫为一体成形,且
所述第十导线、所述第四接垫与所述第六接垫为一体成形。
6.根据权利要求1所述的重布线层结构,还包括:
至少一个虚拟接垫,分离于所述第一接垫、所述第二接垫、所述第三接垫、所述第四接垫、所述第一开关元件、所述第二开关元件、所述第三开关元件与所述第四开关元件。
7.一种半导体封装,包括:
第一晶粒;
第二晶粒;
第一重布线层结构,设置在所述第一晶粒上;以及
第二重布线层结构,设置在所述第二晶粒上,其中
所述第一重布线层结构与所述第二重布线层结构分别包括如权利要求1所述的重布线层结构,且
所述第一重布线层结构与所述第二重布线层结构位于所述第一晶粒与所述第二晶粒之间且彼此耦接。
8.根据权利要求7所述的半导体封装,其中所述第一重布线层结构的所述第三接垫耦接至所述第二重布线层结构的所述第四接垫,且所述第一重布线层结构的所述第四接垫耦接至所述第二重布线层结构的所述第三接垫。
9.根据权利要求8所述的半导体封装,还包括:
第一导电连接件,耦接在所述第一重布线层结构的所述第三导体层与所述第一重布线层结构的所述第四导体层之间;以及
第二导电连接件,耦接在所述第一重布线层结构的所述第五导体层与所述第一重布线层结构的所述第六导体层之间。
10.根据权利要求9所述的半导体封装,还包括:
第三导电连接件,耦接在所述第二重布线层结构的所述第一导体层与所述第二重布线层结构的所述第二导体层之间;以及
第四导电连接件,耦接在所述第二重布线层结构的所述第七导体层与所述第二重布线层结构的所述第八导体层之间。
11.根据权利要求8所述的半导体封装,还包括:
第五导电连接件,耦接在所述第一重布线层结构的所述第三接垫与所述第二重布线层结构的所述第四接垫之间;以及
第六导电连接件,耦接在所述第一重布线层结构的所述第四接垫与所述第二重布线层结构的所述第三接垫之间。
12.根据权利要求7所述的半导体封装,其中所述重布线层结构还包括:
第一导线,耦接在所述第一导体层与所述第一接垫之间;
第二导线,耦接在所述第二导体层与所述第三接垫之间;
第三导线,耦接在所述第三导体层与所述第一接垫之间;
第四导线,耦接在所述第四导体层与所述第四接垫之间;
第五导线,耦接在所述第五导体层与所述第二接垫之间;
第六导线,耦接在所述第六导体层与所述第三接垫之间;
第七导线,耦接在所述第七导体层与所述第二接垫之间;以及
第八导线,耦接在所述第八导体层与所述第四接垫之间。
13.根据权利要求12所述的半导体封装,其中
所述第一导线、所述第一导体层与所述第一接垫为一体成形,
所述第二导线、所述第二导体层与所述第三接垫为一体成形,
所述第三导线、所述第三导体层与所述第一接垫为一体成形,
所述第四导线、所述第四导体层与所述第四接垫为一体成形,
所述第五导线、所述第五导体层与所述第二接垫为一体成形,
所述第六导线、所述第六导体层与所述第三接垫为一体成形,
所述第七导线、所述第七导体层、所述第二接垫为一体成形,且
所述第八导线、所述第八导体层与所述第四接垫为一体成形。
14.根据权利要求7所述的半导体封装,其中所述重布线层结构还包括:
第九导线,耦接在所述第三接垫与所述第五接垫之间;以及
第十导线,耦接在所述第四接垫与所述第六接垫之间。
15.根据权利要求14所述的半导体封装,其中
所述第九导线、所述第三接垫与所述第五接垫为一体成形,且
所述第十导线、所述第四接垫与所述第六接垫为一体成形。
16.根据权利要求7所述的半导体封装,其中所述重布线层结构还包括:
至少一个虚拟接垫,分离于所述第一接垫、所述第二接垫、所述第三接垫、所述第四接垫、所述第一开关元件、所述第二开关元件、所述第三开关元件与所述第四开关元件。
17.根据权利要求7所述的半导体封装,还包括:
基底,其中所述第一晶粒与所述第二晶粒堆叠在所述基底上,且所述第二晶粒位于所述第一晶粒与所述基底之间。
18.根据权利要求7所述的半导体封装,还包括:
包封体,包封所述第一晶粒与所述第二晶粒。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/677,604 US10991648B1 (en) | 2019-11-07 | 2019-11-07 | Redistribution layer structure and semiconductor package |
US16/677,604 | 2019-11-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112786551A CN112786551A (zh) | 2021-05-11 |
CN112786551B true CN112786551B (zh) | 2024-01-12 |
Family
ID=74093933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911281915.3A Active CN112786551B (zh) | 2019-11-07 | 2019-12-13 | 重布线层结构与半导体封装 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10991648B1 (zh) |
CN (1) | CN112786551B (zh) |
TW (1) | TWI708334B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11309288B2 (en) * | 2020-04-08 | 2022-04-19 | Nanya Technology Corporation | Electronic system, die assembly and device die |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5308928A (en) * | 1989-11-09 | 1994-05-03 | International Business Machines Corporation | Soldering interconnects for selective line coupling |
CN107644847A (zh) * | 2016-07-20 | 2018-01-30 | 台湾积体电路制造股份有限公司 | 半导体封装 |
TW201919200A (zh) * | 2017-11-07 | 2019-05-16 | 南韓商三星電子股份有限公司 | 扇出型半導體封裝 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6744067B1 (en) * | 2003-01-17 | 2004-06-01 | Micron Technology, Inc. | Wafer-level testing apparatus and method |
KR100541393B1 (ko) * | 2003-04-26 | 2006-01-10 | 삼성전자주식회사 | 멀티칩 bga 패키지 |
US7071421B2 (en) * | 2003-08-29 | 2006-07-04 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
TWI251861B (en) * | 2005-06-16 | 2006-03-21 | Etron Technology Inc | Re-entrant Routing method and circuit structure |
KR102053349B1 (ko) * | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
KR102320046B1 (ko) * | 2014-09-19 | 2021-11-01 | 삼성전자주식회사 | 캐스케이드 칩 스택을 갖는 반도체 패키지 |
WO2016099523A1 (en) * | 2014-12-19 | 2016-06-23 | Intel IP Corporation | Stacked semiconductor device package with improved interconnect bandwidth |
US10115709B1 (en) * | 2017-07-07 | 2018-10-30 | Micron Technology, Inc. | Apparatuses comprising semiconductor dies in face-to-face arrangements |
KR102071457B1 (ko) * | 2018-03-13 | 2020-01-30 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
-
2019
- 2019-11-07 US US16/677,604 patent/US10991648B1/en active Active
- 2019-11-13 TW TW108141099A patent/TWI708334B/zh active
- 2019-12-13 CN CN201911281915.3A patent/CN112786551B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5308928A (en) * | 1989-11-09 | 1994-05-03 | International Business Machines Corporation | Soldering interconnects for selective line coupling |
CN107644847A (zh) * | 2016-07-20 | 2018-01-30 | 台湾积体电路制造股份有限公司 | 半导体封装 |
TW201919200A (zh) * | 2017-11-07 | 2019-05-16 | 南韓商三星電子股份有限公司 | 扇出型半導體封裝 |
Also Published As
Publication number | Publication date |
---|---|
US20210143091A1 (en) | 2021-05-13 |
CN112786551A (zh) | 2021-05-11 |
TWI708334B (zh) | 2020-10-21 |
US10991648B1 (en) | 2021-04-27 |
TW202119565A (zh) | 2021-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8134240B2 (en) | Semiconductor device and manufacturing method for the same | |
KR101429344B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
US8703599B2 (en) | Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts | |
US20120199981A1 (en) | Semiconductor device and method of fabricating the semiconductor device | |
KR101478247B1 (ko) | 반도체 패키지 및 이를 이용한 멀티 칩 패키지 | |
CN102543923A (zh) | 半导体器件及其制造方法 | |
US7939928B2 (en) | Method and apparatus for stacked die package with insulated wire bonds | |
US20200343163A1 (en) | Semiconductor device with through-mold via | |
US20150155202A1 (en) | Power/ground layout for chips | |
CN112786551B (zh) | 重布线层结构与半导体封装 | |
JP4137929B2 (ja) | 半導体装置 | |
US20160141272A1 (en) | Semiconductor device and method of manufacturing same | |
KR101685068B1 (ko) | 시스템 인 패키지 및 이의 제조방법 | |
US9721928B1 (en) | Integrated circuit package having two substrates | |
CN115706087A (zh) | 半导体封装 | |
US20100140773A1 (en) | Stacked chip, micro-layered lead frame semiconductor package | |
JP3625714B2 (ja) | 半導体装置 | |
US20240071996A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
US9190370B2 (en) | Semiconductor device utilizing redistribution layers to couple stacked die | |
CN213093192U (zh) | 一种ubm跨越式连接rdl的芯片封装结构 | |
TWI788045B (zh) | 扇出型封裝結構及其製造方法 | |
CN101150105A (zh) | 半导体器件及其制造方法 | |
JP2023175671A (ja) | 半導体パッケージ及び製造方法 | |
KR20140130926A (ko) | 팬아웃 타입 시스템 인 패키지 | |
KR20220001292A (ko) | 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |