CN107644860A - 集成扇出型封装 - Google Patents

集成扇出型封装 Download PDF

Info

Publication number
CN107644860A
CN107644860A CN201610889696.7A CN201610889696A CN107644860A CN 107644860 A CN107644860 A CN 107644860A CN 201610889696 A CN201610889696 A CN 201610889696A CN 107644860 A CN107644860 A CN 107644860A
Authority
CN
China
Prior art keywords
conductive pole
conductive
line structure
crystal grain
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610889696.7A
Other languages
English (en)
Inventor
黄见翎
谢静华
廖信宏
黄英叡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107644860A publication Critical patent/CN107644860A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15332—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种集成扇出型封装，包括晶粒、第一重配置线路结构、第二重配置线路结构、多个焊点、多个导电柱以及绝缘包封体。第一重配置线路结构与第二重配置线路结构分别形成在所述晶粒的背面与有源表面上，以将所述晶粒夹在其中。焊点形成在所述晶粒旁且与所述第一重配置线路结构连接。导电柱分别形成在所述焊点上且与所述第二重配置线路结构连接，并通过所述焊点与所述第一重配置线路结构连接。绝缘包封体包封所述晶粒的多个侧壁、所述导电柱的多个侧壁以及所述焊点的多个侧壁。

Description

集成扇出型封装
技术领域
本发明实施例涉及一种集成扇出型封装。
背景技术
由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度不断提升，因此，半导体工业快速成长。近年来，这种集成密度的提升，大多因为最小特征尺寸的持续缩小，因此可以将更多的组件集成在一定的区域中。相较于以前的封装体，这些较小的电子组件也仅需要使用较小面积的较小封装体。半导体组件中的一些较小型式的封装包括有四面扁平封装(quad flat packages，QFPs)、针栅数组(pin grid array，PGA)封装、球栅数组(ball grid array，BGA)封装等。
目前，集成扇出型封装由于其密度而趋于热门。如何减少集成扇出型封装的制造成本将成为重要的议题。
发明内容
本发明实施例提供一种集成扇出型封装包括晶粒(die)、第一重配置线路结构、第二重配置线路结构、多个焊点、多个导电柱以及绝缘包封体。第一重配置线路结构与第二重配置线路结构分别形成在所述晶粒的背面与有源表面上，以将所述晶粒夹在其中。焊点形成在所述晶粒旁且与所述第一重配置线路结构连接。导电柱分别形成在所述焊点上且与所述第二重配置线路结构连接，并通过所述焊点与所述第一重配置线路结构连接。绝缘包封体包封所述晶粒的多个侧壁、所述导电柱的多个侧壁以及所述焊点的多个侧壁。
附图说明
图1至图15为依照本发明一些实施例的一种集成扇出型封装的制造过程的各种阶段的剖面示意图；
图16A至图16C为图8的集成扇出型封装的制造过程的各种阶段的立体示意图；
图17A至图17C为图16C的A-A’切线的集成扇出型封装的制造过程的各种阶段的剖面示意图；
图18为依照本发明的替代实施例的一种模板的剖面示意图；
图19为图8的导电柱的放大部分剖面示意图。
附图标号说明：
10：模板
12a、12b：孔洞；
100：集成扇出型封装；
102：第一重配置线路结构；
102a：第一介电层；
102b、102c：第一重配置导电层；
104、104a：晶种层；
106：图案化光刻胶层；
107：焊膏；
108、108a、108b：焊点；
110、110a、110b、110c：导电柱；
111a：表面；
111b、113d、114a：上表面；
112：晶粒；
112a：有源表面；
112b：接垫；
112c：钝化层；
112d：导电柱；
112f：背面；
114：绝缘包封体；
116：第二重配置线路结构；
116a：第二介电层；
116b：第二重配置导电层；
116b1：球底金属图案；
116b2：连接接垫；
118：导电端子；
120：无源组件；
122：接触开口；
124：导电端子；
130：导电结构；
200：封装；
AD：黏胶；
C：载体；
DB：剥离层；
R：凹陷；
S108：弧形侧壁；
S110：侧壁；
W1、W3：下部宽度；
W2、W4：上部宽度；
ΔH：水平高度差；
t1：深度；
t2：厚度；
t3：高度。
具体实施方式
以下揭示内容提供用于实施所提供的目标的不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，在以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且也可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。为了简单及清楚起见，各种特征可任意地示出为不同尺寸。此外，本发明在各种实例中可重复使用组件标号和/或字母。组件标号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例和/或配置本身之间的关系。
另外，为了易于描述附图中所示出的一个构件或特征与另一组件或特征的关系，本文中可使用例如“在...下”、“在...下方”、“下部”、“在…上方”、“上部”及类似术语的空间相对术语。除了附图中所示出的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
图1至图15为依照本发明一些实施例的一种集成扇出型封装的制造过程的各种阶段的剖面示意图。
请参照图1，提供载体C，载体C具有形成在其上的剥离层(de-bonding layer)DB与第一介电层102a，其中剥离层DB形成在载体C与第一介电层102a之间。在一些实施例中，载体C为玻璃基板，剥离层DB为形成在玻璃基板上的光热转换(light-to-heat conversion，LTHC)离形层，而第一介电层102a为形成在剥离层DB上的光敏聚苯恶唑(photosensitivepolybenzoxazole，PBO)层。在替代实施例中，剥离层DB也可以是在光固化过程中会降低其黏性的光固化离形膜(photo-curable release film)，或者是在热固化过程中会降低其黏性的热固化离形膜(thermal curable release film)。而第一介电层102a也可以由其他的光敏或非光敏介电材料所制成。在一些实施例中，第一介电层102a可以是聚苯恶唑(PBO)层、聚酰亚胺(PI)层或其他合适的介电层。
请参照图2，通过例如物理气相沉积法在第一介电层102a上形成晶种层104。在一些实施例中，物理气相沉积法包括溅镀法、蒸镀法或任何其他合适方法。晶种层104可以是包括铜、铝、钛、上述合金或上述多层的金属晶种层。在一些实施例中，晶种层104包括第一金属层(例如钛层(未示出))以及位在第一金属层上的第二金属层(例如铜层(未示出))。
请参照图3，在形成晶种层104之后，在晶种层104上形成图案化光刻胶层106。图案化光刻胶层106具有多个开口，使得部分晶种层104外露于图案化光刻胶层106的开口。
请参照图4，进行例如电镀工艺以在部分晶种层104上形成第一重配置导电层102b、第一重配置导电层102c。具体来说，第一重配置导电层102b位在第一重配置导电层102c的两旁。第一重配置导电层102b、第一重配置导电层102c被电镀在外露于图案化光刻胶层106的开口的部分晶种层104上。在一些实施例中，第一重配置导电层102b、第一重配置导电层102c可以是金属层，其包括铜、铝、钛或其合金。
请参照图4与图5，在形成第一重配置导电层102b、第一重配置导电层102c之后，剥离图案化光刻胶层106，使得未被第一重配置导电层102b、第一重配置导电层102c所覆盖的部分晶种层104外露。
如图6所示，通过使用第一重配置导电层102b、第一重配置导电层102c当作掩膜，移除未被第一重配置导电层102b、第一重配置导电层102c所覆盖的部分晶种层104，以形成晶种层104a并暴露第一介电层102a的表面。也就是说，被第一重配置导电层102b、第一重配置导电层102c所覆盖的部分晶种层104未被蚀刻并且被留下以形成晶种层104a。第一重配置线路结构102包括第一介电层102a与其上的第一重配置导电层102b、第一重配置导电层102c。在全文中，晶种层的剩余部分104a可视为第一重配置导电层102b、第一重配置导电层102c的底部。在后续附图中，晶种层的剩余部分104a被视为第一重配置导电层102b、第一重配置导电层102c的一部分且不个别示出。
另一方面，如图6所示，虽然图6中仅示出一层第一介电层102a、一层第一重配置导电层102b以及一层第一重配置导电层102c，但本发明不以此为限。在替代实施例中，第一介电层102a与第一重配置导电层102b、第一重配置导电层102c的数量与配置可依产品的设计与需求来进行调整。在形成第一重配置线路结构102之后，另一个介电层可直接形成在第一重配置线路结构102上，然而，另一个介电层的图案化工艺可被省略。
请参照图7与图8，在第一重配置导电层102b上形成多个焊膏107。于焊膏107上分别安置多个导电柱110。接着，进行回焊工艺，焊膏107可经回焊以形成焊点108，且导电柱110可通过焊点108与第一重配置导电层102b接合。参照图7与图8，焊膏107的材料与导电柱110的材料不同。在一些实施例中，焊膏107的熔点小于导电柱110的熔点。在一些实施例中，焊膏107的材料可包括金属材料，其包括锡、银、铜或其合金。焊膏107的形成方法可例如是印刷法、喷涂法或其他合适的方法。导电柱110的材料包括金属，其包括铜或其他合适金属。在一些实施例中，导电柱110为预先制作的(pre-fabricated)且可由材料供货商所提供。
请参照图8，导电结构130包括第一部分与第二部分。第一部分可例如是焊点108，而第二部分可例如是导电柱110。焊点108的侧壁与导电柱110的侧壁具有不同轮廓。在一些实施例中，导电柱110具有直线型(straight)的侧壁，而焊点108具有锥形(tapered)的侧壁(如图8所示)，或者是导电柱110c具有阶梯型(stepped)的侧壁，而焊点108具有弧形的侧壁(arc-sidewalls)(如图19所示)。
图16A至图16C为图8的集成扇出型封装的制造过程的各种阶段的立体示意图。详细地说，如图16A与图16B所示，在模板10上提供多个预制的导电柱110a，并将导电柱110a放置在模板10的多个孔洞12a中。在一些实施例中，预制的导电柱110a包括铜柱或其他合适的金属柱。举例来说，通过振动机器(vibration machine)振动模板10，使得预制的导电柱110a可部分插入模板10的孔洞12a中。由于导电柱110a是预先制作的，因此，容易制造出具有预定高宽比的导电柱110a。此外，由于导电柱110a不需要通过溅镀工艺、光刻工艺、电镀工艺以及光刻胶剥除工艺来制造，因此，可减少导电柱110a的制造成本与制造周期(fabrication cycle time)。
在一些实施例中，导电柱110a可被预先制作。预制的导电柱110a的特性(例如宽度、高度、形状、导电性等)可事先检查。因此，导电柱110a的生产良率可被提升。
请参照图16B与图16C，将载体C倒置(flipped)在模板10上(也就是说将载体C上下翻转)。后续步骤请参照图17A至图17C。
图17A至图17C为图16C的A-A’切线的集成扇出型封装的制造过程的各种阶段的剖面示意图。图18为依照本发明的替代实施例的一种模板的剖面示意图。如图17A与图17B所示，倒置的载体C上的焊膏107面向模板10的孔洞12a中的导电柱110a，使得焊膏107对准模板10的孔洞12a中的导电柱110a。在一些实施例中，导电柱110a可以是I型导电柱且配置在图17A的由盲孔所形成的孔洞12a中。在替代实施例中，如图18所示，导电柱110b也可以是T型导电柱(如图19所示)或其他合适形状且容易制造的导电柱，其配置在由通孔所形成的孔洞12b中。
接着，如图17B与图17C所示，将倒置的载体C上的焊膏107与导电柱110a的表面111a接触。之后，进行回焊工艺，使得焊膏107经回焊以形成焊点108，且导电柱110a通过焊点108固定在第一重配置导电层102b上(如图17C所示)。由于焊膏107的熔点小于导电柱110a的熔点，因此，当回焊温度达到焊膏107的熔点时，焊膏107会先熔融，以达到接合功效。此时，导电柱110a仍维持其形状而不熔融。
在替代实施例中，当载体C倒置并接合在模板10上时，第一重配置导电层102c并未与模板10的上表面接触。在第一重配置导电层102b与导电柱110a的表面111a接合后，驱动载体C向上移动并从模板10的孔洞12a中拉出导电柱110a。焊点108提供足够的附着力以从模板10的孔洞12a中拉出导电柱110a，使得导电柱110a转移接合(transfer-bonded)至第一重配置导电层102b。然后，再次将载体C上下翻转，如图17C所示，使得固定在第一重配置导电层102b上的导电柱110a的表面111a面向下(也就是说朝向载体C)，而导电柱110a的表面111b面向上变成上表面111b。
如图17B与图17C所示，由于模板10的孔洞12a具有平坦的下表面且预制的导电柱110a具有相似或相同的高度，因此，图17C的导电柱110a的上表面111b的共面性比习知电镀后的导电柱好。在安置导电柱110a之后，多个导电柱110a的上表面111b实质上共平面，而不需要进行后续导电柱110a的研磨工艺。如此一来，可进一步地减少本发明实施例的集成扇出型封装的制造成本与制造周期。
图19为图8的导电柱的放大部分剖面示意图。请参照图19，将导电柱110c从模板10转移接合至第一重配置导电层102b之后，导电柱110c的底部可位在焊点108a上或内埋于焊点108b中。导电柱110c下方的焊点108b的厚度t2可小于导电柱110c的高度t3。导电柱110c的高度t3可例如是100微米(μm)至500微米，而导电柱110c下方的焊点108b的厚度t2可例如是2微米至10微米。在一些实施例中，t2/t3的比值为0.004至0.1。在一些实施例中，导电柱110c的底部的内埋深度t1可小于导电柱110c的高度t3的三分之一。也就是说，t1/t3的比值小于三分之一。在一些实施例中，导电柱110c的底部的内埋深度t1可小于30微米。在替代实施例中，导电柱110c的底部的内埋深度t1可小于10微米。多个导电柱110c之间的上表面111b的水平高度差(level height different)ΔH可小于10微米。此水平高度差ΔH可视为共平面，而不影响后续工艺，因此，导电柱110c的研磨工艺可被省略。
详细地说，如图19所示，焊点108a、108b中的至少一者具有弧形侧壁S108，其朝着相对应的焊点108a、108b的中心凹陷。以焊点108a为例，焊点108a具有锥形(tapered)侧壁S108。焊点108a的水平截面积自第一重配置导电层102b往对应的导电柱110c的方向渐缩。在一些实施例中，焊点108a的上部宽度W2等于位在焊点108a上的导电柱110c的下部宽度W1，而焊点108a的下部宽度W3大于位在焊点108a上的导电柱110c的下部宽度W1。在替代实施例中，由于焊点108b覆盖对应的导电柱110c的侧壁S110的一部分，因此，焊点108b的上部宽度W4大于位在焊点108b上的导电柱110c的下部宽度W1，其中上部宽度W4位在焊点108b与导电柱110c之间的界面处。换言之，在回焊工艺之后，焊点108b的顶面具有凹陷R。凹陷R的深度t1可例如小于10微米。导电柱110c的底部可部分插入所述凹陷R中。
请回头参照图8与图9，通过黏胶(adhesive)AD将晶粒112安置在第一重配置导电层102c上。在一些实施例中，晶粒112可通过黏胶AD直接接合至第一重配置导电层102c上。黏胶AD填入第一重配置导电层102c中的开口并覆盖第一重配置导电层102c的上表面。因此，晶粒112通过黏胶AD与第一重配置导电层102c电性绝缘。在一些实施例中，黏胶AD可以是芯片贴覆膜(die attach film，DAF)或线路上覆膜(film over wire，FoW)。晶粒112具有有源表面112a以及相对于有源表面112a的背面112f。在一些实施例中，晶粒112包括多个接垫112b、钝化层112c以及多个导电柱112d。钝化层112c覆盖有源表面112a以及部分接垫112b。接垫112b部分外露于钝化层112c。导电柱112d形成在接垫112b上，并与接垫112b电性连接。晶粒112的背面112f与黏胶AD接触。导电柱112d可例如是铜柱或其他合适的金属柱。
在图9中，虽然只有一个晶粒112安置在第一重配置导电层102c上。然而，晶粒112的数量仅是用以说明，本发明不限于此。在替代实施例中，可将多个晶粒112安置在第一重配置导电层102c上，且安置在第一重配置导电层102c上的晶粒112可排列成数组(array)。当多个晶粒112安置在第一重配置导电层102c上，多个导电柱110的群组可被安置在第一重配置导电层102b上，且导电柱110的群组中的一者环绕各晶粒112。
参照图10，在载体C上形成绝缘材料(未示出)以覆盖焊点108、导电柱110以及晶粒112的表面。在一些实施例中，绝缘材料可以是通过模制工艺(molding process)所形成的模制化合物(molding compound)。在一些实施例中，绝缘材料可包括环氧化合物或其他适合的材料。接着，研磨绝缘材料以及部分晶粒112以暴露出导电柱112d的上表面113d。研磨绝缘材料之后，绝缘包封体114形成在第一重配置线路结构102上，以包封晶粒112的侧壁、导电柱110的侧壁以及焊点108的侧壁。在一些实施例中，在上述研磨工艺期间，部分绝缘材料、部分导电柱112d以及部分导电柱110被移除，以暴露导电柱112d的上表面113d与导电柱110的上表面111b。在一些实施例中，绝缘包封体114可通过机械研磨法和/或化学机械研磨法(CMP)形成。
绝缘包封体114包封晶粒112的侧壁以及导电结构130的侧壁。换言之，导电结构130与晶粒112内埋在绝缘包封体114中。也就是说，导电结构130(其包括焊点108与导电柱110)贯穿绝缘包封体114，且暴露出导电柱110的上表面111b。需注意的是，在经过研磨工艺后，导电柱110的上表面111b、导电柱112d的上表面113d以及绝缘包封体114的上表面114a实质上共平面。
在替代实施例中，由于导电柱110的上表面111b之间的共面性够好，因此，研磨工艺可被省略。详细地说，当晶粒112安置在第一重配置导电层102c上之后，导电柱110的上表面111b以及导电柱112d的上表面113d实质上共平面。可将离形膜(未示出)附着在导电柱110的上表面111b以及导电柱112d的上表面113d上。接着，利用模具固定具有离形膜、晶粒112以及导电柱110的载体C。之后，将绝缘材料填入离形膜、晶粒112以及导电柱110之间的空隙，并接着固化，以形成绝缘包封体114。换言之，离形膜可避免绝缘包封体114附着在导电柱110的上表面111b以及导电柱112d的上表面113d上。因此，本发明实施例可省略研磨工艺，以减少制造成本与制造周期。
请参照图11，在形成绝缘包封体114之后，在导电柱110的上表面111b上、绝缘包封体114的上表面114a上以及导电柱112d的上表面113d上形成第二重配置线路结构116。如图11所示，第二重配置线路结构116包括交替叠层的多个第二介电层116a以及多个第二重配置导电层116b。第二重配置导电层116b与晶粒112的导电柱112d以及导电柱110电性连接。也就是说，导电结构130(其包括焊点108与导电柱110)电性连接第一重配置线路结构102与第二重配置线路结构116。在一些实施例中，导电柱112d的上表面113d以及导电柱110的上表面111b接触第二重配置线路结构116的最底的第二重配置导电层116b。最底部的第二介电层116a部分覆盖导电柱112d的上表面113d以及导电柱110的上表面111b。此外，最顶的第二重配置导电层116b具有多个接垫。在一些实施例中，上述接垫包括多个球底金属(under-ball metallurgy，UBM)图案116b1和/或至少一个连接接垫116b2。UBM图案116b1可用以安置焊球，而连接接垫116b2可用以安置无源组件(passive components)。UBM图案116b1以及连接接垫116b2的数量不限于本发明。
请参照图12，在形成第二重配置线路结构116之后，在UBM图案116b1上安置多个导电端子(conductive terminals)118，并在连接接垫116b2上安置多个无源组件120。在一些实施例中，可通过植球工艺将导电端子118安置在UBM图案116b1上，并可通过焊接工艺或回焊工艺将无源组件120安置在连接接垫116b2上。
请参照图12与图13，在第二重配置线路结构116上安置导电端子118与无源组件120之后，将第一介电层102a与剥离层DB剥离，使得第一介电层102a与剥离层DB以及载体C分离或分层。在一些实施例中，剥离层DB(例如是光热转换释放层)可通过照射紫外光激光，以使第一介电层102a与载体C剥离。
如图13所示，接着，图案化第一介电层102a，以形成多个接触开口122并暴露出第一重配置导电层102b的下表面。在一些实施例中，第一介电层102a中的接触开口122的数量对应于第一重配置导电层102b的数量。
请参照图14，在第一介电层102a中形成接触开口122之后，多个导电端子124(例如是导电球)被放置在外露于接触开口122的第一重配置导电层102b的下表面上。在一些实施例中，导电端子124(例如是导电球)可被回焊以固定在第一重配置导电层102b的被暴露的表面上。换句话说，导电端子124与第一重配置导电层102b电性连接。如图14所示，在形成导电端子118、124之后，可完成具有双侧端子(dual-side terminals)的集成扇出型封装100。
请参照图15，接着提供另一种封装200。在一些实施例中，封装200可以是存储元件。封装200通过导电端子124叠层并电性连接至图14的集成扇出型封装100，以制造出叠层式封装(package-on-package，POP)结构。
根据一些实施例，晶粒可通过黏胶直接安置在第一重配置线路结构上。另外，晶粒的背面上的第一重配置线路结构以及晶粒的有源面上的第二重配置线路结构可通过多个焊点与多个导电柱相互连接。导电柱可通过焊点安置在第一重配置线路结构上。焊点形成在第一重配置线路结构与导电柱之间，以提升导电柱的上表面之间的共面性。
根据一些实施例，一种集成扇出型封装包括晶粒、第一重配置线路结构、第二重配置线路结构、多个焊点、多个导电柱以及绝缘包封体。第一重配置线路结构与第二重配置线路结构分别形成在所述晶粒的背面与有源表面上，以将所述晶粒配置在上述两者之间。焊点形成在所述晶粒旁且与所述第一重配置线路结构连接。导电柱分别形成在所述焊点上且与所述第二重配置线路结构连接，并通过所述焊点与所述第一重配置线路结构连接。绝缘包封体包封所述晶粒的多个侧壁、所述导电柱的多个侧壁以及所述焊点的多个侧壁。
根据一些实施例，所述晶粒通过黏胶与所述第一重配置线路结构接合。所述焊点的材料与所述导电柱的材料不同。所述导电柱下方的所述焊点的厚度小于所述导电柱的高度。所述焊点的至少一者具有多个弧形侧壁或多个锥形侧壁。各所述焊点的上部宽度大于或等于各所述导电柱的下部宽度，而各所述焊点的下部宽度大于各所述导电柱的下部宽度。所述焊点的至少一者的水平截面积往相对应的导电柱渐缩。所述导电柱包括I型导电柱、T型导电柱或其组合。所述焊点的至少一者覆盖相对应的导电柱的多个侧壁的一部分。
根据一些实施例，一种集成扇出型封装包括晶粒、第一重配置线路结构、第二重配置线路结构、绝缘包封体、多个导电结构、多个第一导电端子以及多个第二导电端子。第一重配置线路结构形成在晶粒的背面上。第二重配置线路结构形成在晶粒的有源表面上。绝缘包封体形成在晶粒旁，以包封晶粒。导电结构贯穿绝缘包封体。所述导电结构的至少一者包括第一部分与位在第一部分上的第二部分。第一部分与第一重配置线路结构电性连接。第二部分与第二重配置线路结构电性连接，并通过第一部分与第一重配置线路结构电性连接。第一部分的材料与第二部分的材料不同。第一导电端子与第二重配置线路结构电性连接。第二导电端子与第一重配置线路结构电性连接。
根据一些实施例，所述第一部分的熔点低于所述第二部分的熔点。所述第一部分具有多个弧形侧壁或多个锥形侧壁。所述晶粒通过黏胶与所述第一重配置线路结构接合。所述第一部分还覆盖所述第二部分的多个侧壁的一部分。
根据一些实施例，一种集成扇出型封装的制造方法，其步骤如下。在载体上形成第一重配置线路结构。第一重配置线路结构包括第一介电层以及位在第一介电层上的多个第一重配置导电层。在第一重配置导电层的一部分上形成多个焊点。通过多个焊点将多个导电柱分别安置在所述第一重配置导电层上。通过黏胶将晶粒安置在第一重配置导电层的另一部分上。形成绝缘包封体，以包封晶粒的多个侧壁、导电柱的多个侧壁以及焊点的多个侧壁。在绝缘包封体、晶粒以及导电柱上形成第二重配置线路结构。将第二重配置线路结构电性连接至晶粒以及导电柱。移除载体。
根据一些实施例，在所述焊点上安置所述导电柱的方法包括将所述导电柱分别放置在模板的多个孔洞中；在所述载体的所述第一重配置导电层的一部分上形成多个焊膏；将具有所述焊膏的所述载体倒置在所述模板上，以将所述载体的所述焊膏对齐所述模板的所述孔洞中的所述导电柱；以及对所述焊膏进行回焊工艺，以形成所述焊点并将所述导电柱固定在所述焊点上。所述模板的所述孔洞包括多个盲孔或多个通孔。进行所述回焊工艺之后，所述导电柱的多个上表面实质上共平面。进行所述回焊工艺之后，所述导电柱之间的上表面的水平高度差小于10微米。所述集成扇出型封装的制造方法，更包括在移除所述载体之前，在所述第二重配置线路结构上分别形成多个第一导电端子；以及在移除所述载体之后，图案化所述第一介电层，以暴露所述第一重配置导电层的多个表面，且在所述第一重配置导电层的被暴露的表面上形成多个第二导电端子。
虽然本实施例及其优点已详细说明如上，本领域技术人员应理解，在不悖离所附权利要求书限定的实施例的精神和范畴内可对本文做出各种改变、置换以及变更。另外，本发明的范畴并不限于本文中所述的工艺、机器、制造、物质组成、构件、方法、操作以及步骤的特定实施例。本领域技术人员将容易从本发明中理解现今存在或往后研发的工艺、机器、制造、物质组成、构件、方法、操作或步骤，如本文中所描述的对应实施例可根据本发明使用，以进行实质上相同功能或达到实质上相同效果。因此，所附权利要求书的范围旨在包括例如工艺、机器、制造、物质组成、构件、方法、操作或步骤的范畴。此外，构成单独实施例的每个申请专利范围以及各种申请专利范围与实施例的组合皆为本发明的范围。
以上概述了数个实施例的特征，使本领域普通技术人员可更佳了解本发明的实施例。本领域普通技术人员应理解，其可轻易地使用本发明作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的和/或达到相同优点。本领域普通技术人员还应理解，这种等效的设置并不悖离本发明的精神与范畴，且本领域普通技术人员在不悖离本发明的精神与范畴的情况下可对本文做出各种改变、置换以及改变。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的改动与润饰，均在本发明范围内。

Claims (1)

1.一种集成扇出型封装，其特征在于，包括：
晶粒；
第一重配置线路结构与第二重配置线路结构，分别位在所述晶粒的背面与有源表面上，以将所述晶粒夹在其中；
多个焊点，位在所述晶粒旁且与所述第一重配置线路结构连接；
多个导电柱，分别位在所述焊点上且与所述第二重配置线路结构连接，并通过所述焊点与所述第一重配置线路结构连接；以及
绝缘包封体，包封所述晶粒的多个侧壁、所述导电柱的多个侧壁以及所述焊点的多个侧壁。
CN201610889696.7A 2016-07-21 2016-10-12 集成扇出型封装 Pending CN107644860A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/215,598 US9984960B2 (en) 2016-07-21 2016-07-21 Integrated fan-out package and method of fabricating the same
US15/215,598 2016-07-21

Publications (1)

Publication Number Publication Date
CN107644860A true CN107644860A (zh) 2018-01-30

Family

ID=60990103

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610889696.7A Pending CN107644860A (zh) 2016-07-21 2016-10-12 集成扇出型封装

Country Status (3)

Country Link
US (1) US9984960B2 (zh)
CN (1) CN107644860A (zh)
TW (1) TW201804575A (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10347574B2 (en) * 2017-09-28 2019-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US10573573B2 (en) 2018-03-20 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and package-on-package structure having elliptical conductive columns
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
US10825773B2 (en) * 2018-09-27 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with reinforcement structures in a redistribution circuit structure and method of manufacturing the same
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
CN110034061B (zh) 2019-04-24 2021-05-14 京东方科技集团股份有限公司 芯片转移方法、芯片及目标基板
US11862587B2 (en) * 2019-07-25 2024-01-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US20220328394A1 (en) * 2021-04-07 2022-10-13 Mediatek Inc. Three-dimensional pad structure and interconnection structure for electronic devices

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418857A (en) * 1980-12-31 1983-12-06 International Business Machines Corp. High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
US4672739A (en) * 1985-04-11 1987-06-16 International Business Machines Corporation Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US6555757B2 (en) * 2000-04-10 2003-04-29 Ngk Spark Plug Co., Ltd. Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8669651B2 (en) * 2010-07-26 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structures with reduced bump bridging
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8975741B2 (en) * 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9443797B2 (en) * 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
KR101538573B1 (ko) * 2014-02-05 2015-07-21 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
KR101634067B1 (ko) * 2014-10-01 2016-06-30 주식회사 네패스 반도체 패키지 및 그 제조방법
US9461018B1 (en) * 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9520385B1 (en) * 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same

Also Published As

Publication number Publication date
TW201804575A (zh) 2018-02-01
US20180025966A1 (en) 2018-01-25
US9984960B2 (en) 2018-05-29

Similar Documents

Publication Publication Date Title
CN107644860A (zh) 集成扇出型封装
TWI536519B (zh) 半導體封裝結構以及其製造方法
TWI576927B (zh) 半導體裝置及其製造方法
TWI460845B (zh) 具有區域陣列單元連接器之可堆疊模製微電子封裝
US8796561B1 (en) Fan out build up substrate stackable package and method
TWI390692B (zh) 封裝基板與其製法暨基材
US7670962B2 (en) Substrate having stiffener fabrication method
US20120021541A1 (en) Light emitting device and method of fabricating the same
TW201742209A (zh) 積體扇出型封裝體
CN107123605A (zh) 半导体封装件及其返工工艺
CN101257775A (zh) 制造布线基板的方法和制造电子元件装置的方法
US9462704B1 (en) Extended landing pad substrate package structure and method
US8061024B2 (en) Method of fabricating a circuit board and semiconductor package.
US20120104607A1 (en) Stacked semiconductor packages and related methods
US20220208714A1 (en) Integrated circuit package structure, integrated circuit package unit and associated packaging method
CN110858576B (zh) 覆晶封装基板及其制法
US11670600B2 (en) Panel level metal wall grids array for integrated circuit packaging
US20050258536A1 (en) Chip heat sink device and method
US11824001B2 (en) Integrated circuit package structure and integrated circuit package unit
US11616017B2 (en) Integrated circuit package structure, integrated circuit package unit and associated packaging method
TWI493682B (zh) 內嵌封裝體之封裝模組及其製造方法
JP2008198916A (ja) 半導体装置及びその製造方法
TWI550732B (zh) 晶片封裝結構的製作方法
US20160351522A1 (en) Package-on-package device and cavity formation by solder removal for package interconnection
TWI635587B (zh) 封裝結構及其製作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180130

WD01 Invention patent application deemed withdrawn after publication