TWI460845B - 具有區域陣列單元連接器之可堆疊模製微電子封裝 - Google Patents

具有區域陣列單元連接器之可堆疊模製微電子封裝 Download PDF

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TWI460845B
TWI460845B TW100125522A TW100125522A TWI460845B TW I460845 B TWI460845 B TW I460845B TW 100125522 A TW100125522 A TW 100125522A TW 100125522 A TW100125522 A TW 100125522A TW I460845 B TWI460845 B TW I460845B
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Taiwan
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package
substrate
microelectronic
contacts
component
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TW100125522A
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TW201209991A (en
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Belgacem Haba
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Tessera Inc
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Description

具有區域陣列單元連接器之可堆疊模製微電子封裝
本申請案之標的物係關於微電子封裝，特定言之係關於可堆疊模製微電子封裝，諸如，可在一微電子元件上方及下方之表面處具有封裝接點。
本申請案主張2010年7月19日申請之美國專利申請案第12/839,038號的申請日期之權利，該案之揭示內容特此以引用的方式併入本文中。
諸如半導體晶片之微電子元件通常提供於封裝中，該等封裝提供對於半導體晶片或其他微電子元件之實體及化學保護。此封裝通常包括封裝基板或晶片載體，該封裝基板或晶片載體可包括上面具有導電端子之介電材料面板。晶片黏著於封裝基板上且電連接至封裝基板之該等端子。通常，晶片及基板之多個部分係由囊封物或包覆成型件(overmolding)覆蓋，以使得僅基板之端子承載外表面保持曝露。此封裝可容易地加以裝運、儲存及處置。可使用標準黏著技術(最通常地，表面黏著技術)將封裝黏著至諸如電路板之電路面板。此項技術中已投入了相當大的努力以使此等封裝較小，以使得經封裝之晶片在電路板上佔據較小面積。舉例而言，被稱作晶片尺度封裝之封裝佔據等於晶片自身之面積或僅稍微大於晶片自身之面積的電路板面積。然而，甚至在晶片尺度封裝之情況下，由若干經封裝之晶片所佔據的總計面積亦大於或等於個別晶片之總計面積。
某些多晶片封裝可被稱作「晶粒堆疊封裝」，其中複數個晶片在具有外部界面之共同封裝內黏著於彼此上方。可將此共同封裝黏著於電路面板之一面積上，該面積可等於或僅僅稍大於用以黏著含有單一晶片之單一封裝通常所需的面積。晶粒堆疊封裝方法節省電路面板上之空間。可將在功能上彼此有關之晶片或其他元件提供於共同堆疊封裝中。該封裝可併有此等元件之間的互連。因此，封裝黏著至之電路面板不需要包括此等互連所需的導體及其他元件。此情形又允許使用較簡單之電路面板，且在一些狀況下，允許使用具有較少金屬連接層之電路面板，藉此大大地降低電路面板的成本。此外，常常可使晶粒堆疊封裝內之該等互連具有比黏著於電路面板上之個別封裝之間的相當互連低的電阻抗及短的信號傳播延遲時間。此情形又可如(例如)藉由允許在堆疊封裝內的微電子元件之間的信號傳輸中使用較高之時脈速度而增加此等元件的操作速度。
迄今已提議的一形式之晶片封裝有時被稱作「球堆疊」。球堆疊封裝包括兩個或兩個以上個別單元。每一單元併有類似於個別封裝之封裝基板的單元基板，及黏著至該單元基板且連接至該單元基板上之端子的一或多個微電子元件。該等個別單元堆疊於彼此上方，其中每一個別單元基板上之端子藉由諸如焊球或插腳之導電元件而連接至另一單元基板上的端子。底部單元基板之端子可構成封裝之端子，或者，額外基板可黏著於封裝之底部且可具有連接至該等各種單元基板之端子的端子。球堆疊封裝描繪於(例如)美國公開專利申請案2003/0107118及2004/0031972之某些較佳實施例中，該等專利申請案之揭示內容特此以引用的方式併入本文中。
在有時被稱作摺疊堆疊封裝的另一類型之堆疊封裝中，兩個或兩個以上晶片或其他微電子元件黏著至單一基板。此單一基板通常具有沿著基板延伸之電導體以使黏著於基板上之微電子元件彼此連接。同一基板亦具有連接至黏著於基板上之該等微電子元件中之一者或兩者的導電端子。基板摺疊於自身之上，以使得一部分上之微電子元件處於另一部分上之微電子元件之上，且使得封裝基板的端子曝露於摺疊封裝之底部以用於將封裝黏著至電路面板。在摺疊封裝之某些變體中，在基板已摺疊至其最終組態之後，將該等微電子元件中之一或多者附接至基板。摺疊堆疊之實例展示於以下各案之某些較佳實施例中：美國專利6,121,676；美國專利申請案第10/077,388號；美國專利申請案第10/655,952號；美國臨時專利申請案第60/403,939號；美國臨時專利申請案第60/408,664號；及美國臨時專利申請案第60/408,644號。摺疊堆疊已用於多種目的，但特別可適用於封裝必須彼此通信之晶片中，如(例如)在蜂巢式電話中形成併有基頻信號處理晶片及射頻功率放大器(「RFPA」)晶片的總成中，以便形成緊密的自含式總成。
儘管此項技術中存在所有此等努力，但仍將需要進一步改良。
一種根據本發明之一實施例的微電子封裝可包括一基板，該基板具有一第一表面、一遠離該第一表面之第二表面、複數個基板接點，及與該等基板接點電互連且曝露於該第二表面處之複數個端子。該封裝包括一微電子元件，該微電子元件具有一第一面、一遠離該第一面之第二面及曝露於該第一面處之元件接點，其中該第一面或該第二面中之一者與該基板的該第一表面並置。複數個導電元件突出超過該第一表面且與該等元件接點及該等基板接點電連接。該等導電元件中之至少一些導電元件彼此電絕緣且經調適以同時攜載不同電位。一囊封物上覆該基板之該第一表面、該等導電元件，及該微電子元件之遠離該基板之一面的至少一部分。該囊封物可界定一主表面。複數個封裝接點可上覆該微電子元件之遠離該基板之該面且突出超過該等元件接點距該基板的一高度。該等封裝接點可(諸如)經由該等導電元件而與該基板之該等端子電互連。該等封裝接點可包括導電結合材料塊或實質上硬質導電支柱中之至少一者。該等封裝接點之頂表面可至少部分地曝露於該囊封物之該主表面處。
在一實施例中，該囊封物之該主表面可至少朝向該基板之周邊邊緣延伸超越該微電子元件的周邊邊緣。在一特定實施例中，該等封裝接點可本質上由導電結合材料組成。視情況，該等封裝接點包括實質上硬質支柱。
在一特定實施例中，至少一些導電支柱之頂表面之至少部分曝露於自該囊封物的該主表面向下延伸的開口內。該囊封物可接觸該等至少一些支柱之邊緣表面的至少部分。該等至少一些支柱之邊緣表面可至少部分地曝露於該囊封物中之該等各別開口內。
在一實例中，該囊封物可接觸該等至少一些支柱之該等頂表面之至少部分，以使得該等至少一些支柱的該等頂表面僅部分地曝露於該等開口內。在一特定實例中，該等至少一些支柱之邊緣表面可完全地由該囊封物覆蓋。
在一實例中，該等導電支柱之頂表面可與該囊封物之該主表面共平面。在此實例中，在一狀況下，該等至少一些支柱之邊緣表面可部分地或完全地由該囊封物覆蓋。
在一實施例中，該基板可為一第一基板，且該封裝可進一步包括一第二基板，該第二基板上覆該微電子元件之遠離該第一基板的該面。該第二基板可使該等封裝接點中之至少一些封裝接點與該微電子元件分離。該第一基板與該第二基板可經由該等導電元件而電連接。該等導電元件可為第一導電元件，且該微電子封裝可進一步包括至少一第二導電元件，該至少一第二導電元件連接至一參考電位以便與至少一第一導電元件形成一受控阻抗傳輸線。
在一實例中，無論該封裝包括一個抑或兩個基板，至少一些導電元件可與該微電子元件直接連接。
在一特定實例中，該微電子元件之該等元件接點可面向該第一基板。在另一實例中，該微電子元件之該等元件接點可面向遠離該第一基板之方向且與該第一基板電互連。
在上文或下文中之實例中之任一者中，該微電子元件可為一第一微電子元件，且該封裝可進一步包括安置於該第一微電子元件與該第二基板之間的一第二微電子元件，該第二微電子元件與該第一基板及該第二基板中之至少一者電互連。
在一實例中，為導電結構、熱傳導結構或一隔片中之至少一者的一第二實質上硬質結構可自至少該第一表面突出至至少該第二基板。在一實例中，該第二基板可包括一介電元件。
該等封裝接點可包括遠離該第二基板之一表面突出的複數個實質上硬質導電支柱。
在一實例中，該第二基板可包括一第二介電元件且該等封裝接點可遠離該第二介電元件之一表面突出。該第二基板可包括複數個開口，且該等導電元件中之至少一些導電元件可延伸穿過該第二基板中的該等開口。
在一實施例中，第二實質上硬質導電支柱可遠離該第一基板延伸，且該等第二導電支柱可與該第一基板電連接。該等第二導電支柱可曝露於該囊封物之各別開口內的該囊封物之該主表面處。
根據本發明之一實施例，提供一種製成一微電子封裝之方法。在此方法中，可提供一微電子總成，該微電子總成包括一基板，該基板具有基板接點、一第一表面、一遠離該第一表面之第二表面及曝露於該第二表面處的複數個端子。該總成可包括一微電子元件，該微電子元件具有一正面、曝露於該正面處之元件接點及一遠離該正面之背面，該正面或該背面與該第一表面並置。該微電子總成可進一步包括複數個導電元件，該複數個導電元件突出超過該第一表面且與該等元件接點及該等基板接點電連接。複數個封裝接點可上覆該微電子元件之遠離與該基板第一表面並置之該面的該面。該等封裝接點可與該等導電元件電互連。在特定實例中，該等封裝接點可包括延伸於該微電子元件之該等元件接點之一高度上方的導電結合材料塊或實質上硬質導電支柱中之至少一者。
可接著形成一囊封物以上覆該基板之該第一表面、該等導電元件，及該微電子元件之遠離該基板之一面的至少一部分。該囊封物可界定一主表面且該等封裝接點之頂表面的至少部分可曝露於該囊封物之該主表面處。
在一實施例中，該等頂表面之至少部分可與該囊封物之該主表面齊平。
根據本發明之一實施例，該等封裝接點可能最初並不曝露於該囊封物之該主表面處。在此狀況下，該囊封物主表面可上覆第二導電元件，且可在該囊封物主表面中形成開口以至少部分地曝露該等第二導電元件。在一特定實施例中，該等第二導電元件可用作該微電子封裝之封裝接點。在另一實例中，在於該囊封物層中形成開口之後，可形成與該等第二導電元件電連通之封裝接點。
在一實例中，形成該等封裝接點之該步驟可包括將導電結合材料塊沈積至該等開口內之該等第二導電元件上。在一特定實例中，形成該等封裝接點之該步驟可包括將導電支柱電鍍至曝露於該等開口內之該等第二導電元件上。在一特定實施例中，該等導電元件可包括該微電子元件之元件接點。
在一實例中，該等封裝接點可包括實質上硬質導電支柱或導電塊中之至少一者，且該等封裝接點可延伸於該等元件接點距該基板之該第一表面的一高度上方。
該等導電支柱可具有遠離該基板之該第一表面的頂表面，及遠離該等頂表面延伸之邊緣表面。形成該等開口之該步驟可至少部分地曝露該等邊緣表面。
在一實施例中，可使用本文中之一製造方法來製成第一微電子封裝及第二微電子封裝中之每一者，且接著可將該第二微電子封裝堆疊於該第一微電子封裝之頂上。可經由該第一微電子封裝之封裝接點及該第二微電子封裝之端子電連接該第一微電子封裝與該第二微電子封裝。或者，可經由該第一微電子封裝及該第二微電子封裝之封裝接點或經由該第一微電子封裝及該第二微電子封裝之端子電互連該第一微電子封裝與該第二微電子封裝。
現將根據本發明之實施例描述製造微電子封裝之方法。參看圖1，在一實施例中，可使用介電元件104上之分層金屬結構102製造封裝基板或互連基板，該分層金屬結構具有第一金屬層110、第二金屬層112，及該第一金屬層與該第二金屬層之間的導電蝕刻障壁層114。
如本發明中所使用，諸如「上部」、「下部」、「向上」及「向下」之術語及指示方向之類似術語指代組件自身的參考框架，而非指代重力參考框架。在零件於重力參考框架中定向於諸圖中所展示之方向上的情況下，在重力參考框架中，圖式之頂部向上且圖式之底部向下，在重力參考框架中，上部基板實際上處於下部基板上方。然而，當零件翻轉時，在重力參考框架中，圖式之頂部面向下，在重力參考框架中，上部基板處於下部基板下方。
平行於基板之主表面105的方向在本文中被稱作「水平」或「橫向」方向；而垂直於該主表面之方向在本文中被稱作向上或向下方向且在本文中亦被稱作「垂直」方向。一特徵部安置於比另一特徵部大的「高於表面」之高度處的陳述意謂：兩個特徵部在相同正交方向上自彼表面移位，但一特徵部在相同正交方向上處於比另一特徵部大的遠離彼表面之距離處。相反地，一特徵部安置於比另一特徵部小的「高於表面」之高度處的陳述意謂：兩個特徵部在相同正交方向上自彼表面移位，且一特徵部在相同正交方向上處於比另一特徵部小的距該表面之距離處。
在一實例中，第一金屬層及第二金屬層包括銅或本質上由銅組成，且蝕刻障壁層包括抵抗蝕刻劑以使得該蝕刻劑不能夠圖案化第一金屬層及第二金屬層的金屬。舉例而言，當第一金屬層及第二金屬層係由銅製成時，蝕刻障壁層可由鎳、鉻，或鎳與鉻之合金組成。在一實例中，第一金屬層具有比第二金屬層大得多的厚度。在一實例中，第一金屬層可具有在50微米與300微米之間的厚度，且第二金屬層可具有幾微米之厚度至小於50微米之厚度，且在任何狀況下小於第一金屬層厚度。第二金屬層之厚度通常在約6微米與約30微米之間的範圍內。
如圖1中所見，在此階段，可藉由介電元件104來支撐分層金屬結構，在一特定實例中，介電元件104可包括複數個開口106，經由該複數個開口106曝露第二金屬層112之多個部分。如本發明中所使用，導電結構「曝露於」介電結構之一表面處的陳述指示：該導電結構可用於與一理論點接觸，該理論點在垂直於該介電結構之該表面的方向上自該介電結構之外部朝向該介電結構之該表面移動。因此，曝露於介電結構之一表面處的端子或其他導電結構可自此表面突出；可與此表面齊平；或可相對於此表面凹入且經由介電質中之孔或凹陷而曝露。
介電元件104可包括單一介電材料層，或可為包括若干子層之層壓層。介電元件可主要由聚合介電質(諸如，聚醯亞胺、BT樹脂、環氧樹脂或其他介電聚合物)形成，且在一些實例中，可包括如(例如)玻璃纖維之加強纖維。介電元件104可為可撓性的或硬質的。在一特定實例中，介電元件可為諸如聚醯亞胺材料之聚合物帶材料，諸如通常在捲帶式自動結合(「TAB」)中所使用。
如圖2中所見，在第一金屬層之上形成遮蔽層或其他圖案化犧牲層116。舉幾個例子，該遮蔽層可(諸如)藉由光微影或其他圖案化技術(諸如，模板印刷、絲網印刷，或雷射切除)由抗蝕刻金屬或其他材料形成。接著，如圖3中所見，可(諸如)藉由在朝向分層金屬結構102之方向118上指引蝕刻劑流而圖案化第一金屬層。此圖案化製程移除未受遮蔽層116保護的第一金屬層部分，以便形成複數個經蝕刻之固體金屬支柱120。當蝕刻障壁層114未受到用以圖案化第一金屬層之蝕刻劑侵蝕時，該等支柱突出超過蝕刻障壁層114之曝露表面122。可使該等金屬支柱在蝕刻障壁層上彼此間隔開以便提供一系列個別導體。如圖4中所見，當藉由蝕刻形成該等支柱時，該等支柱可為平截頭圓錐形形狀，每一支柱具有比同一支柱之尖端127寬的底座128，該等支柱通常具有以相對於垂直方向之一角度延伸的邊緣表面。
圖4說明一後續處理階段，在該處理階段中，移除蝕刻障壁金屬層之曝露部分，且圖案化第二金屬層112以形成焊墊124且通常亦形成在介電元件104之平面之方向上延伸的跡線(未圖示)，該等焊墊及該等跡線與支柱120電連接。第二金屬層之該等跡線可電連接該等焊墊中之至少一些焊墊與該等固體金屬支柱中的至少一些固體金屬支柱。由於該圖案化，介電元件104中之開口現變成延伸穿過結構126之厚度的直通開口106。
在上文(圖1至圖4)之變化中，可藉由電鍍至介電層104之一或多個表面上或藉由電鍍步驟與蝕刻步驟之組合而形成包括支柱、焊墊及跡線的類似結構126。在一電鍍結構中，支柱120通常具有邊緣表面，該等邊緣表面相對於該等支柱突出的介電元件之表面105為垂直的。
已界定結構126，圖5說明包括介電元件132之基板130，介電元件132上具有複數個連接元件134及端子140，其中金屬或其他導電元件142電連接接點134與端子140。基板130通常呈具有大量區131的連續或半連續帶或薄片之形式。如下文所解釋，在製程之末尾，每一區131將構成個別封裝之一部分，且每一區131包括(如下文所論述)將形成單一封裝之一部分的特徵部。類似於基板104，基板130可為可撓性的或硬質的且可由與基板104相同之材料中的一或多者建構而成，且基板130之介電元件132可包括單一介電材料層或可為包括若干子層之層壓層，基板130之介電元件132主要由聚合介電質(諸如，聚醯亞胺、BT樹脂、環氧樹脂或其他介電聚合物)形成，且在一些實例中，可包括如(例如)玻璃纖維之加強纖維。類似於基板104之情形，介電元件可為諸如聚醯亞胺材料之聚合物帶材料，諸如通常在捲帶式自動結合(「TAB」)中所使用。
如圖5中特定展示，端子140形成於與連接元件134分離之層中，此等金屬層藉由介電元件132而彼此分離且藉由延伸穿過介電元件之導電元件(諸如，介層孔32)而電連接至彼此。此配置通常被稱作「兩金屬」結構。或者，如圖6中所描繪，基板150可形成為單金屬結構，其中單金屬層構成以下兩者：如曝露於基板之第一表面152處的導電連接元件154，與如曝露於基板之遠離該第一表面之第二表面158處的開口156內的端子160。或者，在圖6中所展示之實施例之變化中，基板150可用於顛倒配置中，在該配置中，該等端子上覆基板之第二表面158，且該等連接元件曝露於自第一表面152開放且延伸穿過介電元件之開口內。在再其他替代例中，構成導電黏著元件、端子或導電黏著元件與端子兩者之一或多個金屬層可安置於介電層之厚度內且經由孔而曝露至適當表面。
如圖7中所見，微電子元件170黏著於第一基板130之第一表面或「上部」表面136上。每一區131上黏著有該等微電子元件中之一或多者。在特定實施例說明中，下部基板之每一區131承載一微電子元件。所展示的微電子元件為以面向下定向所黏著之半導體晶片，其中晶片之接點(例如，結合焊墊(未圖示))連接至基板之導電連接元件134，如(例如)藉由使用諸如焊料之結合材料171將接點結合至導電黏著元件。然而，可使用其他技術。舉例而言，每一微電子元件170可為經封裝之微電子元件，其併有上面具有封裝端子之封裝基板(未圖示)，此等封裝端子連接至第一基板上之導電連接元件134。在再其他變體中，可使用諸如各向異性導電黏接劑之技術。基板130之每一區131內的微電子元件170經由彼區131之導電連接元件134而電連接至同一區之黏著端子140中的至少一些黏著端子140，且電連接至彼區之至少一些層間連接端子138，或電連接至至少一些黏著端子140與至少一些層間連接端子138兩者。作為本文中所描述之組裝製程之部分或在用以製備下部基板130之單獨操作中，可使用習知技術將微電子元件170黏著於下部基板上。
在將微電子元件170黏著至基板130之後，可在基板130與微電子元件之接觸承載面172之間注入底膠174(圖8)，(諸如)以經由結合材料171及連接元件134而促進對微電子元件與基板之間的電連接中之熱應力及機械應力的增加之抵抗性。接著，可(例如)經由黏接劑178將基板100黏著至微電子元件170之背表面176。在一實施例中，例如，當基板100包括聚合介電材料時，黏接劑可為韌性的。然而，在基板100具有處於或接近於微電子元件170之熱膨脹係數的熱膨脹係數的另一實施例中，黏接劑不需要為韌性的，且甚至可為硬質材料。將基板100黏著至微電子元件170，以使得其上的導電支柱120遠離基板之遠離微電子元件170的表面108突出。
如圖8中進一步所見，當將基板與微電子元件接合以形成總成180時，第二基板中之開口106與第一基板之層間連接元件138對準。此情形接著准許形成接合第一基板上之層間連接元件138與第二基板之焊墊124的導電元件182(圖9)，由此形成總成184。舉例而言，可穿過第二基板中之開口106插入導線結合工具的尖端以形成導線結合，該等導線結合具有附接至第二焊墊138之第一端及附接至焊墊124的第二端。接著，可沿著線186割斷總成184以將總成分成個別微電子總成188(圖10)，每一微電子總成188含有第一基板及第二基板中之每一者的一區，及該兩個基板區之間的電連接至每一基板區之微電子元件170。
在上述處理之變化中(圖9A)，可將複數個個別基板126'附接至各別微電子元件170且經由導線結合182'將其電連接至基板130，每一個別基板126'具有自其突出之支柱120及導電元件(例如，其上之焊墊124)。可執行此處理，同時基板130之該等區中之複數個區保持附接在一起(呈連續或半連續基板之形式)。在此狀況下，可將導線結合182'安置於超越每一基板126'之周邊邊緣107處。
如圖11中所展示，可使用模190來形成包含總成188之結構的模製囊封物區。舉例而言，在如圖9A中所見之結構中，在割斷基板130之前，可將模板192定位為抵靠第一基板區131之表面136。接著，經由入口(未圖示)將囊封物引入至模中以環繞導線結合182且通常填充個別支柱120之間及微電子元件170之邊緣198與導線結合182之間的所有空間。接著可將總成自模移除且視情況可處理總成以使囊封物201至少部分地固化，如圖12中所表示。彼時亦將割斷基板130以便形成個別單元188。導電支柱120曝露於囊封物之上覆微電子元件170的曝露之主表面200處。導電支柱在上覆微電子元件170的囊封物之開口202內延伸。通常在將具有囊封物區之微電子總成188自模190移除之後，可將焊料凸塊204或焊球與端子140接合以形成如圖12中所見之微電子封裝210。
圖13說明根據一特定實施例之微電子封裝290，其中端子240(其可為焊墊，或附接有結合材料球242(例如，焊球)之焊墊)中之每一者可與曝露於囊封物的遠離端子240之表面200處的各別導電支柱220垂直地對準。封裝290中的端子及支柱之此配置促進在堆疊總成中的複數個微電子封裝290彼此之堆疊及接合，如下文之圖21中。
在微電子封裝290(在圖13至圖14中進一步說明)中，支柱220形成上覆上部基板100之表面221的區域陣列222。曝露於第二基板100之表面221處的焊墊224可(諸如)藉由導線結合282而與曝露於下部基板之表面處的焊墊238電連接。如圖14中進一步展示，封裝290中之導線結合可經配置以便提供具有所要阻抗或受控阻抗之傳輸線。特定言之，下部基板上之焊墊中之一些焊墊可用於與參考電位連接，該參考電位諸如接地、電源供應電壓，或相對於其他支柱220處所存在的信號之典型改變速率可僅緩慢地改變或可非常緩慢地改變或僅在窄範圍內改變的另一電位。舉例而言，焊墊238A可為用於經由提供於基板230之表面244處的電連接240、242與接地電連接的接地焊墊。參考導線結合284A在鄰近於信號導線結合282之走向(runs)的走向上在基板之此等接地焊墊224A、238A之間延伸。在此狀況下，參考導線結合之走向處於在沿著基板100之表面221的橫向方向292中之一或多者上距信號導線結合之走向實質上均勻的間距處。或者，或除此之外，封裝290可包括參考導線結合284B，參考導線結合284B延伸至參考焊墊238B以用於與參考電位連接，且此等參考導線結合284B之走向可在相對於基板100之第一表面221的垂直方向294(圖13)上實質上對準地在信號導線結合282B之走向的上方或下方延伸。可視情況在同一微電子封裝290中提供任何或所有此等特定實施。
在上文所描述之方法(圖1至圖12)之變化中，不需要導電支柱在將總成自模移除時已曝露。實情為，如圖15中所見，囊封物可上覆頂表面121，亦即，支柱之遠離基板100之端。在此狀況下，頂表面121係由囊封物覆蓋以使得頂表面121內埋於囊封物之主表面300下方。接著，如圖16A中所展示，複數個開口301可形成於囊封物中，該複數個開口301部分地曝露支柱之頂表面121，從而留下頂表面之其他部分303仍由囊封物覆蓋。在此狀況下，支柱之邊緣表面123可保持由囊封物覆蓋。
在圖16A中的實施例之變化中，囊封物主表面中之開口302(圖16B)至少部分地曝露至少一些支柱之頂表面121且至少部分地曝露相同支柱的邊緣表面123。支柱之邊緣表面123可僅部分地曝露於一開口內(如圖16B中所展示)或可曝露至基板之表面105。在鄰近之支柱120之間的囊封物201之部分304可保持為在該等支柱之間絕緣且用於含有結合材料(例如，錫、焊料、導電膏等)之流動，該結合材料可接合至支柱120，諸如，在經接合微電子封裝之堆疊總成中，如下文參看圖21進一步描述。
在一實施例中，一支柱120的頂表面之至少一部分及邊緣表面之至少一部分可曝露於主表面中的一個此開口內，且無任何其他支柱120之表面可曝露於同一開口內。或者，複數個兩個或兩個以上支柱120中之每一者的頂表面之至少部分及邊緣表面之至少部分可曝露於形成於囊封物主表面中的個別開口內。在另一狀況下，複數個兩個或兩個以上支柱的頂表面之至少部分及邊緣表面之至少部分可曝露於形成於囊封物主表面中的個別開口內。
在特定實施例中，一支柱列或者一或多個完整支柱列中之兩個或兩個以上支柱可使頂表面之至少部分及邊緣表面的至少部分曝露於囊封物主表面中之個別開口內。在一些狀況下，僅頂表面之可能小於完整頂表面的部分曝露於特定開口內。在一些狀況下，完整頂表面可曝露於特定開口內。在特定狀況下，僅邊緣表面之部分可曝露於特定開口內，且在一些狀況下，邊緣表面可曝露至基板之表面105或曝露至由支柱所接觸的導電元件表面。在一特定實施例中，完整頂表面及邊緣表面之部分(亦即，小於複數個支柱中之每一者之完整邊緣表面的部分)可曝露於囊封物主表面中的個別開口內。
圖17說明上述實施例(圖12；或圖13至圖14)之變化，其中囊封物201形成於曝露於基板400之面向外之表面421處的導電焊墊402之頂上。以彼方式，焊墊402內埋於囊封物之曝露表面404下方，在一實例中，曝露表面404可為囊封物之主表面。類似於上文所描述之實施例(圖12至圖13)之導電支柱220，焊墊402可經由跡線(未圖示)或其他導體(未圖示)而與第一基板400之結合焊墊124電連接，以用於同時攜載處於不同電位的信號及其他電壓。在使囊封物至少部分地固化之後，在囊封物中形成開口406(圖18)，開口406自曝露表面404延伸且至少部分地曝露各別焊墊402。隨後，可在每一開口內提供導電結合材料(例如，錫、焊料或導電膏等)以形成曝露於表面404處之導電塊408(圖19)。在封裝之一變化(圖19)中，可將金屬(諸如，銅、金或銅與金之組合)電鍍至該等開口內之焊墊上以形成固體金屬支柱(替代曝露於表面404處的塊408)。可在形成支柱之後使總成平坦化，以使得以此方式所電鍍的支柱之表面為平坦的且可與表面404齊平。
在另一替代例(圖20)中，在將囊封物塗覆至導電焊墊402之前，將導電塊410(例如，焊球)與導電焊墊402接合。在模製期間，模之頂板192(圖11)接觸導電塊之表面且可藉由模壓縮導電塊410以便使與頂板接觸的導電塊表面平坦。結果，當將封裝490自模移除時，導電塊具有曝露於主表面404處的相對寬之平坦表面412。
在圖20之變化中，如圖20A中所見，可形成具有在高度H1 處之主表面405的囊封物，高度H1 大於導電塊410(例如，焊球)在上部基板400上方延伸至的高度H2。在形成囊封物層之後，可使用雷射切除、機械研磨或其他方式來形成曝露導電塊中之各別者的開口411。
在上述實施例(圖15至圖20A)之變化中，兩個或兩個以上導電支柱或導電塊可曝露於囊封物層中之個別開口中。在圖20A中所展示的實施例之變化中，導電塊410可接觸每一導電支柱之頂表面427及邊緣表面428，導電塊部分地曝露於開口411內。
圖21說明形成包括複數個微電子封裝290A、290B、290C(每一微電子封裝係如上文所描述)之堆疊總成500的程序。可將第一微電子封裝之焊球242A與電路面板502(例如，可撓性或硬質電路板或卡、主機板等)之端子504接合。以此方式，在一方面的電路面板502與封裝290A之微電子元件170A及層間導電元件138A之間提供用於攜載信號及其他電壓的電連接。導電支柱120A亦經由經具有與端子240A及焊球242A之電連接(未圖示)的焊墊124、導線結合282及層間導電元件138A的電連接而將信號及其他電壓攜載至電路面板之焊墊504及自焊墊504攜載信號及其他電壓。
在將微電子封裝290A與電路面板502接合之後，可將微電子封裝290B之焊球242B與微電子封裝290A之導電支柱120A接合。圖21進一步說明定位微電子封裝290C以使得其上之焊球242C與微電子封裝290B之導電支柱120B對準，此後將微電子封裝290C與微電子封裝290B接合。在一變化中，可藉由將總成中的一封裝上之焊球與總成中的另一封裝之各別導電支柱接合而形成微電子封裝290A、290B、290C之總成，此後可將曝露於此總成之底部的焊球242A接合至電路面板之對應焊墊504。
下文如下參看圖式展示及描述額外變化，該等圖式經簡化以使得並非特別展示或參考所存在的所有元件。又，並非在如下文所描述的變化中之每一者中有必要存在或需要每一圖式中所展示的所有元件。關於本文中所描述之實施例，「上部基板」或「下部基板」不需要符合重力參考框架。在圖22至圖32中，被稱作「上部基板」或「下部基板」的元件中之每一者可為個別基板或可為較大(例如，連續或半連續)基板之一割斷部分。另外，可使每一微電子封裝或總成中的上部基板與下部基板之相對位置反轉，以使得下部基板替代每一各別圖中所說明之上部基板，且上部基板替代每一圖中的下部基板。
因此，在一實施例中，如圖22中所見，參考導線結合584可具有在鄰近於且至少實質上平行於信號導線結合582之走向的垂直方向上延伸的走向，參考導線結合電連接至曝露於囊封物之主表面504處的參考導電支柱520。參考導電支柱可用於連接至參考電位(諸如，接地或電源供應電壓)，(諸如)以用於與參考導線結合584一起用於控制信號導線結合之阻抗。如圖22中進一步所見，在一特定實施例中，第一基板550可具有複數個金屬層552，該複數個金屬層552中之至少一金屬層可內埋於第一基板550之介電元件的厚度內。
圖23說明實施例(圖22)之變化，其中額外導電支柱522與突出超過下部基板550之第一表面554的導電元件538(例如，跡線、焊墊等)電連接。導電支柱522可與一或多個參考支柱520或參考導體電連接，(諸如)用於提供一或多個參考電位(例如，電源供應電壓或接地)。在一實例中，支柱520具有底座521，底座521與支柱522之對應鄰近表面523以冶金方式接合或成一體式。在一特定實施例中，諸如隔片之結構可替代支柱522以用於維持上部基板與下部基板之間的所要間距。或者，熱散播器或其他熱導體可替代導電支柱522或導電支柱522亦可充當隔片或具有熱傳導功能。
圖24說明實施例(圖22)之另一變化，其中上部基板或第二基板600為引線框架，在該引線框架中，(諸如)藉由在製成引線框架時壓印或模壓金屬箔(且在一些狀況下，在其上電鍍金屬)而整體形成支柱620及自支柱延伸之跡線622。接著可將此引線框架600結合至微電子元件670之背表面672，且接著可將所得總成置放於模內且接著如上文關於圖11所描述形成囊封物。或者，並非壓印或模壓金屬箔，而是除了以下情況以外，可自分層金屬結構(諸如，上文關於圖1至圖4所描述)圖案化上部基板：圖案化之分層金屬結構可經由黏接劑而至晶片670之面，亦即，不需要額外介電元件(諸如，支撐微電子封裝中之支柱及支柱上之接點的介電基板)。
如圖22中，一或多個參考支柱620A及一或多個參考導線結合可攜載諸如電力或接地之參考電位。圖25說明另一變化，其中可省略圖24之該一或多個參考支柱620A。
圖26說明實施例(圖13至圖14)之變化，其中微電子元件770之接觸承載面771面向上，亦即，遠離下部基板700。微電子元件770之接點772(例如，結合焊墊)可鄰近於微電子元件之周邊邊緣774而被提供，以使得接點曝露於超越上部基板730之鄰近周邊邊緣732處。第一導線結合740可電連接微電子元件之接點772與下部基板上之對應焊墊744。第二導線結合742可電連接接點772與上部基板之對應焊墊(未圖示)。在一實施例中，一或多個導線結合可直接連接上部基板之焊墊與下部基板之焊墊。
在另一變化中，如圖27中所見，第一微電子元件870及第二微電子元件880可各自以面向上方式黏著，亦即，接觸承載面面向遠離下部基板800的方向。該等微電子元件可經由在每一微電子元件上之接點之間延伸的導線結合882而電連接在一起。額外導線結合884、886可電連接微電子元件與上部基板830及下部基板800。在另一變化中，可將第三微電子元件、第四微電子元件或甚至更大數目個微電子元件以類似方式黏著及電連接於微電子封裝內。
圖27A說明圖27中所展示的實施例之變化，其中兩個微電子元件970、980各自以覆晶方式黏著至各別基板800、900。該等微電子元件之背面可以背面方式結合在一起，如所展示。如圖27A中進一步所見，微電子封裝中的導線結合984中之至少一些導線結合984可具有受控阻抗。亦即，在元件之間(例如，在下部基板800與上部基板900之間)攜載信號的導線結合984(如圖27中所見)可位於其他導線結合986之側面且處於距其他導線結合986實質上均勻間距處，導線結合986具有與信號導線結合之垂直走向平行的垂直走向。其他導線結合986電連接至參考電位(例如，接地、電源供應電壓)，或者，經受僅非常緩慢地改變(與由信號導線結合所攜載的信號之改變速率相比較)的電壓。此等參考導線結合986經由提供於上部基板800及下部基板900中之每一者上的接點而電連接至參考電位。
在圖27A中所展示的實施例之變化中，一或多個微電子元件可以覆晶方式黏著至基板800、900中之各別者，且另一微電子元件可以相對於該等基板中之一者(該微電子元件經由一或多個導線結合(未圖示)而電連接至該基板)面向上定向的方式黏著。在圖27中所展示的實施例之特定變化中，微電子元件(未圖示)可以覆晶方式黏著至基板800，且微電子元件870可以背面方式結合至以覆晶方式黏著之微電子元件的背面。彼微電子元件870可與基板800電連接(如圖27中所展示)，且另一微電子元件880可電連接至下部基板800、上部基板830或微電子元件870，如上文關於圖27所展示及描述。
圖28說明實施例(圖26)之另一變化，其類似於圖20之實施例在於：在形成囊封物之前，將焊球940與導電元件(例如，上部基板上之焊墊(未圖示))接合。
圖29說明圖26實施例之變化，其亦類似於圖19之實施例在於：可在形成囊封物之後形成導電塊1008。
圖30說明又一變化，其中微電子元件1170黏著至基板1100，其中接觸承載面1172面向遠離基板1100之方向。在此實施例中，省略上部基板。導電支柱1120(其(例如)可具有在50微米與300微米之間的高度)可如關於上述實施例(圖1至圖14)所描述。該等支柱可遠離微電子元件之面1172而延伸且曝露於囊封物之表面1102處。在一實施例中，導電支柱可如以下各案中所描述而形成：共同擁有的美國申請案第12/317,707號、第12/462,208號、第12/286,102號、第12/832,376號或美國專利第7,911,805號(TIMI 3.0-100、TIMI 3.0-101、TESSERA 3.0-585、TESSERA 3.0-609或TESSERA 3.0-565)，該等案之揭示內容以引用的方式併入本文中。支柱1120可用於將微電子元件1170電連接至另一封裝或元件，以及用於經由以下各者而將焊球(例如，基板1100之球狀柵格陣列(BGA)界面1140)電連接至另一封裝或元件：焊墊1174、導線結合1176，及沿著連接支柱1120與導線結合1176之表面1172延伸的導電元件1178。
圖31說明實施例(圖30)之另一變化，其中提供諸如焊球之導電塊1220替代圖30中所見的導電支柱1120。
圖32說明上述實施例(圖26)之變化，其具有在下部基板與囊封物1300之表面1302之間延伸的一或多個額外導電支柱1320。該等導電支柱可與焊球1340中之一或多者電連接。在一實施例中，額外導電支柱可呈沿著微電子元件1370之周邊邊緣1374延伸(亦即，在進出提供圖32所在之紙面的方向上)的隆脊、環或其部分的形式。在一實施例中，該一或多個額外導電支柱可攜載時間變化之信號。或者，該一或多個額外導電支柱1320可攜載諸如接地或電源供應電壓之參考電位。
圖33說明根據另一實施例之堆疊總成，其中上部封裝之端子1440B與連接器(例如，具有如上文關於圖26所展示及描述之結構的下部微電子封裝1490A之導電支柱1420A)接合。圖33說明：微電子封裝1490A上之連接器1420A之間距、數目及接觸面積可經標準化以便與另一封裝1490B的對應BGA界面配合，且另一封裝不需要具有與封裝1490A相同的結構。
較佳實施例之上述描述意欲說明而非限制本發明。製造微電子封裝之特定方法及其中之結構可如Belgacem Haba之於2010年7月19日申請的題為「可堆疊模製微電子封裝(STACKABLE MOLDED MICROELECTRONIC PACKAGES)」之共同擁有的美國申請案第12/838,974號中進一步描述，該申請案之揭示內容以引用的方式併入本文中。
由於可在不脫離如藉由申請專利範圍所界定之本發明的情況下利用上文所論述之特徵部的此等及其他變化及組合，故較佳實施例之上述描述應作為說明來理解而非作為如藉由申請專利範圍所界定的本發明之限制來理解。
32．．．介層孔
100．．．基板
102．．．分層金屬結構
104．．．介電元件/介電層
105．．．基板之主表面
106．．．開口
107．．．基板之周邊邊緣
108．．．基板之遠離微電子元件的表面
110．．．第一金屬層
112．．．第二金屬層
114．．．導電蝕刻障壁層
116．．．遮蔽層或其他圖案化犧牲層
118．．．方向
120．．．經蝕刻之固體金屬支柱/導電支柱
120A．．．導電支柱
120B．．．導電支柱
121．．．頂表面
122．．．蝕刻障壁層之曝露表面
123．．．支柱之邊緣表面
124．．．焊墊
126．．．結構
126'．．．基板
127．．．支柱之尖端
128．．．底座
130．．．基板
131．．．區
132．．．介電元件
134．．．連接元件/接點
136．．．第一表面或「上部」表面
138．．．層間連接端子/層間連接元件/第二焊墊
138A．．．層間導電元件
140．．．端子
142．．．金屬或其他導電元件
150．．．基板
152．．．第一表面
154．．．導電連接元件
156．．．開口
158．．．第二表面
160．．．端子
170．．．微電子元件
170A．．．微電子元件
171．．．結合材料
172．．．接觸承載面
174．．．底膠
176．．．微電子元件之背表面
178．．．黏接劑
180．．．總成
182．．．導電元件/導線結合
182'．．．導線結合
184．．．總成
186．．．線
188．．．微電子總成/單元
190．．．模
192．．．模板/模之頂板
198．．．微電子元件之邊緣
200．．．囊封物之主表面/囊封物的遠離端子之表面
201．．．囊封物
202．．．開口
204．．．焊料凸塊
210．．．微電子封裝
220．．．導電支柱
221．．．上部基板之表面
222．．．區域陣列
224．．．焊墊
224A．．．接地焊墊
230．．．基板
238．．．焊墊
238A．．．焊墊/接地焊墊
238B．．．參考焊墊
240．．．端子/電連接
240A．．．端子
242．．．結合材料球/電連接
242A．．．焊球
242B．．．焊球
242C．．．焊球
244．．．基板之表面
282．．．導線結合
282B．．．信號導線結合
284A．．．參考導線結合
284B．．．參考導線結合
290．．．微電子封裝
290A．．．微電子封裝
290B．．．微電子封裝
290C．．．微電子封裝
292．．．橫向方向
294．．．垂直方向
300．．．囊封物之主表面
301．．．開口
302．．．開口
303．．．頂表面之其他部分
304．．．在鄰近之支柱之間的囊封物之部分
400．．．基板
402．．．導電焊墊
404．．．囊封物之曝露表面
405．．．主表面
406．．．開口
408．．．導電塊
410．．．導電塊
411．．．開口
412．．．相對寬之平坦表面
421．．．基板之面向外之表面
427．．．導電支柱之頂表面
428．．．導電支柱之邊緣表面
490．．．封裝
500．．．堆疊總成
502．．．電路面板
504．．．端子/焊墊/囊封物之主表面
520．．．參考導電支柱
521．．．底座
522．．．導電支柱
523．．．支柱之對應鄰近表面
538．．．導電元件
550．．．第一基板
552．．．金屬層
554．．．第一表面
582．．．信號導線結合
584．．．參考導線結合
600．．．上部基板或第二基板/引線框架
620．．．支柱
620A．．．參考支柱
622．．．跡線
670．．．微電子元件/晶片
672．．．微電子元件之背表面
700．．．下部基板
730．．．上部基板
732．．．周邊邊緣
740．．．第一導線結合
742．．．第二導線結合
744．．．焊墊
770．．．微電子元件
771．．．接觸承載面
772．．．接點
774．．．周邊邊緣
800．．．下部基板
830．．．上部基板
870．．．第一微電子元件
880．．．第二微電子元件
882．．．導線結合
884．．．導線結合
886．．．導線結合
900．．．基板
940．．．焊球
970．．．微電子元件
980．．．微電子元件
984．．．導線結合
986．．．參考導線結合
1008．．．導電塊
1100．．．基板
1102‧‧‧囊封物之表面
1120‧‧‧導電支柱
1140‧‧‧球狀柵格陣列(BGA)界面
1170‧‧‧微電子元件
1172‧‧‧接觸承載面
1174‧‧‧焊墊
1176‧‧‧導線結合
1178‧‧‧導電元件
1220‧‧‧導電塊
1300‧‧‧囊封物
1302‧‧‧囊封物之表面
1320‧‧‧導電支柱
1340‧‧‧焊球
1370‧‧‧微電子元件
1374‧‧‧微電子元件之周邊邊緣
1420A‧‧‧導電支柱/連接器
1440B‧‧‧上部封裝之端子
1490A‧‧‧下部微電子封裝
1490B‧‧‧封裝
圖1為說明根據本發明之實施例的製造基板之方法中的一階段的截面圖；
圖2為說明根據本發明之實施例的製造基板之方法中的在圖1中所展示之階段之後的一階段的截面圖；
圖3為說明根據本發明之實施例的製造基板之方法中的在圖1中所展示之階段之後的一階段的截面圖；
圖4為說明根據本發明之實施例的製造基板之方法中的在圖1中所展示之階段之後的一階段的截面圖；
圖5為說明根據本發明之實施例之方法中所使用的基板的截面圖；
圖6為說明根據本發明之實施例之變化的方法中所使用之基板的截面圖；
圖7為說明根據本發明之實施例之方法中的在圖5或圖6之階段之後的一製造階段的截面圖；
圖8為說明根據本發明之實施例之方法中的在圖7之階段之後的一製造階段的截面圖；
圖9為說明根據本發明之實施例之方法中的在圖8之階段之後的一製造階段的截面圖；
圖9A為說明根據圖8及圖9中所展示的本發明之實施例之變化的方法中之在圖7之階段之後的一製造階段的截面圖；
圖10為說明根據本發明之實施例之方法中的在圖9或圖9A之階段之後的一製造階段的截面圖；
圖11為說明在圖10之階段之後的一製造階段的截面圖；
圖12為說明根據本發明之實施例之微電子封裝的截面圖；
圖13為穿過圖14之線13-13截取的截面圖，該圖說明根據本發明之實施例之微電子封裝；
圖14為朝向根據圖13中所展示的本發明之實施例的微電子封裝之上部基板檢視的俯視平面圖；
圖15為說明根據本發明之實施例的製造微電子封裝之方法中之一階段的截面圖；
圖16A為說明根據本發明之實施例的製造微電子封裝之方法中的在圖15中所展示之階段之後的一階段的截面圖；
圖16B為說明圖16A中所展示之方法之變化中的在圖15中所展示之階段之後的一階段的截面圖；
圖17為說明根據本發明之實施例的製造微電子封裝之方法中之一階段的截面圖；
圖18為說明根據本發明之實施例的製造微電子封裝之方法中的在圖17中所展示之階段之後的一階段的截面圖；
圖19為說明根據本發明之實施例的製造微電子封裝之方法中的在圖18中所展示之階段之後的一階段的截面圖；
圖20為說明根據本發明之實施例之微電子封裝的截面圖；
圖20A為說明根據圖20中所展示的本發明之實施例之變化的微電子封裝的截面圖；
圖20B為說明根據圖20中所展示的本發明之實施例之另一變化的微電子封裝的截面圖；
圖21為說明根據本發明之實施例的製成堆疊微電子總成之方法中之一階段的截面圖；
圖22為說明根據本發明之實施例之微電子封裝的截面圖；
圖23為說明根據本發明之實施例之微電子封裝的截面圖；
圖24為說明根據本發明之實施例之微電子封裝的截面圖；
圖25為說明根據本發明之實施例之微電子封裝的截面圖；
圖26為說明根據本發明之實施例之微電子封裝的截面圖；
圖27為說明根據本發明之實施例之微電子封裝的截面圖；
圖27A為說明根據本發明之實施例之微電子封裝的截面圖；
圖28為說明根據本發明之實施例之微電子封裝的截面圖；
圖29為說明根據本發明之實施例之微電子封裝的截面圖；
圖30為說明根據本發明之實施例之微電子封裝的截面圖；
圖31為說明根據本發明之實施例之微電子封裝的截面圖；
圖32為說明根據本發明之實施例之微電子封裝的截面圖；及
圖33為說明根據本發明之實施例之微電子總成的截面圖。
100．．．基板
170．．．微電子元件
220．．．導電支柱
221．．．上部基板之表面
222．．．區域陣列
224．．．焊墊
230．．．基板
238．．．焊墊
240．．．端子/電連接
242．．．結合材料球/電連接
244．．．基板之表面
282．．．導線結合
290．．．微電子封裝
294．．．垂直方向

Claims (38)

  1. 一種微電子封裝，其包含：一第一基板，其具有一第一表面、一遠離該第一表面之第二表面、被曝露於該第一表面之複數個第一基板接點，及與該等第一基板接點電互連且曝露於該第二表面處的複數個端子；一第二基板，其遠離該第一表面，該第二基板具有一第一表面、遠離該第一表面之一第二表面以及被曝露於該第二基板之該第二表面之複數個第二基板接點以及被曝露於該第二基板之該第二表面之複數個焊墊；一微電子元件，其被置於該第一基板之該第一表面和該第二基板之該第一表面之間，該微電子元件具有一第一面、一遠離該第一面之第二面，及曝露於該第一面處之元件接點，該第一面或該第二面中之一者與該第一基板的該第一表面並置；複數個導線結合，其突出超過該第一基板的該第一表面且延伸於該第一基板接點和該第二基板接點之間，該等導線結合中之至少一些導線結合彼此電絕緣且經調適以同時攜載不同電位；一連續囊封物，其上覆該第一基板之該第一表面、該等導線結合，及該第二基板之該第二表面的至少一部分，該連續囊封物界定一主表面；及複數個封裝接點，其曝露於該囊封物之主要表面且上覆該第二基板之該第二表面且突出超過該第二基板接點 的一高度，該等封裝接點至少經由該等導線結合、從該囊封物之主要表面向下延伸的開口、包含延伸於該等開口中之銅或金的固體金屬支柱之該等封裝接點、被放置於該等焊墊上之該等支柱而與該微電子元件之該等元件接點電互連，其中該等封裝接點之至少頂表面至少部分地曝露於該連續囊封物之該主表面處，並且該等封裝接點係經建構以同時攜載個別不同的電位。
  2. 如請求項1之封裝，其中該囊封物之該主表面至少朝向該基板之周邊邊緣延伸超越該微電子元件的周邊邊緣。
  3. 如請求項1之封裝，其中該等固體金屬支柱實質上為硬質的。
  4. 如請求項3之封裝，其中該囊封物接觸該等至少一些支柱之邊緣表面的至少部分。
  5. 如請求項4之封裝，其中該等至少一些支柱之該等邊緣表面至少部分地曝露於該囊封物中的該等各別開口內。
  6. 如請求項4之封裝，其中該囊封物接觸該等至少一些支柱之該等頂表面的至少部分，以使得該等至少一些支柱之該等頂表面僅部分地曝露於該等開口內。
  7. 如請求項6之封裝，其中該等至少一些支柱之邊緣表面完全地由該囊封物覆蓋。
  8. 如請求項3之封裝，其中該等導電支柱之頂表面與該囊封物之該主表面共平面。
  9. 如請求項8之封裝，其中該等至少一些支柱之邊緣表面完全地由該囊封物覆蓋。
  10. 如請求項1之封裝，其中該些導線結合包含第一導線結合，且至少一個第二導線結合倍連接至一基板接點用於電連接該至少一個第二導線結合至至一參考電位，使得該至少一個第二導線結合與第一導線結合之至少一個形成一受控阻抗傳輸線。
  11. 如請求項1之封裝，其進一步包含與該微電子元件直接連接之至少一些額外的導線結合。
  12. 如請求項1之封裝，其中該微電子元件之該等元件接點面向該第一基板。
  13. 如請求項1之封裝，其中該微電子元件之該等元件接點面向遠離該第一基板之方向且與該第一基板電互連。
  14. 如請求項12或請求項13之封裝，其中該微電子元件為一第一微電子元件，該封裝進一步包含安置於該第一微電子元件與該第二基板之間的一第二微電子元件，該第二微電子元件與該第一基板及該第二基板中之至少一者電互連。
  15. 如請求項1之封裝，其進一步包含為導電結構、熱傳導結構或一隔片中之至少一者的第二實質上硬質結構，其至少自該第一表面突出至該第二基板。
  16. 如請求項15之封裝，其中該第二基板包括一介電元件。
  17. 如請求項1之封裝，其中該等封裝接點包括遠離該第二基板之一表面突出的複數個實質上硬質導電支柱。
  18. 如請求項17之封裝，其中該第二基板包括一第二介電元件且該等封裝接點遠離該第二介電元件的一表面突出。
  19. 如請求項17或請求項18之封裝，其中該第二基板包括複數個開口，且該等導電元件中之至少一些導電元件延伸穿過該第二基板中的該等開口。
  20. 如請求項17之封裝，其進一步包含遠離該第一基板延伸之第二實質上硬質導電支柱，且第二導電支柱與該第一基板電連接，該等第二導電支柱曝露於該囊封物之各別開口內的該囊封物之該主表面處。
  21. 一種製成一微電子封裝之方法，其包含：提供一微電子總成，該微電子總成包括一基板，該基板具有基板接點、一第一表面、一遠離該第一表面之第二表面及曝露於該第二表面處之複數個端子；一微電子元件，該微電子元件具有一正面、曝露於該正面處之元件接點及一遠離該正面之背面，該正面或該背面與該第一表面並置，該微電子總成進一步包括複數個導電元件，該複數個導電元件突出超過該第一表面且與該等元件接點及該等基板接點電連接；複數個封裝接點，該複數個封裝接點上覆該微電子元件之遠離與該基板第一表面並置之該面的該面，該等封裝接點與該等導電元件電互連，該等封裝接點包括延伸於該微電子元件之該等元件接點之一高度上方的導電結合材料塊或實質上硬質導電支柱中之至少一者；接著形成一囊封物，該囊封物上覆該第一表面、該等導電元件，及該微電子元件之遠離該基板之一面的至少一部分，該囊封物界定一主表面，其中該等封裝接點之 頂表面的至少部分曝露於該囊封物之該主表面處。
  22. 如請求項21之方法，其中該等頂表面之該等至少部分與該囊封物之該主表面齊平。
  23. 如請求項21之用以製成第一微電子封裝及第二微電子封裝中的每一者之方法，其進一步包含將該第二微電子封裝堆疊於該第一微電子封裝之頂上，及經由該第一微電子封裝之封裝接點及該第二微電子封裝之端子電互連該第一微電子封裝與該第二微電子封裝。
  24. 如請求項21之用以製成第一微電子封裝及第二微電子封裝中的每一者之方法，其進一步包含將該第二微電子封裝堆疊於該第一微電子封裝之頂上，及經由該第一微電子封裝之該等封裝接點及該第二微電子封裝之封裝接點電互連該第一微電子封裝與該第二微電子封裝。
  25. 如請求項21之用以製成第一微電子封裝及第二微電子封裝中的每一者之方法，其進一步包含將該第二微電子封裝堆疊於該第一微電子封裝之頂上，及經由該第一微電子封裝之端子及該第二微電子封裝之該等端子電互連該第一微電子封裝與該第二微電子封裝。
  26. 一種製成一微電子封裝之方法，其包含：提供一微電子總成，該微電子總成包括一基板，該基板具有基板接點、一第一表面、一遠離該第一表面之第二表面及曝露於該第二表面處之複數個端子；一微電子元件，該微電子元件具有一正面、曝露於該正面處之元件接點及一遠離該正面之背面，該正面或該背面與該第 一表面並置，該微電子總成進一步包括複數個導電元件，該複數個導電元件突出超過該第一表面且與該等元件接點及該等基板接點電連接；及第二導電元件，該等第二導電元件上覆該微電子元件之遠離與該基板第一表面並置之該面的該面，該等第二導電元件與該等導電元件電互連；接著形成一囊封物，該囊封物上覆該第一表面、該等導電元件，及該微電子元件之遠離該基板之一面的至少一部分，該囊封物界定一主表面；及接著在該囊封物中形成開口以至少部分地曝露該等第二導電元件。
  27. 如請求項26之方法，其中該等第二導電元件用作該微電子封裝之封裝接點。
  28. 如請求項26之方法，其進一步包含形成與該等第二導電元件電連通之封裝接點。
  29. 如請求項28之方法，其中形成該等封裝接點之該步驟包括將導電結合材料塊沈積至該等開口內的該等第二導電元件上。
  30. 如請求項29之方法，其中該等導電元件包括該微電子元件之元件接點。
  31. 如請求項28之方法，其中形成該等封裝接點之該步驟包括將導電支柱電鍍至曝露於該等開口內之該等第二導電元件上。
  32. 如請求項31之方法，其中該等導電元件包括該微電子元 件之元件接點。
  33. 如請求項27之方法，其中該等封裝接點包括實質上硬質導電支柱或導電塊中之至少一者，該等封裝接點延伸於該等元件接點距該基板之該第一表面的一高度上方。
  34. 如請求項33之方法，其中該等導電支柱具有遠離該基板之該第一表面的頂表面，及遠離該等頂表面延伸之邊緣表面，其中形成該等開口之該步驟至少部分地曝露該等邊緣表面。
  35. 如請求項26之用以製成第一微電子封裝及第二微電子封裝中的每一者之方法，其進一步包含將該第二微電子封裝堆疊於該第一微電子封裝之頂上，及經由該第一微電子封裝之封裝接點及該第二微電子封裝之端子電互連該第一微電子封裝與該第二微電子封裝。
  36. 如請求項26之用以製成第一微電子封裝及第二微電子封裝中的每一者之方法，其進一步包含將該第二微電子封裝堆疊於該第一微電子封裝之頂上，及經由該第一微電子封裝之該等封裝接點及該第二微電子封裝之封裝接點電互連該第一微電子封裝與該第二微電子封裝。
  37. 如請求項26之用以製成第一微電子封裝及第二微電子封裝中的每一者之方法，其進一步包含將該第二微電子封裝堆疊於該第一微電子封裝之頂上，及經由該第一微電子封裝之端子及該第二微電子封裝之該等端子電互連該第一微電子封裝與該第二微電子封裝。
  38. 一種微電子封裝，其包含： 一第一基板，其具有一第一表面、一遠離該第一表面之第二表面、被曝露於該第一表面之複數個第一基板接點，及與該等第一基板接點電互連且曝露於該第二表面處的複數個端子；一第二基板，其遠離該第一基板，該第二基板具有一第一表面、遠離該第一表面之一第二表面以及被曝露於該第二基板之該第二表面之複數個第二基板接點；一微電子元件，其被置於該第一基板之該第一表面和該第二基板之該第一表面之間，該微電子元件具有一第一面、一遠離該第一面之第二面，及曝露於該第一面處之元件接點，該第一面或該第二面中之一者與該第一基板的該第一表面並置；複數個導線結合，其突出超過該第一基板的該第一表面且延伸於該第一基板接點和該第二基板接點之間，該等導線結合中之至少一些導線結合彼此電絕緣且經調適以同時攜載不同電位；一連續囊封物，其上覆該第一基板之該第一表面、該等導線結合，及該第二基板之該第二表面的至少一部分，該連續囊封物界定一主表面；及複數個封裝接點，其曝露於該囊封物之主要表面且上覆該第二基板之該第二表面且突出超過該第二基板接點的一高度，該等封裝接點至少經由該等導線結合、在該囊封物中而從該囊封物之主要表面向下延伸的複數個開口，該等開口逐漸變細以成為從該囊封物之主要表面逐 漸變小至暴露於該基板之第二表面的焊墊、包含大量的導電結合材料塊或導電支柱中的至少一者之該等封裝接點、被放置於該等焊墊上之該等支柱而與該微電子元件之該等元件接點電互連，其中該等封裝接點之至少頂表面至少部分地曝露於該連續囊封物之該主表面處，並且垓等封裝接點係經建構以同時帶有個別不同的電位。
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