JP2013535825A - エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ - Google Patents
エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ Download PDFInfo
- Publication number
- JP2013535825A JP2013535825A JP2013520776A JP2013520776A JP2013535825A JP 2013535825 A JP2013535825 A JP 2013535825A JP 2013520776 A JP2013520776 A JP 2013520776A JP 2013520776 A JP2013520776 A JP 2013520776A JP 2013535825 A JP2013535825 A JP 2013535825A
- Authority
- JP
- Japan
- Prior art keywords
- package
- substrate
- microelectronic
- conductive
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 220
- 239000000758 substrate Substances 0.000 claims abstract description 229
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 48
- 229910052751 metal Inorganic materials 0.000 description 47
- 239000002184 metal Substances 0.000 description 47
- 229910000679 solder Inorganic materials 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 17
- 230000007246 mechanism Effects 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 7
- 230000005484 gravity Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 239000012783 reinforcing fiber Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001976 improved effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1052—Wire or wire-like electrical connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Micromachines (AREA)
- Connector Housings Or Holding Contact Members (AREA)
Abstract
【選択図】図13
Description
本出願は、2010年7月19日に出願された米国特許出願第12/839,038号の出願日の利益を主張するものであり、この特許出願は、その開示を引用することにより、本明細書の一部をなすものとする。
Claims (36)
- 超小型電子パッケージであって、
第1の表面と、この第1の表面から離れて位置する第2の表面とを有するとともに、複数の基板コンタクトと、この基板コンタクトと電気的に互いに接続され且つ前記第2の表面において露出する複数の端子とを有する基板と、
第1の面と、この第1の面から離れて位置する第2の面とを有するとともに、前記第1の面において露出する素子コンタクトを有する超小型電子素子であって、前記第1の面及び前記第2の面のうちの一方は、前記基板の前記第1の表面と並んで配置される超小型電子素子と、
前記第1の表面から上方に突出し、前記素子コンタクト及び前記基板コンタクトと電気的に接続される複数の導電性素子であって、この導電性素子のうちの少なくとも複数は互いに電気的に絶縁され、かつ異なる電位を同時に搬送するように構成される複数の導電性素子と、
前記基板の前記第1の表面と、前記導電性素子と、前記基板から離れている前記超小型電子素子の面の少なくとも一部との上に重なる封入材であって、この封入材は主面を画定するものである封入材と、
前記基板から離れている前記超小型電子素子の前記面の上に重なり、前記基板から前記素子コンタクトの高さより高く突出する複数のパッケージコンタクトであって、このパッケージコンタクトは少なくとも前記導電性素子を通して前記基板の前記端子と電気的に互いに接続され、このパッケージコンタクトは導電性結合材料の塊状物又は硬質の導電性ポストのうちの少なくとも一方を含み、このパッケージコンタクトの少なくとも上面は前記封入材の前記主面において少なくとも部分的に露出する複数のパッケージコンタクトと
を備える超小型電子パッケージ。 - 前記封入材の前記主面は、前記超小型電子素子の周縁部を越えて、少なくとも前記基板の周縁部に向かって延在する請求項1に記載のパッケージ。
- 前記パッケージコンタクトは導電性結合材料から本質的になる請求項1に記載のパッケージ。
- 前記パッケージコンタクトは実質的に硬質のポストを含む請求項1に記載のパッケージ。
- 少なくとも複数の導電性ポストの上面の少なくとも一部は、前記封入材の前記主面から下方に延在する開口部内に露出し、前記封入材は前記少なくとも複数のポストのエッジ面の少なくとも一部と接触する請求項4に記載のパッケージ。
- 前記少なくとも複数のポストの前記エッジ面は、前記封入材内の前記それぞれの開口部内に少なくとも部分的に露出する請求項5に記載のパッケージ。
- 前記封入材は、前記少なくとも複数のポストの前記上面が前記開口部内に部分的にのみ露出するように、前記少なくとも複数のポストの前記上面の少なくとも一部と接触する請求項5に記載のパッケージ。
- 前記少なくとも複数のポストのエッジ面は前記封入材によって完全に覆われる請求項7に記載のパッケージ。
- 前記導電性ポストの上面は前記封入材の前記主面と同一平面をなす請求項4に記載のパッケージ。
- 前記少なくとも複数のポストのエッジ面は前記封入材によって完全に覆われる請求項9に記載のパッケージ。
- 前記基板は第1の基板であり、前記パッケージは、前記第1の基板から離れている前記超小型電子素子の前記面の上に重なる第2の基板を更に備え、前記第2の基板は前記パッケージコンタクトのうちの少なくとも複数を前記超小型電子素子から分離する請求項1に記載のパッケージ。
- 前記第1の基板及び前記第2の基板は前記導電性素子を通して電気的に接続され、前記導電性素子は第1の導電性素子であり、前記パッケージは、少なくとも1つの第1の導電性素子とともに制御されたインピーダンスの伝送線路を形成するように基準電位に接続される少なくとも1つの第2の導電性素子を更に備える請求項1に記載のパッケージ。
- 前記導電性素子のうちの少なくとも複数は前記超小型電子素子と直接接続される請求項1又は11に記載のパッケージ。
- 前記超小型電子素子の前記素子コンタクトは前記第1の基板に面する請求項11に記載のパッケージ。
- 前記超小型電子素子の前記素子コンタクトは前記第1の基板から離れて面し、前記第1の基板と電気的に互いに接続される請求項11に記載のパッケージ。
- 前記超小型電子素子は第1の超小型電子素子であり、前記パッケージは前記第1の超小型電子素子と前記第2の基板との間に配置される第2の超小型電子素子を更に含み、前記第2の超小型電子素子は前記第1の基板及び前記第2の基板のうちの少なくとも1つと電気的に互いに接続される請求項14又は15に記載のパッケージ。
- 前記パッケージは第2の硬質の構造を更に備え、この第2の構造は前記第1の表面から少なくとも前記第2の基板まで突出する導電性構造、熱伝導性構造又はスペーサのうちの少なくとも1つである請求項11に記載のパッケージ。
- 前記第2の基板は誘電体素子を含む請求項17に記載のパッケージ。
- 前記パッケージコンタクトは、前記第2の基板の表面から離れるように突出する複数の硬質の導電性ポストを含む請求項11に記載のパッケージ。
- 前記第2の基板は第2の誘電体素子を含み、前記パッケージコンタクトは前記第2の誘電体素子の表面から離れるように突出する請求項19に記載のパッケージ。
- 前記第2の基板は複数の開口部を含み、前記導電性素子のうちの少なくとも複数は前記第2の基板内の前記開口部を通って延在する請求項19又は20に記載のパッケージ。
- 前記パッケージは前記第1の基板から離れるように延在する第2の硬質の導電性ポストを更に備え、第2の導電性ポストは前記第1の基板と電気的に接続され、前記第2の導電性ポストは前記封入材の前記主面において前記封入材のそれぞれの開口部内に露出する請求項19に記載のパッケージ。
- 超小型電子パッケージを形成する方法であって、
超小型電子アセンブリを配設するステップであって、このアセンブリは、
基板コンタクトと、第1の表面と、この第1の表面から離れている第2の表面と、この第2の表面において露出する複数の端子とを有する基板と、
前面と、この前面において露出する素子コンタクトと、この前面から離れている背面とを有する超小型電子素子であって、前記前面又は前記背面は前記第1の表面と並置される超小型電子素子とを備え、
この超小型電子アセンブリは、
前記第1の表面の上方に突出し、前記素子コンタクト及び前記基板コンタクトと電気的に接続される複数の導電性素子と、
前記基板の前記第1の表面と並置される前記面から離れている前記超小型電子素子の前記面の上に重なる複数のパッケージコンタクトであって、このパッケージコンタクトは前記導電性素子と電気的に互いに接続され、このパッケージコンタクトは前記超小型電子素子の前記素子コンタクトの高さより高く延在する導電性結合材料の塊状物又は硬質の導電性ポストのうちの少なくとも一方を含む、複数のパッケージコンタクトとを更に備える、配設するステップと、
その後、前記第1の表面と、前記導電性素子と、前記基板から離れている前記超小型電子素子の面の少なくとも一部との上に重なる封入材を形成するステップであって、この封入材は主面を画定し、前記パッケージコンタクトの上面の少なくとも一部はこの封入材の前記主面において露出する、形成するステップと
を含む超小型電子パッケージを形成する方法。 - 前記上面の前記少なくとも一部は前記封入材の前記主面と同一平面をなす請求項23に記載の方法。
- 超小型電子パッケージを形成する方法であって、
超小型電子アセンブリを配設するステップであって、このアセンブリは、
基板コンタクトと、第1の表面と、この第1の表面から離れている第2の表面と、この第2の表面において露出する複数の端子とを有する基板と、
前面と、この前面において露出する素子コンタクトと、この前面から離れている背面を有する超小型電子素子であって、前記前面又は前記背面は前記第1の表面と並置される超小型電子素子とを備え、
この超小型電子アセンブリは、
前記第1の表面の上方に突出し、前記素子コンタクト及び前記基板コンタクトと電気的に接続される複数の導電性素子と、
前記基板の前記第1の表面と並置される前記面から離れている前記超小型電子素子の前記面の上に重なる第2の導電性素子であって、この第2の導電性素子は前記導電性素子と電気的に互いに接続される、第2の導電性素子とを更に備える、配設するステップと、
その後、前記第1の表面と、前記導電性素子と、前記基板から離れている前記超小型電子素子の面の少なくとも一部との上に重なる封入材を形成するステップであって、この封入材は主面を画定する、形成するステップと、
その後、前記封入材内に開口部を形成して、前記第2の導電性素子を少なくとも部分的に露出させる、形成するステップと
を含む超小型電子パッケージを形成する方法。 - 前記第2の導電性素子は前記超小型電子パッケージのためのパッケージコンタクトとしての役割を果たす請求項25に記載の方法。
- 前記第2の導電性素子と導通するパッケージコンタクトを形成するステップを更に含む請求項25に記載の方法。
- 前記パッケージコンタクトを形成するステップは、前記開口部内の前記第2の導電性素子上に導電性ボンディング材料の塊状物を堆積するステップを含む請求項27に記載の方法。
- 前記導電性素子は、前記超小型電子素子の素子コンタクトを含む請求項28に記載の方法。
- 前記パッケージコンタクトを形成するステップは、前記開口部内に露出する前記第2の導電性素子上に導電性ポストをめっきすることを含む請求項27に記載の方法。
- 前記導電性素子は、前記超小型電子素子の素子コンタクトを含む請求項30に記載の方法。
- 前記パッケージコンタクトは硬質の導電性ポスト又は導電性塊状物のうちの少なくとも一方を含み、このパッケージコンタクトは前記基板の前記第1の表面から前記素子コンタクトの高さより高く延在する請求項26に記載の方法。
- 前記導電性ポストは前記基板の前記第1の面から離れている上面と、この上面から離れるように延在するエッジ面とを有し、前記開口部を形成するステップは前記エッジ面を少なくとも部分的に露出させる請求項32に記載の方法。
- 前記方法は、第1の超小型電子パッケージ及び第2の超小型電子パッケージをそれぞれ形成するために用いられ、前記第1の超小型電子パッケージの上に前記第2の超小型電子パッケージを積層するステップと、前記第1の超小型電子パッケージ及び前記第2の超小型電子パッケージを、この第1の超小型電子パッケージの前記パッケージコンタクトと、この第2の超小型電子パッケージの前記端子とを通して電気的に互いに接続するステップとを更に含む請求項23又は25に記載の方法。
- 前記方法は、第1の超小型電子パッケージ及び第2の超小型電子パッケージをそれぞれ形成するために用いられ、前記第1の超小型電子パッケージの上に前記第2の超小型電子パッケージを積層するステップと、前記第1の超小型電子パッケージ及び前記第2の超小型電子パッケージを、この第1の超小型電子パッケージの前記パッケージコンタクトと、この第2の超小型電子パッケージの前記パッケージコンタクトとを通して電気的に互いに接続するステップとを更に含む請求項23又は25に記載の方法。
- 前記方法は、第1の超小型電子パッケージ及び第2の超小型電子パッケージをそれぞれ形成するために用いられ、前記第1の超小型電子パッケージの上に前記第2の超小型電子パッケージを積層するステップと、前記第1の超小型電子パッケージ及び前記第2の超小型電子パッケージを、この第1の超小型電子パッケージの前記端子と、この第2の超小型電子パッケージの前記端子とを通して電気的に互いに接続するステップとを更に含む請求項23又は25に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/839,038 | 2010-07-19 | ||
US12/839,038 US9159708B2 (en) | 2010-07-19 | 2010-07-19 | Stackable molded microelectronic packages with area array unit connectors |
PCT/US2011/044342 WO2012012321A2 (en) | 2010-07-19 | 2011-07-18 | Stackable molded microelectronic packages with area array unit connectors |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016202866A Division JP2017038075A (ja) | 2010-07-19 | 2016-10-14 | エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2013535825A true JP2013535825A (ja) | 2013-09-12 |
JP2013535825A5 JP2013535825A5 (ja) | 2014-09-04 |
JP6027966B2 JP6027966B2 (ja) | 2016-11-16 |
Family
ID=44533104
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013520776A Active JP6027966B2 (ja) | 2010-07-19 | 2011-07-18 | エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ |
JP2016202866A Pending JP2017038075A (ja) | 2010-07-19 | 2016-10-14 | エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016202866A Pending JP2017038075A (ja) | 2010-07-19 | 2016-10-14 | エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ |
Country Status (7)
Country | Link |
---|---|
US (2) | US9159708B2 (ja) |
EP (1) | EP2596530A2 (ja) |
JP (2) | JP6027966B2 (ja) |
KR (2) | KR101734882B1 (ja) |
CN (2) | CN103201836B (ja) |
TW (1) | TWI460845B (ja) |
WO (1) | WO2012012321A2 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US8906743B2 (en) | 2013-01-11 | 2014-12-09 | Micron Technology, Inc. | Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
TWI557865B (zh) * | 2014-01-29 | 2016-11-11 | 矽品精密工業股份有限公司 | 堆疊組及其製法與基板結構 |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
WO2016043697A1 (en) * | 2014-09-15 | 2016-03-24 | Intel Corporation | Methods to form high density through-mold interconnections |
KR102289985B1 (ko) | 2014-12-08 | 2021-08-17 | 삼성디스플레이 주식회사 | 표시 장치 |
CN104538368A (zh) * | 2014-12-30 | 2015-04-22 | 华天科技(西安)有限公司 | 一种基于二次塑封技术的三维堆叠封装结构及其制备方法 |
TWI550805B (zh) * | 2015-04-20 | 2016-09-21 | 南茂科技股份有限公司 | 晶片堆疊封裝結構 |
CN106486453A (zh) * | 2015-08-25 | 2017-03-08 | 力成科技股份有限公司 | 一种柱顶互连型态半导体封装构造及其制造方法 |
US9842820B1 (en) * | 2015-12-04 | 2017-12-12 | Altera Corporation | Wafer-level fan-out wirebond packages |
CN110024115B (zh) * | 2016-10-04 | 2024-02-02 | 天工方案公司 | 具有包覆模制结构的双侧射频封装 |
US20180114786A1 (en) * | 2016-10-21 | 2018-04-26 | Powertech Technology Inc. | Method of forming package-on-package structure |
FR3060846B1 (fr) * | 2016-12-19 | 2019-05-24 | Institut Vedecom | Procede d’integration de puces de puissance et de bus barres formant dissipateurs thermiques |
TWI675441B (zh) * | 2018-05-14 | 2019-10-21 | 欣興電子股份有限公司 | 封裝載板結構及其製造方法 |
CN109801894A (zh) * | 2018-12-28 | 2019-05-24 | 华进半导体封装先导技术研发中心有限公司 | 芯片封装结构和封装方法 |
KR102574414B1 (ko) | 2019-05-21 | 2023-09-04 | 삼성전기주식회사 | 전자 부품 모듈 |
JP2021041375A (ja) * | 2019-09-13 | 2021-03-18 | 株式会社東芝 | 導電性流体用吐出ヘッド |
US11410902B2 (en) | 2019-09-16 | 2022-08-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US20230015323A1 (en) * | 2021-07-19 | 2023-01-19 | Texas Instruments Incorporated | Semiconductor package with topside cooling |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004172157A (ja) * | 2002-11-15 | 2004-06-17 | Shinko Electric Ind Co Ltd | 半導体パッケージおよびパッケージスタック半導体装置 |
JP2004319892A (ja) * | 2003-04-18 | 2004-11-11 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2006344917A (ja) * | 2005-06-10 | 2006-12-21 | Sharp Corp | 半導体装置、積層型半導体装置、および半導体装置の製造方法 |
JP2007208159A (ja) * | 2006-02-06 | 2007-08-16 | Hitachi Ltd | 半導体装置 |
JP2009506553A (ja) * | 2005-08-31 | 2009-02-12 | マイクロン テクノロジー, インク. | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
JP2009508324A (ja) * | 2005-08-19 | 2009-02-26 | マイクロン テクノロジー, インク. | マイクロ電子デバイス、積み重ねられたマイクロ電子デバイス、およびマイクロ電子デバイスを製造する方法 |
US20090206461A1 (en) * | 2008-02-15 | 2009-08-20 | Qimonda Ag | Integrated circuit and method |
US20090236753A1 (en) * | 2008-03-21 | 2009-09-24 | Moon Dongsoo | Integrated circuit package system for stackable devices |
US20100032822A1 (en) * | 2008-08-07 | 2010-02-11 | Advanced Semiconductor Engineering, Inc. | Chip package structure |
WO2010041630A1 (ja) * | 2008-10-10 | 2010-04-15 | 日本電気株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (473)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1439262B2 (de) | 1963-07-23 | 1972-03-30 | Siemens AG, 1000 Berlin u. 8000 München | Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression |
US3358897A (en) | 1964-03-31 | 1967-12-19 | Tempress Res Co | Electric lead wire bonding tools |
US3623649A (en) | 1969-06-09 | 1971-11-30 | Gen Motors Corp | Wedge bonding tool for the attachment of semiconductor leads |
DE2119567C2 (de) | 1970-05-05 | 1983-07-14 | International Computers Ltd., London | Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung |
DE2228703A1 (de) | 1972-06-13 | 1974-01-10 | Licentia Gmbh | Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen |
US4327860A (en) | 1980-01-03 | 1982-05-04 | Kulicke And Soffa Ind. Inc. | Method of making slack free wire interconnections |
US4422568A (en) | 1981-01-12 | 1983-12-27 | Kulicke And Soffa Industries, Inc. | Method of making constant bonding wire tail lengths |
US4437604A (en) | 1982-03-15 | 1984-03-20 | Kulicke & Soffa Industries, Inc. | Method of making fine wire interconnections |
JPS59189069U (ja) | 1983-06-02 | 1984-12-14 | 昭和アルミニウム株式会社 | 冷却装置 |
JPS61125062A (ja) | 1984-11-22 | 1986-06-12 | Hitachi Ltd | ピン取付け方法およびピン取付け装置 |
US4604644A (en) | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
JP2608701B2 (ja) | 1985-09-19 | 1997-05-14 | 三菱電機株式会社 | 保護装置の点検回路 |
US5917707A (en) | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
US5476211A (en) | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US4924353A (en) | 1985-12-20 | 1990-05-08 | Hughes Aircraft Company | Connector system for coupling to an integrated circuit chip |
US4716049A (en) | 1985-12-20 | 1987-12-29 | Hughes Aircraft Company | Compressive pedestal for microminiature connections |
JPS62158338A (ja) | 1985-12-28 | 1987-07-14 | Tanaka Denshi Kogyo Kk | 半導体装置 |
US4793814A (en) | 1986-07-21 | 1988-12-27 | Rogers Corporation | Electrical circuit board interconnect |
US4695870A (en) | 1986-03-27 | 1987-09-22 | Hughes Aircraft Company | Inverted chip carrier |
JPS62226307A (ja) | 1986-03-28 | 1987-10-05 | Toshiba Corp | ロボツト装置 |
US4771930A (en) | 1986-06-30 | 1988-09-20 | Kulicke And Soffa Industries Inc. | Apparatus for supplying uniform tail lengths |
JPS6397941A (ja) | 1986-10-14 | 1988-04-28 | Fuji Photo Film Co Ltd | 感光材料 |
KR970003915B1 (ko) | 1987-06-24 | 1997-03-22 | 미다 가쓰시게 | 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈 |
US5138438A (en) | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
JP2642359B2 (ja) | 1987-09-11 | 1997-08-20 | 株式会社日立製作所 | 半導体装置 |
US4804132A (en) | 1987-08-28 | 1989-02-14 | Difrancesco Louis | Method for cold bonding |
US4845354A (en) | 1988-03-08 | 1989-07-04 | International Business Machines Corporation | Process control for laser wire bonding |
US4998885A (en) | 1989-10-27 | 1991-03-12 | International Business Machines Corporation | Elastomeric area array interposer |
US5077598A (en) | 1989-11-08 | 1991-12-31 | Hewlett-Packard Company | Strain relief flip-chip integrated circuit assembly with test fixturing |
US5095187A (en) | 1989-12-20 | 1992-03-10 | Raychem Corporation | Weakening wire supplied through a wire bonder |
AU637874B2 (en) | 1990-01-23 | 1993-06-10 | Sumitomo Electric Industries, Ltd. | Substrate for packaging a semiconductor device |
AU645283B2 (en) | 1990-01-23 | 1994-01-13 | Sumitomo Electric Industries, Ltd. | Substrate for packaging a semiconductor device |
US5083697A (en) | 1990-02-14 | 1992-01-28 | Difrancesco Louis | Particle-enhanced joining of metal surfaces |
US4975079A (en) | 1990-02-23 | 1990-12-04 | International Business Machines Corp. | Connector assembly for chip testing |
US4999472A (en) | 1990-03-12 | 1991-03-12 | Neinast James E | Electric arc system for ablating a surface coating |
US5241456A (en) | 1990-07-02 | 1993-08-31 | General Electric Company | Compact high density interconnect structure |
US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5067382A (en) | 1990-11-02 | 1991-11-26 | Cray Computer Corporation | Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire |
KR940001149B1 (ko) | 1991-04-16 | 1994-02-14 | 삼성전자 주식회사 | 반도체 장치의 칩 본딩 방법 |
JPH04346436A (ja) | 1991-05-24 | 1992-12-02 | Fujitsu Ltd | バンプ製造方法とバンプ製造装置 |
WO1993004375A1 (en) | 1991-08-23 | 1993-03-04 | Nchip, Inc. | Burn-in technologies for unpackaged integrated circuits |
US5220489A (en) | 1991-10-11 | 1993-06-15 | Motorola, Inc. | Multicomponent integrated circuit package |
JP2931936B2 (ja) | 1992-01-17 | 1999-08-09 | 株式会社日立製作所 | 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置 |
US5831836A (en) | 1992-01-30 | 1998-11-03 | Lsi Logic | Power plane for semiconductor device |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5438224A (en) | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
US5494667A (en) | 1992-06-04 | 1996-02-27 | Kabushiki Kaisha Hayahibara | Topically applied hair restorer containing pine extract |
US6054756A (en) | 1992-07-24 | 2000-04-25 | Tessera, Inc. | Connection components with frangible leads and bus |
KR100209457B1 (ko) | 1992-07-24 | 1999-07-15 | 토마스 디스테파노 | 반도체 접속 부품과 그 제조 방법 및 반도체 칩 접속 방법 |
US5977618A (en) | 1992-07-24 | 1999-11-02 | Tessera, Inc. | Semiconductor connection components and methods with releasable lead support |
US5371654A (en) | 1992-10-19 | 1994-12-06 | International Business Machines Corporation | Three dimensional high performance interconnection package |
US6295729B1 (en) | 1992-10-19 | 2001-10-02 | International Business Machines Corporation | Angled flying lead wire bonding process |
US20050062492A1 (en) | 2001-08-03 | 2005-03-24 | Beaman Brian Samuel | High density integrated circuit apparatus, test probe and methods of use thereof |
JP2716336B2 (ja) | 1993-03-10 | 1998-02-18 | 日本電気株式会社 | 集積回路装置 |
JPH06268101A (ja) | 1993-03-17 | 1994-09-22 | Hitachi Ltd | 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板 |
US5340771A (en) | 1993-03-18 | 1994-08-23 | Lsi Logic Corporation | Techniques for providing high I/O count connections to semiconductor dies |
US20030048108A1 (en) | 1993-04-30 | 2003-03-13 | Beaman Brian Samuel | Structural design and processes to control probe position accuracy in a wafer test probe assembly |
US7368924B2 (en) | 1993-04-30 | 2008-05-06 | International Business Machines Corporation | Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof |
US5811982A (en) | 1995-11-27 | 1998-09-22 | International Business Machines Corporation | High density cantilevered probe for electronic devices |
JP2981385B2 (ja) | 1993-09-06 | 1999-11-22 | シャープ株式会社 | チップ部品型ledの構造及びその製造方法 |
US5346118A (en) | 1993-09-28 | 1994-09-13 | At&T Bell Laboratories | Surface mount solder assembly of leadless integrated circuit packages to substrates |
US6835898B2 (en) | 1993-11-16 | 2004-12-28 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
US5455390A (en) | 1994-02-01 | 1995-10-03 | Tessera, Inc. | Microelectronics unit mounting with multiple lead bonding |
WO1995026047A1 (en) | 1994-03-18 | 1995-09-28 | Hitachi Chemical Company, Ltd. | Semiconductor package manufacturing method and semiconductor package |
US5615824A (en) | 1994-06-07 | 1997-04-01 | Tessera, Inc. | Soldering with resilient contacts |
US5802699A (en) | 1994-06-07 | 1998-09-08 | Tessera, Inc. | Methods of assembling microelectronic assembly with socket for engaging bump leads |
JPH07335783A (ja) | 1994-06-13 | 1995-12-22 | Fujitsu Ltd | 半導体装置及び半導体装置ユニット |
US5468995A (en) | 1994-07-05 | 1995-11-21 | Motorola, Inc. | Semiconductor device having compliant columnar electrical connections |
US6177636B1 (en) | 1994-12-29 | 2001-01-23 | Tessera, Inc. | Connection components with posts |
US5989936A (en) | 1994-07-07 | 1999-11-23 | Tessera, Inc. | Microelectronic assembly fabrication with terminal formation from a conductive layer |
US6117694A (en) | 1994-07-07 | 2000-09-12 | Tessera, Inc. | Flexible lead structures and methods of making same |
US5688716A (en) | 1994-07-07 | 1997-11-18 | Tessera, Inc. | Fan-out semiconductor chip assembly |
US5518964A (en) | 1994-07-07 | 1996-05-21 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation and bonding |
US6828668B2 (en) | 1994-07-07 | 2004-12-07 | Tessera, Inc. | Flexible lead structures and methods of making same |
US5656550A (en) | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
US5659952A (en) | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5541567A (en) | 1994-10-17 | 1996-07-30 | International Business Machines Corporation | Coaxial vias in an electronic substrate |
US5495667A (en) | 1994-11-07 | 1996-03-05 | Micron Technology, Inc. | Method for forming contact pins for semiconductor dice and interconnects |
US5736074A (en) | 1995-06-30 | 1998-04-07 | Micro Fab Technologies, Inc. | Manufacture of coated spheres |
US5971253A (en) | 1995-07-31 | 1999-10-26 | Tessera, Inc. | Microelectronic component mounting with deformable shell terminals |
US5872051A (en) | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
US5810609A (en) | 1995-08-28 | 1998-09-22 | Tessera, Inc. | Socket for engaging bump leads on a microelectronic device and methods therefor |
US5766987A (en) | 1995-09-22 | 1998-06-16 | Tessera, Inc. | Microelectronic encapsulation methods and equipment |
US6211572B1 (en) | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
JP3332308B2 (ja) | 1995-11-07 | 2002-10-07 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JPH09134934A (ja) | 1995-11-07 | 1997-05-20 | Sumitomo Metal Ind Ltd | 半導体パッケージ及び半導体装置 |
US5718361A (en) | 1995-11-21 | 1998-02-17 | International Business Machines Corporation | Apparatus and method for forming mold for metallic material |
US5731709A (en) | 1996-01-26 | 1998-03-24 | Motorola, Inc. | Method for testing a ball grid array semiconductor device and a device for such testing |
US5994152A (en) | 1996-02-21 | 1999-11-30 | Formfactor, Inc. | Fabricating interconnects and tips using sacrificial substrates |
US6000126A (en) | 1996-03-29 | 1999-12-14 | General Dynamics Information Systems, Inc. | Method and apparatus for connecting area grid arrays to printed wire board |
US6821821B2 (en) | 1996-04-18 | 2004-11-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
DE19618227A1 (de) | 1996-05-07 | 1997-11-13 | Herbert Streckfus Gmbh | Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte |
KR100186333B1 (ko) | 1996-06-20 | 1999-03-20 | 문정환 | 칩 사이즈 반도체 패키지 및 그 제조방법 |
JPH10135221A (ja) | 1996-10-29 | 1998-05-22 | Taiyo Yuden Co Ltd | バンプ形成方法 |
JPH10135220A (ja) | 1996-10-29 | 1998-05-22 | Taiyo Yuden Co Ltd | バンプ形成方法 |
US6492719B2 (en) | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
US5976913A (en) | 1996-12-12 | 1999-11-02 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation using restraining straps |
US6133072A (en) | 1996-12-13 | 2000-10-17 | Tessera, Inc. | Microelectronic connector with planar elastomer sockets |
US6121676A (en) | 1996-12-13 | 2000-09-19 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US6054337A (en) | 1996-12-13 | 2000-04-25 | Tessera, Inc. | Method of making a compliant multichip package |
US6225688B1 (en) | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
JP3400279B2 (ja) | 1997-01-13 | 2003-04-28 | 株式会社新川 | バンプ形成方法 |
US5898991A (en) | 1997-01-16 | 1999-05-04 | International Business Machines Corporation | Methods of fabrication of coaxial vias and magnetic devices |
US5839191A (en) | 1997-01-24 | 1998-11-24 | Unisys Corporation | Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package |
US6495914B1 (en) | 1997-08-19 | 2002-12-17 | Hitachi, Ltd. | Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate |
CA2213590C (en) | 1997-08-21 | 2006-11-07 | Keith C. Carroll | Flexible circuit connector and method of making same |
JP3859318B2 (ja) | 1997-08-29 | 2006-12-20 | シチズン電子株式会社 | 電子回路のパッケージ方法 |
JP3937265B2 (ja) | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | 半導体装置 |
JP2978861B2 (ja) | 1997-10-28 | 1999-11-15 | 九州日本電気株式会社 | モールドbga型半導体装置及びその製造方法 |
US6038136A (en) | 1997-10-29 | 2000-03-14 | Hestia Technologies, Inc. | Chip package with molded underfill |
JP3393800B2 (ja) | 1997-11-05 | 2003-04-07 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JPH11219984A (ja) | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
US6222136B1 (en) | 1997-11-12 | 2001-04-24 | International Business Machines Corporation | Printed circuit board with continuous connective bumps |
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
US6002168A (en) | 1997-11-25 | 1999-12-14 | Tessera, Inc. | Microelectronic component with rigid interposer |
JPH11163022A (ja) | 1997-11-28 | 1999-06-18 | Sony Corp | 半導体装置、その製造方法及び電子機器 |
US6124546A (en) | 1997-12-03 | 2000-09-26 | Advanced Micro Devices, Inc. | Integrated circuit chip package and method of making the same |
US6260264B1 (en) | 1997-12-08 | 2001-07-17 | 3M Innovative Properties Company | Methods for making z-axis electrical connections |
US6052287A (en) | 1997-12-09 | 2000-04-18 | Sandia Corporation | Silicon ball grid array chip carrier |
US5973391A (en) | 1997-12-11 | 1999-10-26 | Read-Rite Corporation | Interposer with embedded circuitry and method for using the same to package microelectronic units |
JPH11220082A (ja) | 1998-02-03 | 1999-08-10 | Oki Electric Ind Co Ltd | 半導体装置 |
JP3536650B2 (ja) | 1998-02-27 | 2004-06-14 | 富士ゼロックス株式会社 | バンプ形成方法および装置 |
JPH11260856A (ja) | 1998-03-11 | 1999-09-24 | Matsushita Electron Corp | 半導体装置及びその製造方法並びに半導体装置の実装構造 |
KR100260997B1 (ko) | 1998-04-08 | 2000-07-01 | 마이클 디. 오브라이언 | 반도체패키지 |
US6329224B1 (en) | 1998-04-28 | 2001-12-11 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
US6180881B1 (en) | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
KR100266693B1 (ko) | 1998-05-30 | 2000-09-15 | 김영환 | 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법 |
KR100265563B1 (ko) | 1998-06-29 | 2000-09-15 | 김영환 | 볼 그리드 어레이 패키지 및 그의 제조 방법 |
US6414391B1 (en) | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
US6164523A (en) | 1998-07-01 | 2000-12-26 | Semiconductor Components Industries, Llc | Electronic component and method of manufacture |
US5854507A (en) | 1998-07-21 | 1998-12-29 | Hewlett-Packard Company | Multiple chip assembly |
US6515355B1 (en) | 1998-09-02 | 2003-02-04 | Micron Technology, Inc. | Passivation layer for packaged integrated circuits |
JP2000091383A (ja) | 1998-09-07 | 2000-03-31 | Ngk Spark Plug Co Ltd | 配線基板 |
US6194250B1 (en) | 1998-09-14 | 2001-02-27 | Motorola, Inc. | Low-profile microelectronic package |
US6158647A (en) | 1998-09-29 | 2000-12-12 | Micron Technology, Inc. | Concave face wire bond capillary |
US6684007B2 (en) | 1998-10-09 | 2004-01-27 | Fujitsu Limited | Optical coupling structures and the fabrication processes |
US6268662B1 (en) | 1998-10-14 | 2001-07-31 | Texas Instruments Incorporated | Wire bonded flip-chip assembly of semiconductor devices |
JP3407275B2 (ja) | 1998-10-28 | 2003-05-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | バンプ及びその形成方法 |
US6332270B2 (en) | 1998-11-23 | 2001-12-25 | International Business Machines Corporation | Method of making high density integral test probe |
US6206273B1 (en) | 1999-02-17 | 2001-03-27 | International Business Machines Corporation | Structures and processes to create a desired probetip contact geometry on a wafer test probe |
KR100319609B1 (ko) | 1999-03-09 | 2002-01-05 | 김영환 | 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법 |
US6177729B1 (en) | 1999-04-03 | 2001-01-23 | International Business Machines Corporation | Rolling ball connector |
US6258625B1 (en) | 1999-05-18 | 2001-07-10 | International Business Machines Corporation | Method of interconnecting electronic components using a plurality of conductive studs |
US6376769B1 (en) | 1999-05-18 | 2002-04-23 | Amerasia International Technology, Inc. | High-density electronic package, and method for making same |
JP3398721B2 (ja) | 1999-05-20 | 2003-04-21 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ及びその製造方法 |
US6228687B1 (en) | 1999-06-28 | 2001-05-08 | Micron Technology, Inc. | Wafer-level package and methods of fabricating |
TW417839U (en) | 1999-07-30 | 2001-01-01 | Shen Ming Tung | Stacked memory module structure and multi-layered stacked memory module structure using the same |
US6168965B1 (en) | 1999-08-12 | 2001-01-02 | Tower Semiconductor Ltd. | Method for making backside illuminated image sensor |
JP4526651B2 (ja) | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP5333337B2 (ja) | 1999-08-12 | 2013-11-06 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
EP2265101B1 (en) | 1999-09-02 | 2012-08-29 | Ibiden Co., Ltd. | Printed circuit board and method of manufacturing printed circuit board |
US6867499B1 (en) | 1999-09-30 | 2005-03-15 | Skyworks Solutions, Inc. | Semiconductor packaging |
JP3513444B2 (ja) | 1999-10-20 | 2004-03-31 | 株式会社新川 | ピン状ワイヤ等の形成方法 |
JP2001127246A (ja) | 1999-10-29 | 2001-05-11 | Fujitsu Ltd | 半導体装置 |
US6362525B1 (en) | 1999-11-09 | 2002-03-26 | Cypress Semiconductor Corp. | Circuit structure including a passive element formed within a grid array substrate and method for making the same |
JP3619410B2 (ja) | 1999-11-18 | 2005-02-09 | 株式会社ルネサステクノロジ | バンプ形成方法およびそのシステム |
JP3798597B2 (ja) | 1999-11-30 | 2006-07-19 | 富士通株式会社 | 半導体装置 |
JP3566156B2 (ja) | 1999-12-02 | 2004-09-15 | 株式会社新川 | ピン状ワイヤ等の形成方法 |
US6790757B1 (en) | 1999-12-20 | 2004-09-14 | Agere Systems Inc. | Wire bonding method for copper interconnects in semiconductor devices |
KR100426494B1 (ko) | 1999-12-20 | 2004-04-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 이것의 제조방법 |
JP2001196407A (ja) | 2000-01-14 | 2001-07-19 | Seiko Instruments Inc | 半導体装置および半導体装置の形成方法 |
US6710454B1 (en) | 2000-02-16 | 2004-03-23 | Micron Technology, Inc. | Adhesive layer for an electronic apparatus having multiple semiconductor devices |
JP2001339011A (ja) | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3980807B2 (ja) | 2000-03-27 | 2007-09-26 | 株式会社東芝 | 半導体装置及び半導体モジュール |
JP2001274196A (ja) | 2000-03-28 | 2001-10-05 | Rohm Co Ltd | 半導体装置 |
KR100583491B1 (ko) | 2000-04-07 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조방법 |
US6578754B1 (en) | 2000-04-27 | 2003-06-17 | Advanpack Solutions Pte. Ltd. | Pillar connections for semiconductor chips and method of manufacture |
US6531335B1 (en) | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
JP2001326236A (ja) | 2000-05-12 | 2001-11-22 | Nec Kyushu Ltd | 半導体装置の製造方法 |
US6522018B1 (en) | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US6647310B1 (en) | 2000-05-30 | 2003-11-11 | Advanced Micro Devices, Inc. | Temperature control of an integrated circuit |
US6531784B1 (en) | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
US6560117B2 (en) | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
US6476583B2 (en) | 2000-07-21 | 2002-11-05 | Jomahip, Llc | Automatic battery charging system for a battery back-up DC power supply |
SE517086C2 (sv) | 2000-08-08 | 2002-04-09 | Ericsson Telefon Ab L M | Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat |
US20020020898A1 (en) | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
US6462575B1 (en) | 2000-08-28 | 2002-10-08 | Micron Technology, Inc. | Method and system for wafer level testing and burning-in semiconductor components |
JP3874062B2 (ja) | 2000-09-05 | 2007-01-31 | セイコーエプソン株式会社 | 半導体装置 |
US6507104B2 (en) | 2000-09-07 | 2003-01-14 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with embedded heat-dissipating device |
US7009297B1 (en) | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
US6423570B1 (en) | 2000-10-18 | 2002-07-23 | Intel Corporation | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby |
JP4505983B2 (ja) | 2000-12-01 | 2010-07-21 | 日本電気株式会社 | 半導体装置 |
JP3798620B2 (ja) * | 2000-12-04 | 2006-07-19 | 富士通株式会社 | 半導体装置の製造方法 |
TW511405B (en) | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
KR100393102B1 (ko) | 2000-12-29 | 2003-07-31 | 앰코 테크놀로지 코리아 주식회사 | 스택형 반도체패키지 |
AUPR244801A0 (en) | 2001-01-10 | 2001-02-01 | Silverbrook Research Pty Ltd | A method and apparatus (WSM01) |
US6388322B1 (en) | 2001-01-17 | 2002-05-14 | Aralight, Inc. | Article comprising a mechanically compliant bump |
JP2002280414A (ja) | 2001-03-22 | 2002-09-27 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002289769A (ja) | 2001-03-26 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 積層型半導体装置およびその製造方法 |
SG108245A1 (en) | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
US7115986B2 (en) | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
TW544826B (en) | 2001-05-18 | 2003-08-01 | Nec Electronics Corp | Flip-chip-type semiconductor device and manufacturing method thereof |
US6930256B1 (en) | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US6754407B2 (en) | 2001-06-26 | 2004-06-22 | Intel Corporation | Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board |
US20030006494A1 (en) | 2001-07-03 | 2003-01-09 | Lee Sang Ho | Thin profile stackable semiconductor package and method for manufacturing |
US6451626B1 (en) | 2001-07-27 | 2002-09-17 | Charles W.C. Lin | Three-dimensional stacked semiconductor package |
US6765287B1 (en) | 2001-07-27 | 2004-07-20 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
JP4023159B2 (ja) | 2001-07-31 | 2007-12-19 | ソニー株式会社 | 半導体装置の製造方法及び積層半導体装置の製造方法 |
US6550666B2 (en) | 2001-08-21 | 2003-04-22 | Advanpack Solutions Pte Ltd | Method for forming a flip chip on leadframe semiconductor package |
US7605479B2 (en) | 2001-08-22 | 2009-10-20 | Tessera, Inc. | Stacked chip assembly with encapsulant layer |
US7176506B2 (en) | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
US20030057544A1 (en) | 2001-09-13 | 2003-03-27 | Nathan Richard J. | Integrated assembly protocol |
US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
US6897565B2 (en) | 2001-10-09 | 2005-05-24 | Tessera, Inc. | Stacked packages |
JP2003122611A (ja) | 2001-10-11 | 2003-04-25 | Oki Electric Ind Co Ltd | データ提供方法及びサーバ装置 |
JP4257771B2 (ja) | 2001-10-16 | 2009-04-22 | シンジーテック株式会社 | 導電性ブレード |
JP3875077B2 (ja) | 2001-11-16 | 2007-01-31 | 富士通株式会社 | 電子デバイス及びデバイス接続方法 |
US20030094666A1 (en) | 2001-11-16 | 2003-05-22 | R-Tec Corporation | Interposer |
JP2003174124A (ja) | 2001-12-04 | 2003-06-20 | Sainekkusu:Kk | 半導体装置の外部電極形成方法 |
JP3507059B2 (ja) | 2002-06-27 | 2004-03-15 | 沖電気工業株式会社 | 積層マルチチップパッケージ |
JP2003197669A (ja) | 2001-12-28 | 2003-07-11 | Seiko Epson Corp | ボンディング方法及びボンディング装置 |
TW584950B (en) | 2001-12-31 | 2004-04-21 | Megic Corp | Chip packaging structure and process thereof |
JP3935370B2 (ja) | 2002-02-19 | 2007-06-20 | セイコーエプソン株式会社 | バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器 |
SG115456A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
US6653723B2 (en) | 2002-03-09 | 2003-11-25 | Fujitsu Limited | System for providing an open-cavity low profile encapsulated semiconductor package |
KR100452819B1 (ko) | 2002-03-18 | 2004-10-15 | 삼성전기주식회사 | 칩 패키지 및 그 제조방법 |
US6979230B2 (en) | 2002-03-20 | 2005-12-27 | Gabe Cherian | Light socket |
US7323767B2 (en) | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
JP2004047702A (ja) | 2002-07-11 | 2004-02-12 | Toshiba Corp | 半導体装置積層モジュール |
US6756252B2 (en) | 2002-07-17 | 2004-06-29 | Texas Instrument Incorporated | Multilayer laser trim interconnect method |
US6987032B1 (en) | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
AU2003265417A1 (en) | 2002-08-16 | 2004-03-03 | Tessera, Inc. | Microelectronic packages with self-aligning features |
TW549592U (en) | 2002-08-16 | 2003-08-21 | Via Tech Inc | Integrated circuit package with a balanced-part structure |
US6740546B2 (en) | 2002-08-21 | 2004-05-25 | Micron Technology, Inc. | Packaged microelectronic devices and methods for assembling microelectronic devices |
US6964881B2 (en) | 2002-08-27 | 2005-11-15 | Micron Technology, Inc. | Multi-chip wafer level system packages and methods of forming same |
JP2004095799A (ja) | 2002-08-30 | 2004-03-25 | Toshiba Corp | 半導体装置およびその製造方法 |
US7294928B2 (en) | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US7246431B2 (en) | 2002-09-06 | 2007-07-24 | Tessera, Inc. | Methods of making microelectronic packages including folded substrates |
US7071547B2 (en) | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
US7229906B2 (en) | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
US7259445B2 (en) | 2002-09-30 | 2007-08-21 | Advanced Interconnect Technologies Limited | Thermal enhanced package for block mold assembly |
US7045884B2 (en) | 2002-10-04 | 2006-05-16 | International Rectifier Corporation | Semiconductor device package |
JP2006502596A (ja) | 2002-10-08 | 2006-01-19 | チップパック,インク. | 裏返しにされた第二のパッケージを有する積み重ねられた半導体マルチパッケージモジュール |
TW567601B (en) | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
TWI221664B (en) | 2002-11-07 | 2004-10-01 | Via Tech Inc | Structure of chip package and process thereof |
JP2004172477A (ja) | 2002-11-21 | 2004-06-17 | Kaijo Corp | ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置 |
JP4464041B2 (ja) | 2002-12-13 | 2010-05-19 | キヤノン株式会社 | 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法 |
KR100621991B1 (ko) | 2003-01-03 | 2006-09-13 | 삼성전자주식회사 | 칩 스케일 적층 패키지 |
JP2004221257A (ja) | 2003-01-14 | 2004-08-05 | Seiko Epson Corp | ワイヤボンディング方法及びワイヤボンディング装置 |
WO2004077525A2 (en) | 2003-02-25 | 2004-09-10 | Tessera, Inc. | Ball grid array with bumps |
US20040217471A1 (en) | 2003-02-27 | 2004-11-04 | Tessera, Inc. | Component and assemblies with ends offset downwardly |
JP3885747B2 (ja) | 2003-03-13 | 2007-02-28 | 株式会社デンソー | ワイヤボンディング方法 |
JP2004343030A (ja) | 2003-03-31 | 2004-12-02 | North:Kk | 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール |
JP4199588B2 (ja) | 2003-04-25 | 2008-12-17 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法 |
DE10320646A1 (de) | 2003-05-07 | 2004-09-16 | Infineon Technologies Ag | Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben |
JP4145730B2 (ja) | 2003-06-17 | 2008-09-03 | 松下電器産業株式会社 | 半導体内蔵モジュール |
US20040262728A1 (en) | 2003-06-30 | 2004-12-30 | Sterrett Terry L. | Modular device assemblies |
KR100604821B1 (ko) | 2003-06-30 | 2006-07-26 | 삼성전자주식회사 | 적층형 볼 그리드 어레이 패키지 및 그 제조방법 |
US7227095B2 (en) | 2003-08-06 | 2007-06-05 | Micron Technology, Inc. | Wire bonders and methods of wire-bonding |
KR100546374B1 (ko) | 2003-08-28 | 2006-01-26 | 삼성전자주식회사 | 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법 |
US7372151B1 (en) | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US7061096B2 (en) | 2003-09-24 | 2006-06-13 | Silicon Pipe, Inc. | Multi-surface IC packaging structures and methods for their manufacture |
US7129576B2 (en) | 2003-09-26 | 2006-10-31 | Tessera, Inc. | Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps |
US7462936B2 (en) | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
JP4272968B2 (ja) | 2003-10-16 | 2009-06-03 | エルピーダメモリ株式会社 | 半導体装置および半導体チップ制御方法 |
JP4167965B2 (ja) | 2003-11-07 | 2008-10-22 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 配線回路用部材の製造方法 |
KR100564585B1 (ko) | 2003-11-13 | 2006-03-28 | 삼성전자주식회사 | 이중 스택된 bga 패키지 및 다중 스택된 bga 패키지 |
TWI227555B (en) | 2003-11-17 | 2005-02-01 | Advanced Semiconductor Eng | Structure of chip package and the process thereof |
KR100621992B1 (ko) | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지 |
JP2005183923A (ja) | 2003-11-28 | 2005-07-07 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US7345361B2 (en) | 2003-12-04 | 2008-03-18 | Intel Corporation | Stackable integrated circuit packaging |
JP2005175019A (ja) | 2003-12-08 | 2005-06-30 | Sharp Corp | 半導体装置及び積層型半導体装置 |
JP5197961B2 (ja) * | 2003-12-17 | 2013-05-15 | スタッツ・チップパック・インコーポレイテッド | マルチチップパッケージモジュールおよびその製造方法 |
DE10360708B4 (de) | 2003-12-19 | 2008-04-10 | Infineon Technologies Ag | Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben |
JP4334996B2 (ja) | 2003-12-24 | 2009-09-30 | 株式会社フジクラ | 多層配線板用基材、両面配線板およびそれらの製造方法 |
US7495644B2 (en) | 2003-12-26 | 2009-02-24 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing display device |
US6900530B1 (en) | 2003-12-29 | 2005-05-31 | Ramtek Technology, Inc. | Stacked IC |
US6917098B1 (en) | 2003-12-29 | 2005-07-12 | Texas Instruments Incorporated | Three-level leadframe for no-lead packages |
US8207604B2 (en) | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
US7709968B2 (en) | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
US7176043B2 (en) | 2003-12-30 | 2007-02-13 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP2005203497A (ja) | 2004-01-14 | 2005-07-28 | Toshiba Corp | 半導体装置およびその製造方法 |
US20050173807A1 (en) | 2004-02-05 | 2005-08-11 | Jianbai Zhu | High density vertically stacked semiconductor device |
US8399972B2 (en) | 2004-03-04 | 2013-03-19 | Skyworks Solutions, Inc. | Overmolded semiconductor package with a wirebond cage for EMI shielding |
US7095105B2 (en) | 2004-03-23 | 2006-08-22 | Texas Instruments Incorporated | Vertically stacked semiconductor device |
JP4484035B2 (ja) | 2004-04-06 | 2010-06-16 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US8092734B2 (en) | 2004-05-13 | 2012-01-10 | Aptina Imaging Corporation | Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers |
US6962864B1 (en) | 2004-05-26 | 2005-11-08 | National Chung Cheng University | Wire-bonding method for chips with copper interconnects by introducing a thin layer |
US7233057B2 (en) | 2004-05-28 | 2007-06-19 | Nokia Corporation | Integrated circuit package with optimized mold shape |
US7453157B2 (en) | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP4385329B2 (ja) | 2004-10-08 | 2009-12-16 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
EP2039460A3 (de) | 2004-11-02 | 2014-07-02 | HID Global GmbH | Verlegevorrichtung, Kontaktiervorrichtung, Zustellsystem, Verlege- und Kontaktiereinheit, herstellungsanlage, Verfahren zur Herstellung und eine Transpondereinheit |
US8525314B2 (en) | 2004-11-03 | 2013-09-03 | Tessera, Inc. | Stacked packaging improvements |
US7268421B1 (en) | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
US7750483B1 (en) | 2004-11-10 | 2010-07-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal |
US7440722B2 (en) | 2004-11-30 | 2008-10-21 | Palo Alto Research Center Incorporated | Xerography methods and systems employing addressable fusing of unfused toner image |
KR100674926B1 (ko) | 2004-12-08 | 2007-01-26 | 삼성전자주식회사 | 메모리 카드 및 그 제조 방법 |
JP4504798B2 (ja) | 2004-12-16 | 2010-07-14 | パナソニック株式会社 | 多段構成半導体モジュール |
JP2006186086A (ja) | 2004-12-27 | 2006-07-13 | Itoo:Kk | プリント基板のはんだ付け方法およびブリッジ防止用ガイド板 |
DE102005006333B4 (de) | 2005-02-10 | 2007-10-18 | Infineon Technologies Ag | Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben |
DE102005006995B4 (de) | 2005-02-15 | 2008-01-24 | Infineon Technologies Ag | Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben |
KR100630741B1 (ko) | 2005-03-04 | 2006-10-02 | 삼성전자주식회사 | 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법 |
US7939934B2 (en) | 2005-03-16 | 2011-05-10 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7371676B2 (en) | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
TWI284394B (en) | 2005-05-12 | 2007-07-21 | Advanced Semiconductor Eng | Lid used in package structure and the package structure of having the same |
JP2006324553A (ja) | 2005-05-20 | 2006-11-30 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7216794B2 (en) | 2005-06-09 | 2007-05-15 | Texas Instruments Incorporated | Bond capillary design for ribbon wire bonding |
CN100550367C (zh) | 2005-07-01 | 2009-10-14 | 皇家飞利浦电子股份有限公司 | 电子器件 |
US7476608B2 (en) | 2005-07-14 | 2009-01-13 | Hewlett-Packard Development Company, L.P. | Electrically connecting substrate with electrical device |
TWI263313B (en) | 2005-08-15 | 2006-10-01 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
US7675152B2 (en) | 2005-09-01 | 2010-03-09 | Texas Instruments Incorporated | Package-on-package semiconductor assembly |
US7504716B2 (en) | 2005-10-26 | 2009-03-17 | Texas Instruments Incorporated | Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking |
JP2007123595A (ja) | 2005-10-28 | 2007-05-17 | Nec Corp | 半導体装置及びその実装構造 |
US8183682B2 (en) | 2005-11-01 | 2012-05-22 | Nxp B.V. | Methods of packaging a semiconductor die and package formed by the methods |
JP4530975B2 (ja) | 2005-11-14 | 2010-08-25 | 株式会社新川 | ワイヤボンディング方法 |
JP2007142042A (ja) | 2005-11-16 | 2007-06-07 | Sharp Corp | 半導体パッケージとその製造方法,半導体モジュール,および電子機器 |
US7344917B2 (en) | 2005-11-30 | 2008-03-18 | Freescale Semiconductor, Inc. | Method for packaging a semiconductor device |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8067267B2 (en) * | 2005-12-23 | 2011-11-29 | Tessera, Inc. | Microelectronic assemblies having very fine pitch stacking |
US20070190747A1 (en) | 2006-01-23 | 2007-08-16 | Tessera Technologies Hungary Kft. | Wafer level packaging to lidded chips |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
JP2007234845A (ja) | 2006-03-01 | 2007-09-13 | Nec Corp | 半導体装置 |
US7759782B2 (en) | 2006-04-07 | 2010-07-20 | Tessera, Inc. | Substrate for a microelectronic package and method of fabricating thereof |
US7390700B2 (en) | 2006-04-07 | 2008-06-24 | Texas Instruments Incorporated | Packaged system of semiconductor chips having a semiconductor interposer |
JP5598787B2 (ja) | 2006-04-17 | 2014-10-01 | マイクロンメモリジャパン株式会社 | 積層型半導体装置の製造方法 |
US7242081B1 (en) | 2006-04-24 | 2007-07-10 | Advanced Semiconductor Engineering Inc. | Stacked package structure |
US7780064B2 (en) | 2006-06-02 | 2010-08-24 | Asm Technology Singapore Pte Ltd | Wire bonding method for forming low-loop profiles |
JP4961848B2 (ja) | 2006-06-12 | 2012-06-27 | 日本電気株式会社 | 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法 |
US7967062B2 (en) | 2006-06-16 | 2011-06-28 | International Business Machines Corporation | Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof |
US20070290325A1 (en) | 2006-06-16 | 2007-12-20 | Lite-On Semiconductor Corporation | Surface mounting structure and packaging method thereof |
WO2008014633A1 (en) | 2006-06-29 | 2008-02-07 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
KR100792352B1 (ko) | 2006-07-06 | 2008-01-08 | 삼성전기주식회사 | 패키지 온 패키지의 바텀기판 및 그 제조방법 |
KR100800478B1 (ko) | 2006-07-18 | 2008-02-04 | 삼성전자주식회사 | 적층형 반도체 패키지 및 그의 제조방법 |
US20080023805A1 (en) | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
JP5132101B2 (ja) * | 2006-07-27 | 2013-01-30 | 新光電気工業株式会社 | スタックパッケージ構造体及びその製造に用いる単体パッケージと、それらの製造方法 |
US8048479B2 (en) | 2006-08-01 | 2011-11-01 | Qimonda Ag | Method for placing material onto a target board by means of a transfer board |
JP2008039502A (ja) | 2006-08-03 | 2008-02-21 | Alps Electric Co Ltd | 接触子およびその製造方法 |
US7486525B2 (en) | 2006-08-04 | 2009-02-03 | International Business Machines Corporation | Temporary chip attach carrier |
US7425758B2 (en) | 2006-08-28 | 2008-09-16 | Micron Technology, Inc. | Metal core foldover package structures |
KR20080020069A (ko) | 2006-08-30 | 2008-03-05 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR100891516B1 (ko) | 2006-08-31 | 2009-04-06 | 주식회사 하이닉스반도체 | 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지 |
KR100770934B1 (ko) | 2006-09-26 | 2007-10-26 | 삼성전자주식회사 | 반도체 패키지와 그를 이용한 반도체 시스템 패키지 |
TWI336502B (en) | 2006-09-27 | 2011-01-21 | Advanced Semiconductor Eng | Semiconductor package and semiconductor device and the method of making the same |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
TWI312561B (en) | 2006-10-27 | 2009-07-21 | Advanced Semiconductor Eng | Structure of package on package and method for fabricating the same |
KR100817073B1 (ko) | 2006-11-03 | 2008-03-26 | 삼성전자주식회사 | 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지 |
US8193034B2 (en) | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
WO2008065896A1 (fr) | 2006-11-28 | 2008-06-05 | Kyushu Institute Of Technology | Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé |
US8598717B2 (en) | 2006-12-27 | 2013-12-03 | Spansion Llc | Semiconductor device and method for manufacturing the same |
JP2008166439A (ja) | 2006-12-27 | 2008-07-17 | Spansion Llc | 半導体装置およびその製造方法 |
KR100757345B1 (ko) | 2006-12-29 | 2007-09-10 | 삼성전자주식회사 | 플립 칩 패키지 및 그의 제조 방법 |
US20080156518A1 (en) | 2007-01-03 | 2008-07-03 | Tessera, Inc. | Alignment and cutting of microelectronic substrates |
TWI332702B (en) | 2007-01-09 | 2010-11-01 | Advanced Semiconductor Eng | Stackable semiconductor package and the method for making the same |
JP5347222B2 (ja) | 2007-01-10 | 2013-11-20 | 富士通株式会社 | 半導体装置の製造方法 |
US7719122B2 (en) | 2007-01-11 | 2010-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | System-in-package packaging for minimizing bond wire contamination and yield loss |
JP4823089B2 (ja) | 2007-01-31 | 2011-11-24 | 株式会社東芝 | 積層型半導体装置の製造方法 |
KR101057368B1 (ko) | 2007-01-31 | 2011-08-18 | 후지쯔 세미컨덕터 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
US8685792B2 (en) | 2007-03-03 | 2014-04-01 | Stats Chippac Ltd. | Integrated circuit package system with interposer |
WO2008108970A2 (en) | 2007-03-05 | 2008-09-12 | Tessera, Inc. | Chips having rear contacts connected by through vias to front contacts |
US7517733B2 (en) | 2007-03-22 | 2009-04-14 | Stats Chippac, Ltd. | Leadframe design for QFN package with top terminal leads |
CN101636830B (zh) | 2007-03-23 | 2012-07-11 | 三洋电机株式会社 | 半导体装置及其制造方法 |
JP4926787B2 (ja) | 2007-03-30 | 2012-05-09 | アオイ電子株式会社 | 半導体装置の製造方法 |
JPWO2008120755A1 (ja) | 2007-03-30 | 2010-07-15 | 日本電気株式会社 | 機能素子内蔵回路基板及びその製造方法、並びに電子機器 |
US7589394B2 (en) | 2007-04-10 | 2009-09-15 | Ibiden Co., Ltd. | Interposer |
JP5003260B2 (ja) | 2007-04-13 | 2012-08-15 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US7994622B2 (en) | 2007-04-16 | 2011-08-09 | Tessera, Inc. | Microelectronic packages having cavities for receiving microelectric elements |
KR20080094251A (ko) | 2007-04-19 | 2008-10-23 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 그 제조방법 |
JP5601751B2 (ja) | 2007-04-26 | 2014-10-08 | スパンション エルエルシー | 半導体装置 |
US20080284045A1 (en) | 2007-05-18 | 2008-11-20 | Texas Instruments Incorporated | Method for Fabricating Array-Molded Package-On-Package |
JP2008306128A (ja) | 2007-06-11 | 2008-12-18 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
KR100865125B1 (ko) | 2007-06-12 | 2008-10-24 | 삼성전기주식회사 | 반도체 패키지 및 그 제조방법 |
JP5179787B2 (ja) | 2007-06-22 | 2013-04-10 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US7944034B2 (en) | 2007-06-22 | 2011-05-17 | Texas Instruments Incorporated | Array molded package-on-package having redistribution lines |
US7911805B2 (en) | 2007-06-29 | 2011-03-22 | Tessera, Inc. | Multilayer wiring element having pin interface |
SG148901A1 (en) | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
KR20090007120A (ko) | 2007-07-13 | 2009-01-16 | 삼성전자주식회사 | 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법 |
US7781877B2 (en) | 2007-08-07 | 2010-08-24 | Micron Technology, Inc. | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
JP2009044110A (ja) | 2007-08-13 | 2009-02-26 | Elpida Memory Inc | 半導体装置及びその製造方法 |
SG150396A1 (en) | 2007-08-16 | 2009-03-30 | Micron Technology Inc | Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods |
KR101388538B1 (ko) | 2007-09-28 | 2014-04-23 | 테세라, 인코포레이티드 | 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리 |
JP2009088254A (ja) | 2007-09-28 | 2009-04-23 | Toshiba Corp | 電子部品パッケージ及び電子部品パッケージの製造方法 |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
KR20090033605A (ko) | 2007-10-01 | 2009-04-06 | 삼성전자주식회사 | 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치 |
US20090091009A1 (en) | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
US8008183B2 (en) | 2007-10-04 | 2011-08-30 | Texas Instruments Incorporated | Dual capillary IC wirebonding |
US7834464B2 (en) | 2007-10-09 | 2010-11-16 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
TWI389220B (zh) | 2007-10-22 | 2013-03-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US20090127686A1 (en) | 2007-11-21 | 2009-05-21 | Advanced Chip Engineering Technology Inc. | Stacking die package structure for semiconductor devices and method of the same |
KR100886100B1 (ko) | 2007-11-29 | 2009-02-27 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US7902644B2 (en) | 2007-12-07 | 2011-03-08 | Stats Chippac Ltd. | Integrated circuit package system for electromagnetic isolation |
US7964956B1 (en) | 2007-12-10 | 2011-06-21 | Oracle America, Inc. | Circuit packaging and connectivity |
US8390117B2 (en) | 2007-12-11 | 2013-03-05 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
JP2009158593A (ja) | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | バンプ構造およびその製造方法 |
US20090170241A1 (en) | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US8258015B2 (en) | 2008-02-22 | 2012-09-04 | Stats Chippac Ltd. | Integrated circuit package system with penetrable film adhesive |
JP5043743B2 (ja) | 2008-04-18 | 2012-10-10 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法 |
KR20090123680A (ko) | 2008-05-28 | 2009-12-02 | 주식회사 하이닉스반도체 | 적층 반도체 패키지 |
US8021907B2 (en) | 2008-06-09 | 2011-09-20 | Stats Chippac, Ltd. | Method and apparatus for thermally enhanced semiconductor package |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
US7859033B2 (en) | 2008-07-09 | 2010-12-28 | Eastman Kodak Company | Wafer level processing for backside illuminated sensors |
TWI372453B (en) | 2008-09-01 | 2012-09-11 | Advanced Semiconductor Eng | Copper bonding wire, wire bonding structure and method for processing and bonding a wire |
US8384203B2 (en) | 2008-07-18 | 2013-02-26 | United Test And Assembly Center Ltd. | Packaging structural member |
US8004093B2 (en) | 2008-08-01 | 2011-08-23 | Stats Chippac Ltd. | Integrated circuit package stacking system |
US20100044860A1 (en) | 2008-08-21 | 2010-02-25 | Tessera Interconnect Materials, Inc. | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer |
KR100997793B1 (ko) | 2008-09-01 | 2010-12-02 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
KR20100033012A (ko) | 2008-09-19 | 2010-03-29 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이를 갖는 적층 반도체 패키지 |
US7842541B1 (en) | 2008-09-24 | 2010-11-30 | Amkor Technology, Inc. | Ultra thin package and fabrication method |
US8063475B2 (en) | 2008-09-26 | 2011-11-22 | Stats Chippac Ltd. | Semiconductor package system with through silicon via interposer |
JP5185062B2 (ja) | 2008-10-21 | 2013-04-17 | パナソニック株式会社 | 積層型半導体装置及び電子機器 |
MY149251A (en) | 2008-10-23 | 2013-07-31 | Carsem M Sdn Bhd | Wafer-level package using stud bump coated with solder |
KR101461630B1 (ko) | 2008-11-06 | 2014-11-20 | 삼성전자주식회사 | 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법 |
TW201023308A (en) | 2008-12-01 | 2010-06-16 | Advanced Semiconductor Eng | Package-on-package device, semiconductor package and method for manufacturing the same |
KR101011863B1 (ko) | 2008-12-02 | 2011-01-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US7642128B1 (en) | 2008-12-12 | 2010-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US8012797B2 (en) | 2009-01-07 | 2011-09-06 | Advanced Semiconductor Engineering, Inc. | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries |
JP2010199528A (ja) | 2009-01-27 | 2010-09-09 | Tatsuta System Electronics Kk | ボンディングワイヤ |
JP2010177597A (ja) | 2009-01-30 | 2010-08-12 | Sanyo Electric Co Ltd | 半導体モジュールおよび携帯機器 |
US9142586B2 (en) | 2009-02-24 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for backside illuminated image sensor |
JP2010206007A (ja) | 2009-03-04 | 2010-09-16 | Nec Corp | 半導体装置及びその製造方法 |
JPWO2010101163A1 (ja) | 2009-03-04 | 2012-09-10 | 日本電気株式会社 | 機能素子内蔵基板及びそれを用いた電子デバイス |
US8106498B2 (en) * | 2009-03-05 | 2012-01-31 | Stats Chippac Ltd. | Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof |
US8258010B2 (en) | 2009-03-17 | 2012-09-04 | Stats Chippac, Ltd. | Making a semiconductor device having conductive through organic vias |
US20100244276A1 (en) | 2009-03-25 | 2010-09-30 | Lsi Corporation | Three-dimensional electronics package |
US8194411B2 (en) | 2009-03-31 | 2012-06-05 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Electronic package with stacked modules with channels passing through metal layers of the modules |
US20100289142A1 (en) | 2009-05-15 | 2010-11-18 | Il Kwon Shim | Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof |
US8020290B2 (en) | 2009-06-14 | 2011-09-20 | Jayna Sheats | Processes for IC fabrication |
TWI379367B (en) | 2009-06-15 | 2012-12-11 | Kun Yuan Technology Co Ltd | Chip packaging method and structure thereof |
US20100327419A1 (en) | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
JP5214554B2 (ja) | 2009-07-30 | 2013-06-19 | ラピスセミコンダクタ株式会社 | 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法 |
US7923304B2 (en) | 2009-09-10 | 2011-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system with conductive pillars and method of manufacture thereof |
US8264091B2 (en) | 2009-09-21 | 2012-09-11 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulated via and method of manufacture thereof |
US8390108B2 (en) | 2009-12-16 | 2013-03-05 | Stats Chippac Ltd. | Integrated circuit packaging system with stacking interconnect and method of manufacture thereof |
US8169065B2 (en) | 2009-12-22 | 2012-05-01 | Epic Technologies, Inc. | Stackable circuit structures and methods of fabrication thereof |
TWI392066B (zh) | 2009-12-28 | 2013-04-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
US9496152B2 (en) | 2010-03-12 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Carrier system with multi-tier conductive posts and method of manufacture thereof |
US7928552B1 (en) | 2010-03-12 | 2011-04-19 | Stats Chippac Ltd. | Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof |
KR101667656B1 (ko) | 2010-03-24 | 2016-10-20 | 삼성전자주식회사 | 패키지-온-패키지 형성방법 |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8564141B2 (en) | 2010-05-06 | 2013-10-22 | SK Hynix Inc. | Chip unit and stack package having the same |
US8217502B2 (en) | 2010-06-08 | 2012-07-10 | Stats Chippac Ltd. | Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
KR20120007839A (ko) | 2010-07-15 | 2012-01-25 | 삼성전자주식회사 | 적층형 반도체 패키지의 제조방법 |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
KR101683814B1 (ko) | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8304900B2 (en) | 2010-08-11 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked lead and method of manufacture thereof |
US8518746B2 (en) | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
US20120063090A1 (en) | 2010-09-09 | 2012-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling mechanism for stacked die package and method of manufacturing the same |
US8409922B2 (en) | 2010-09-14 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect |
US20120080787A1 (en) | 2010-10-05 | 2012-04-05 | Qualcomm Incorporated | Electronic Package and Method of Making an Electronic Package |
US8618646B2 (en) | 2010-10-12 | 2013-12-31 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US8697492B2 (en) | 2010-11-02 | 2014-04-15 | Tessera, Inc. | No flow underfill |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US8502387B2 (en) | 2010-12-09 | 2013-08-06 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US20120184116A1 (en) | 2011-01-18 | 2012-07-19 | Tyco Electronics Corporation | Interposer |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8476115B2 (en) | 2011-05-03 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material |
US8487421B2 (en) | 2011-08-01 | 2013-07-16 | Tessera, Inc. | Microelectronic package with stacked microelectronic elements and method for manufacture thereof |
US20130037929A1 (en) | 2011-08-09 | 2013-02-14 | Kay S. Essig | Stackable wafer level packages and related methods |
KR101800440B1 (ko) | 2011-08-31 | 2017-11-23 | 삼성전자주식회사 | 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법 |
US9177832B2 (en) | 2011-09-16 | 2015-11-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect |
US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9105552B2 (en) | 2011-10-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8912651B2 (en) | 2011-11-30 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) structure including stud bulbs and method |
US8680684B2 (en) | 2012-01-09 | 2014-03-25 | Invensas Corporation | Stackable microelectronic package structures |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9082763B2 (en) | 2012-03-15 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Joint structure for substrates and methods of forming |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9171790B2 (en) | 2012-05-30 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8828860B2 (en) | 2012-08-30 | 2014-09-09 | International Business Machines Corporation | Double solder bumps on substrates for low temperature flip chip bonding |
KR101419597B1 (ko) | 2012-11-06 | 2014-07-14 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
-
2010
- 2010-07-19 US US12/839,038 patent/US9159708B2/en active Active
-
2011
- 2011-07-18 KR KR1020137003922A patent/KR101734882B1/ko active IP Right Grant
- 2011-07-18 EP EP11741499.5A patent/EP2596530A2/en not_active Withdrawn
- 2011-07-18 KR KR1020177012160A patent/KR101895019B1/ko active IP Right Grant
- 2011-07-18 JP JP2013520776A patent/JP6027966B2/ja active Active
- 2011-07-18 WO PCT/US2011/044342 patent/WO2012012321A2/en active Application Filing
- 2011-07-18 CN CN201180043268.8A patent/CN103201836B/zh active Active
- 2011-07-18 CN CN201610583981.6A patent/CN106129041B/zh active Active
- 2011-07-19 TW TW100125522A patent/TWI460845B/zh active
-
2015
- 2015-10-08 US US14/878,548 patent/US9553076B2/en active Active
-
2016
- 2016-10-14 JP JP2016202866A patent/JP2017038075A/ja active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004172157A (ja) * | 2002-11-15 | 2004-06-17 | Shinko Electric Ind Co Ltd | 半導体パッケージおよびパッケージスタック半導体装置 |
JP2004319892A (ja) * | 2003-04-18 | 2004-11-11 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2006344917A (ja) * | 2005-06-10 | 2006-12-21 | Sharp Corp | 半導体装置、積層型半導体装置、および半導体装置の製造方法 |
JP2009508324A (ja) * | 2005-08-19 | 2009-02-26 | マイクロン テクノロジー, インク. | マイクロ電子デバイス、積み重ねられたマイクロ電子デバイス、およびマイクロ電子デバイスを製造する方法 |
JP2009506553A (ja) * | 2005-08-31 | 2009-02-12 | マイクロン テクノロジー, インク. | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
JP2007208159A (ja) * | 2006-02-06 | 2007-08-16 | Hitachi Ltd | 半導体装置 |
US20090206461A1 (en) * | 2008-02-15 | 2009-08-20 | Qimonda Ag | Integrated circuit and method |
US20090236753A1 (en) * | 2008-03-21 | 2009-09-24 | Moon Dongsoo | Integrated circuit package system for stackable devices |
US20100032822A1 (en) * | 2008-08-07 | 2010-02-11 | Advanced Semiconductor Engineering, Inc. | Chip package structure |
WO2010041630A1 (ja) * | 2008-10-10 | 2010-04-15 | 日本電気株式会社 | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20170051546A (ko) | 2017-05-11 |
KR101895019B1 (ko) | 2018-09-04 |
JP6027966B2 (ja) | 2016-11-16 |
JP2017038075A (ja) | 2017-02-16 |
EP2596530A2 (en) | 2013-05-29 |
CN106129041A (zh) | 2016-11-16 |
US20120013001A1 (en) | 2012-01-19 |
CN103201836A (zh) | 2013-07-10 |
US20160086922A1 (en) | 2016-03-24 |
TWI460845B (zh) | 2014-11-11 |
US9159708B2 (en) | 2015-10-13 |
CN103201836B (zh) | 2016-08-17 |
TW201209991A (en) | 2012-03-01 |
KR20130086347A (ko) | 2013-08-01 |
US9553076B2 (en) | 2017-01-24 |
CN106129041B (zh) | 2024-03-12 |
WO2012012321A2 (en) | 2012-01-26 |
WO2012012321A3 (en) | 2012-06-21 |
KR101734882B1 (ko) | 2017-05-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6027966B2 (ja) | エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ | |
KR100800478B1 (ko) | 적층형 반도체 패키지 및 그의 제조방법 | |
JP5598787B2 (ja) | 積層型半導体装置の製造方法 | |
US6876074B2 (en) | Stack package using flexible double wiring substrate | |
US8030135B2 (en) | Methods for a multiple die integrated circuit package | |
US7514297B2 (en) | Methods for a multiple die integrated circuit package | |
KR100711675B1 (ko) | 반도체 장치 및 그 제조 방법 | |
TWI426586B (zh) | 具有用於將焊墊鍍於晶片下方之導線的球柵陣列封裝 | |
KR101245454B1 (ko) | 비대칭적으로 배열된 다이 및 몰딩을 포함하는 멀티패키지 모듈 | |
TWI353046B (en) | Land grid array semiconductor device packages, ass | |
JP4704800B2 (ja) | 積層型半導体装置及びその製造方法 | |
US7364784B2 (en) | Thin semiconductor package having stackable lead frame and method of manufacturing the same | |
US9324681B2 (en) | Pin attachment | |
JP3781998B2 (ja) | 積層型半導体装置の製造方法 | |
US8975738B2 (en) | Structure for microelectronic packaging with terminals on dielectric mass | |
WO2007053606A2 (en) | Multiple die integrated circuit package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140718 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140718 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150421 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150423 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150721 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150821 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150924 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160308 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20160608 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160808 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160916 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161017 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6027966 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |