JP4334996B2 - 多層配線板用基材、両面配線板およびそれらの製造方法 - Google Patents
多層配線板用基材、両面配線板およびそれらの製造方法 Download PDFInfo
- Publication number
- JP4334996B2 JP4334996B2 JP2003426392A JP2003426392A JP4334996B2 JP 4334996 B2 JP4334996 B2 JP 4334996B2 JP 2003426392 A JP2003426392 A JP 2003426392A JP 2003426392 A JP2003426392 A JP 2003426392A JP 4334996 B2 JP4334996 B2 JP 4334996B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- layer
- insulating layer
- insulating
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
11 金属板(第1の金属層)
12 バンプ
13 マスキング
16 樹脂前駆体
17 絶縁接着層
18 金属板(第2の金属層)
20 両面配線板
21、22 導体回路
30 多層配線板用基材
31 樹脂前駆体
32 下地層
33 可塑性ポリイミド前駆体
34 表層
35 絶縁接着層
50 両面配線板
Claims (4)
- 片面に層間導通用のバンプが形成された銅層のバンプ形成面に、エポキシ樹脂前駆体をバンプ頂部を除く領域に塗布した後、加熱硬化して第1の絶縁層を形成し、前記第1の絶縁層上に接着性を有する熱可塑性ポリイミド前駆体を塗布して第2の絶縁層を形成し、前記銅層のバンプ形成面に前記バンプの頂部が露出または突出し、前記第1の絶縁層と前記第2の絶縁層とからなる絶縁接着層を備えることを特徴とする多層配線板用基材。
- 片面に層間導通用のバンプ、および、エポキシ樹脂前駆体をバンプ頂部を除く領域に塗布した後、加熱硬化して第1の絶縁層を形成し、前記第1の絶縁層上に接着性を有する熱可塑性ポリイミド前駆体を塗布して第2の絶縁層を形成し、前記バンプの形成面に前記バンプの頂部が露出または突出し、前記第1の絶縁層と前記第2の絶縁層とからなる絶縁接着層が形成された第1の銅層と、
前記絶縁接着層で貼り合わされて前記バンプにより前記第1の銅層と層間導通された第2の銅層と、
を備えることを特徴とする両面配線板。 - 銅層の片面に層間導通用のバンプを形成する工程と、
前記銅層のバンプ形成面に、前記バンプの配置パターンを遮蔽するマスキングを位置決めする工程と、
前記マスキングを通して前記銅層のバンプ形成面にエポキシ樹脂前駆体を塗布した後、加熱硬化して第1の絶縁層を形成し、前記第1の絶縁層上に接着性を有する熱可塑性ポリイミド前駆体を塗布して第2の絶縁層を形成し、前記銅層のバンプ形成面に前記バンプの頂部が露出または突出し、前記第1の絶縁層と前記第2の絶縁層とからなる絶縁接着層を形成する工程と、
を備えることを特徴とする多層配線板用基材の製造方法。 - 第1の銅層の片面に層間導通用のバンプを形成する工程と、
前記第1の銅層のバンプ形成面に、前記バンプの配置パターンを遮蔽するマスキングを位置決めする工程と、
前記マスキングを通して前記第1の銅層のバンプ形成面にエポキシ樹脂前駆体を塗布した後、加熱硬化して第1の絶縁層を形成し、前記第1の絶縁層上に接着性を有する熱可塑性ポリイミド前駆体を塗布して第2の絶縁層を形成し、前記第1の銅層のバンプ形成面に前記バンプの頂部が露出または突出し、前記第1の絶縁層と前記第2の絶縁層とからなる絶縁接着層を形成する工程と、
第2の銅層を前記バンプにより前記第1の銅層と層間導通を保って前記絶縁接着層で貼り合わせる工程と、
を備えることを特徴とする両面配線板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003426392A JP4334996B2 (ja) | 2003-12-24 | 2003-12-24 | 多層配線板用基材、両面配線板およびそれらの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003426392A JP4334996B2 (ja) | 2003-12-24 | 2003-12-24 | 多層配線板用基材、両面配線板およびそれらの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005183880A JP2005183880A (ja) | 2005-07-07 |
JP4334996B2 true JP4334996B2 (ja) | 2009-09-30 |
Family
ID=34785947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003426392A Expired - Fee Related JP4334996B2 (ja) | 2003-12-24 | 2003-12-24 | 多層配線板用基材、両面配線板およびそれらの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4334996B2 (ja) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101053079A (zh) | 2004-11-03 | 2007-10-10 | 德塞拉股份有限公司 | 堆叠式封装的改进 |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
CN109936919A (zh) * | 2019-03-05 | 2019-06-25 | 惠州市特创电子科技有限公司 | 一种通过导电膏导通的高频传输线路板及其制备方法 |
JPWO2022064933A1 (ja) | 2020-09-24 | 2022-03-31 |
-
2003
- 2003-12-24 JP JP2003426392A patent/JP4334996B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005183880A (ja) | 2005-07-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4334996B2 (ja) | 多層配線板用基材、両面配線板およびそれらの製造方法 | |
TWI386140B (zh) | Flexible multilayer circuit board | |
US7229293B2 (en) | Connecting structure of circuit board and method for manufacturing the same | |
JP2002064271A (ja) | 複合配線基板及びその製造方法 | |
JP2003347748A (ja) | 多層配線基板及びその製造方法。 | |
KR20080064872A (ko) | 적층 회로 기판의 제조 방법, 회로판 및 그 제조 방법 | |
JP2007110010A (ja) | フレキシブルプリント配線板、フレキシブルプリント回路板、およびそれらの製造方法 | |
WO2002007485A1 (en) | Circuit board and method for manufacturing the same, and electronic apparatus comprising it | |
JP6414652B1 (ja) | 多層基板および電子機器 | |
US8161634B2 (en) | Method of fabricating a printed circuit board | |
JP2005243899A (ja) | プリント配線板及びその製造方法 | |
KR101204083B1 (ko) | 전기소자 내장 다층 연성 인쇄회로기판 및 그 제조 방법 | |
JP2007158069A (ja) | 半導体パッケージの外部接続構造及びその製造方法 | |
KR100699237B1 (ko) | 임베디드 인쇄회로기판 제조방법 | |
JP2004104045A (ja) | 多層回路配線基板 | |
JP2010278379A (ja) | 配線基板およびその製造方法 | |
JP2001015868A (ja) | 回路基板、パッケージ及びリードフレームとその製造方法 | |
JP2006100703A (ja) | リジッド−フレキシブル基板及びその製造方法 | |
WO2019198241A1 (ja) | 部品内蔵基板の製造方法及び部品内蔵基板 | |
JP2889516B2 (ja) | 多層配線基板の製造方法 | |
JP3509315B2 (ja) | 回路基板の製造方法 | |
US20230063719A1 (en) | Method for manufacturing wiring substrate | |
JP2000133943A (ja) | 多層基板の製造方法 | |
KR101044133B1 (ko) | 인쇄회로기판 제조용 캐리어와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법 | |
JP2005183490A (ja) | 多層配線板用基材、両面配線板およびそれらの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Effective date: 20060614 Free format text: JAPANESE INTERMEDIATE CODE: A621 |
|
A711 | Notification of change in applicant |
Effective date: 20070206 Free format text: JAPANESE INTERMEDIATE CODE: A711 |
|
A131 | Notification of reasons for refusal |
Effective date: 20080701 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
A521 | Written amendment |
Effective date: 20080926 Free format text: JAPANESE INTERMEDIATE CODE: A523 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081031 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20081031 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20081031 |
|
A131 | Notification of reasons for refusal |
Effective date: 20090106 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090225 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090526 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Effective date: 20090624 Free format text: JAPANESE INTERMEDIATE CODE: A61 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120703 Year of fee payment: 3 |
|
R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |