US20080284045A1 - Method for Fabricating Array-Molded Package-On-Package - Google Patents

Method for Fabricating Array-Molded Package-On-Package Download PDF

Info

Publication number
US20080284045A1
US20080284045A1 US11750757 US75075707A US2008284045A1 US 20080284045 A1 US20080284045 A1 US 20080284045A1 US 11750757 US11750757 US 11750757 US 75075707 A US75075707 A US 75075707A US 2008284045 A1 US2008284045 A1 US 2008284045A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
surface
mold
pad
substrate
method according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11750757
Inventor
Mark A. Gerber
David N. Walter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

A method and apparatus for fabricating a semiconductor device are disclosed. The method attaches semiconductor chips (130) on a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias and with contact pads (103) in pad locations. A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold cavity. The substrate and the chip are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface. After pressuring encapsulation compound into the cavity, the mold is opened; the encapsulated device has apertures to the pad locations. Any residual compound formed on the pads is removed by laser, plasma, or chemical to expose the metal surface.

Description

    FIELD OF THE INVENTION
  • The present invention is related in general to the field of semiconductor devices and processes and more specifically to the structure and fabrication method of low-profile, vertically integrated package-on-package integrated circuit assemblies.
  • DESCRIPTION OF THE RELATED ART
  • The thickness of today's semiconductor package-on-package products is the sum of the thicknesses of the semiconductor chips, electric interconnections, and encapsulations, which are used in the individual devices constituting the building-blocks of the products. This simple approach, however, is no longer acceptable for the recent applications especially for hand-held wireless equipments, since these applications place new, stringent constraints on the size and volume of semiconductor components used for these applications.
  • Furthermore, while the market place renewed a push to shrink semiconductor devices both in two and in three dimensions, the miniaturization effort included packaging strategies for thinner semiconductor devices as well as electronic systems. This trend to reduce product thickness initiated an increasing tendency to have product warpage problems, especially in thin assemblies, caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the plastic substrates, the molding compound, the solder balls, and the printed circuit board. For instance, with silicon as the semiconductor material and plastic FR-4 as substrate material, the difference in CTE is about an order of magnitude. Warpage is aggravated by repeated temperature cycles and solder reflows. Warpage can lead to some of the most debilitating problems encountered by semiconductor assemblies such as the fracture and separation of solder joints, or the separation of materials followed by moisture ingress.
  • SUMMARY OF THE INVENTION
  • Applicants recognize an existing need to shrink semiconductor devices both in two and in three dimensions, especially for a device-stacking and package-on-package method for semiconductor devices as well as electronic systems. Specifically, applicants recognize an existing need to design production equipment such as molds, to fabricate devices directly usable for assembling package-on-package the products.
  • The invention solves the problem by constructing one mold portion with contours so that the molded device will offer direct coupling with another device to form a package-on-package product. In addition, the new fabrication method is low-cost and simplified, and the products provide improved testability and thus yield. Using these contoured molds, stacking chips and packages will shorten the time-to-market of innovative products such as vertically integrated semiconductor systems, which utilize available chips of various capabilities (for example processors and memory chips), eliminating the wait for a redesign of chips.
  • Based on the contoured mold equipment, package-on-package devices can be produced with excellent electrical performance, mechanical stability free of warping, and high product reliability. Further, it is a technical advantage that the fabrication method is flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations.
  • One embodiment of the invention is a method for fabricating a semiconductor device. A semiconductor chip is assembled on a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and conductive vias and contact pads in pad locations. A mold is provided, which has a top portion with metal protrusions at locations matching the pad locations; the protrusions are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold cavity. The bottom mold portion is featureless. The substrate with the chip is loaded onto the bottom mold portion; the mold is closed by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface. A cavity is thus formed by the top portion. After pressuring encapsulation compound into the cavity, the mold is opened. The encapsulation of the molded device has apertures to the pad locations. Finally, any residual compound formed on the pads is removed to expose the metal surface.
  • The protrusions approach the pad metal surface in the closed cavity to a distance between 0 and 100 μm. The compound formed in that distance can be removed either by shining laser light into the compound apertures, depositing compound particles on the sidewalls; or by a plasma clean-up process, leaving a roughened surface on the aperture sidewalls; or by a chemical etch process, leaving a compound undercut next to the pad metal surface.
  • The mold apertures may be filled with solder material contacting the pad metal surface, or they may serve to attach another semiconductor device with solder bodies, creating a package-on-package semiconductor assembly.
  • Another embodiment of the invention is a mold with top and bottom portions forming a cavity for holding semiconductor devices, wherein the device includes a semiconductor chip assembled on a sheet-like insulating substrate having contact pads in pad locations and with a metal surface. The mold is operable to be closed by clamping the top portion onto the bottom portion. The top portion includes metal protrusions at locations matching the pad locations; the protrusions are shaped as truncated cones of a height suitable to approach the pad metal surface in the closed cavity. The cones are angled with a range of about 10 to 30 degrees from vertical. Furthermore, the protrusions may optionally include a ridge operable to create a gas release channel in the aperture of the contact pads.
  • Another embodiment of the invention is a semiconductor device including a sheet-like insulating substrate with a perimeter, a first (top) surface with a chip assembly site and contact pads in pad locations and with a metal surface, and a second (bottom) surface. A semiconductor chip is assembled (by wire bonding or by flip-chip) on the assembly site. An encapsulated region, located only on the top substrate and extending to the substrate perimeter, encloses the chip in compound and has contact apertures at the pad locations for permitting external communication with the metal surfaces; the apertures may include sidewall surfaces with compound structures modified from its smooth-molded character by a metal clean-up process.
  • The compound structures on the aperture sidewalls may include thermally modified compound particles indicative of a laser process used for exposing the pad metal. Alternatively, the aperture sidewalls may have a roughened surface indicative of a plasma clean-up process used for exposing the pad metal. Or alternatively, the aperture sidewalls have indications of a chemical etch process used for exposing the pad metal.
  • The device further may have elongated grooves in the contact apertures operable as gas release channels. Solder material may be in the apertures, contacting the pad metal surface. Alternatively, another semiconductor device with solder balls can be attached to the first substrate surface by contacting the pad surfaces with the solder balls and thus creating a package-on-package semiconductor assembly. In addition, solder bodies may be attached to the second substrate surface.
  • The technical advances represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 7 illustrate certain process steps for fabricating an array-molded semiconductor device according to an embodiment of the invention.
  • FIG. 1A is a schematic cross section of a substrate with contact pads and a semiconductor chip assembled by wire bonding.
  • FIG. 1B is a schematic cross section of a substrate with contact pads and a semiconductor chip assembled by flip-chip technology.
  • FIG. 1C is a schematic cross section of a sheet-like substrate with contact pads and a plurality of chips flip-assembled for array processing.
  • FIG. 2A shows a schematic cross section of the top portion of a mold with structural features according to the invention.
  • FIG. 2B shows a schematic cross section of the top portion of a mold intended for array-molding with structural features according to the invention.
  • FIG. 3A shows a schematic cross section of the bottom portion of a mold.
  • FIG. 3B shows a schematic cross section of the bottom portion of a mold intended for array-molding.
  • FIG. 4 illustrates a schematic cross section of the open mold according to an embodiment of the invention, loaded with a substrate assembled with semiconductor devices.
  • FIG. 5 shows a schematic cross section of the closed mold according to an embodiment of the invention, loaded with a substrate assembled with semiconductor devices.
  • FIG. 6A illustrates a schematic cross section of a molded semiconductor array after removal from the mold.
  • FIG. 6B shows a magnified schematic cross section of a molded unit after removal from the mold and singulation from the array.
  • FIG. 7 is a schematic cross section of a discrete device after removing any molding compound from the contact pads, filling an aperture with solder, and attaching solder bodies for external communication.
  • FIG. 8A shows a schematic cross section of a finished array with features according to the invention.
  • FIG. 8B depicts a schematic top view of a finished array, molded according to the invention, before singulation.
  • FIG. 8C shows a schematic perspective view of a discrete unit singulated from the molded array with features according to the invention.
  • FIG. 9 illustrates a schematic cross section of another embodiment of the invention, wherein a second semiconductor device with solder bodies is attached to the first device so that the aperture-exposed pads of the first device are contacted by the solder bodies of the second device, creating a package-on-package semiconductor assembly.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIGS. 1A through 7 illustrate schematically the steps of one embodiment of the present invention, a method for array-molding semiconductor devices. The steps shown in FIGS. 1A and 1B show the assembly of a semiconductor chip on a substrate by wire bonding (FIG. 1A) and by flip-chip technology (FIG. 1B); FIG. 1C exemplifies a portion of an array of chips assembled by flip-chip. A sheet-like substrate 101 with insulating core (for example, plastic, glass-fiber reinforced, ceramic) is integral with two or more patterned layers of conductive lines and conductive vias (preferably copper) and contact pads in pad locations. Lines 110 do not reach beyond the boundaries of substrate 101. Substrate 101 has a first surface 101 a and a second surface 101 b, and a preferred thickness range from 0.2 to 0.5 mm. The first surface 101 a includes chip assembly sites 102 and contact pads 103 in pad locations. The metal of the contact pads is preferably copper with a solderable surface (for example, including a layer of gold or palladium). Second surface 101 b also has pads 112 with a solderable surface.
  • A plurality of semiconductor chips 130 is provided. In order to attach and electrically connect the chips, they are assembled on each assembly site either by adhesive attachment and wire bonding, or by flip-chip connection. For flip-attachment, the connecting metal bumps 140 may be made of solder, gold, or copper.
  • As illustrated in FIG. 2A to 3B, in the next process step a mold made of steel or another suitable material is provided, which allows the encapsulation of a single unit or an array of units. The mold has a top portion manufactured to include recesses suitable for a cavity, and a bottom portion; when closed, the mold is forming a cavity for holding semiconductor devices. In FIG. 2A, the top portion is intended to process a single unit and is designated 201; in FIG. 2B, the top portion is constructed for an array of units to be processed together as a batch. In FIG. 3A, the bottom portion is intended to process a single unit and is designated 301; in FIG. 2B, the bottom portion is constructed for an array of units to be processed together.
  • The top portion 201 includes protrusions 202 at locations matching the pad locations of the device shown in FIGS. 1A and 1B; the bottom portion 301 is without corresponding protrusions. The protrusions are preferably shaped as truncated cones, with the cone surface angled within a preferred range from about 10 to 30 degrees from vertical. The angle is designated 202 a in FIG. 2A. Furthermore, the protrusions preferably may have a ridge 203, which may extend along the whole angled side of the cone. Ridge 203 is operable to create a groove or channel in the molded part, which may provide release of gas in the solder ball attachment process, or help in the solder paste reflow process.
  • The height 202 b of the protrusion is selected to be suitable to approach the substrate pad metal (103 in FIGS. 1A and 1B) in the closed mold. Preferably, the protrusion should approach the pad metal surface in the closed mold to a distance between 0 and about 100 μm. More preferably, height 202 b of the protrusion is sufficient to touch the pad metal surface in the closed mold.
  • The bottom portion 301 in FIGS. 3A and 310 in FIG. 3B of the mold has no protrusions; it is featureless and preferably flat. For some individual devices, it may be an advantage to recess a portion outlined by length 302 and depth 303 sufficient to accommodate the substrate of a discrete device, but for array processing, a featureless flat bottom mold portion is preferable.
  • In the next process step (see FIG. 4), the substrate 101 with the assembled chips 130 is loaded onto the bottom mold portion 310. The second substrate surface 101 b is rested on mold portion 310, and the first substrate surface 101 a with the contact pads 103 is positioned away from the bottom mold portion 310. Protrusions 202 of the top mold portion 210 are aligned with the respective contact pads 103 of substrate 101.
  • FIG. 5 shows the next process step of closing the mold by clamping the top portion 210 onto the bottom portion 310 so that the protrusions 202 are aligned with the contact pads 103, approaching or touching the pad surface. The top portion 210 resting on the flat bottom portion 310 forms the cavity of the mold for holding the semiconductor devices. Preferably, the protrusions touch the contact pads; however, material or alignment tolerances may cause a residual distance between 0 and about 100 μm between the protrusion and the pad. FIG. 5 also shows the respective ridge 203 for each protrusion 202.
  • In order to avoid any residual distance between protrusions and pads, causing a gap between protrusions and pads, and thus to avoid any bleeding of mold compound into the gap, an alternative method includes the step of placing a thin sheet 220 of compliant, inert polymer over the surface 201 a of the complete top mold portion (see FIG. 2A) The polymer is selected to tolerate significant pressure from the protrusions clamped against the pads. The sheet may have a chemical composition to be either dissolved into the molding compound and become part of the molded encapsulation, or, preferably, remain a coherent sheet which can be readily peeled off the top mold portion, after the mold is opened again.
  • Next, encapsulation material such as epoxy-based and filler-loaded molding compound is pressured into the cavity to fill the cavity; the runners for supplying the compound, and the gates needed for entering the cavity and controlling the compound flow, are not shown in FIG. 5. By this transfer molding step, encapsulations for the devices of the array are created.
  • After partially polymerizing the compound 601, the mold is opened and the substrate together with the encapsulated array of chips is removed from the mold; FIG. 6A illustrates the encapsulated array, and FIG. 6B shows an enlarged view of one unit. Subsequently, compound 601 is fully polymerized. For many device types, the thickness of the molded encapsulation is between 0.6 and 0.7 mm. FIGS. 6A and 6B show that the encapsulation has apertures 603 to the pad locations.
  • FIG. 6B indicates by dashed contour 602 any residual encapsulation that may form on the contact pads 103. These thin deposits (thickness 602 a between 0 and about 100 μm), if formed, have to be removed to expose the clean metal surface of pad 103. At least three methods are suitable to remove these unwanted encapsulation layers.
  • The first method employs drilling or vaporizing by laser light. A focused laser beam shines into the encapsulation aperture 603, removes the compound layer thereby forming particles 604 in a thermal process, and may deposit these particles on the otherwise smooth sidewalls 603 a; particles 604 attest to the thermal process used to clean up the pads. The second method employs a plasma clean-up process; the plasma leaves a roughened surface 605 on the aperture sidewalls 603 a. The third method employs a chemical etch process, which leaves a surface structure 606 recognizable by one skilled in the art. All three methods are material-sensitive and thus controllable to stop at the metal surface of the contact pads.
  • When the compliant inert film is employed, which can be peeled off after the molding process (see above), the pad metal surfaces remain clean throughout the molding process and consequently no clean-up step is necessary.
  • In an additional process step, reflow bodies such as solder balls 701 are attached to the attachment pads 112 (see FIGS. 1A and 1B) on the second substrate surface 101 b. This step is illustrated in FIG. 7, showing a magnified portion of the array (it should be noted that in the example of FIG. 7, wire bonding has been employed to assemble the chip on the first substrate surface 101 a).
  • In an optional process step, the mold apertures 703 may be filled with solder paste 704, which contacts the surface of pad metal 103. During the reflow step of the paste, grooves 705 may help to separate the flux-rich part form the solder-rich part.
  • FIGS. 8A, 8B, and 8C depict the singulation step. The dashed lines 801 (in the cross section of FIG. 8A), 802 and 803 (in the top view of FIG. 8B) indicate saw lines of saws, which cut through the mold compound 601 and the substrate 101 to singulate discrete units from the sheet-like substrate of the array. Due to the sawing process step, the individual units have recognizable saw marks on their sides.
  • A discrete unit is illustrated in FIG. 8C in an X-ray view, which emphasizes the apertures 703 to the contact pads, but omits the encapsulated assembled chip for clarity reasons (not to scale). In addition, the gas release channels 810 have been omitted for all apertures except for one row of apertures.
  • The gas release channels help to prevent the trapping of air and gas, when another device 902 with solder bodies 910 is attached to the first device 901 and the apertures are filled with solder to contact the exposed surfaces of the contact pads 103. FIG. 9 illustrates a resulting package-on-package semiconductor assembly.
  • Another embodiment of the invention is an apparatus for the fabrication of a semiconductor device; the apparatus is illustrated in FIGS. 2B and 3B. A mold has top (201 in FIG. 2A, 210 in FIG. 2B) and bottom (301 in FIG. 3A, 310 in FIG. 3B) portions; the top portion has a cavity with protrusions for holding semiconductor devices, the bottom portion is without corresponding protrusions and preferably featureless. Preferably, the device includes a semiconductor chip attached to a sheet-like insulating substrate with contact pads in pad locations. When the mold is operated, it is closed by clamping the top portion onto the bottom portion, whereby a cavity is formed.
  • The top portion includes protrusions (202 in FIG. 2A) at locations matching the pad locations. Preferably, the protrusions are made of the same material (for instance, steel) as the top portion of the mold. The protrusions are preferably shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold; a practical distance from the cone to the pad surface is between 0 and about 100 μm. More preferably, the height is suitable to touch the pads metal surface in the closed mold. The angle 202 a of the cones is preferably between 10 and 30 degrees from vertical. In addition, it is advantageous to add a ridge to the protrusions (203 in FIG. 2A), which are configured to create, in the molded encapsulation, a gas release channel in the aperture of the contact pads. The release channel provides an escape for air and other gases in the solder attachment process, when the aperture is being filled with solder.
  • The bottom portion of the mold is preferably featureless, in particular in molds for encapsulating whole arrays as shown in FIG. 3B. The bottom part provides support for placing the device substrate in the mold. On the other hand, it may be advantageous for molding discrete devices to have a recess (302 in FIG. 3A) of a certain depth in the bottom part for tightly positioning the device substrate. No molding compound reaches the bottom of the cavity or the bottom surface of the substrate.
  • Another embodiment of the invention is a semiconductor device, singulated by sawing from an array-molded substrate, and designed to become part of a semiconductor package-on-package device. An example of the embodiment is illustrated in FIG. 8C; a magnified cross section before singulation is depicted in FIG. 7. A sheet-like insulating substrate 101 has obtained its perimeter 820, preferably by sawing, which leaves recognizable saw marks. The substrate has a first surface 101 a with a chip assembly site and contact pads 103 in pad locations and with a metal surface. The substrate further has a second surface 101 b with attachment sites for solder bodies 701.
  • A semiconductor chip is attached to the assembly site (not shown in FIG. 8C); the attachment and assembly may be performed by wire bonding, as depicted in the example of FIG. 7, or by flip-chip technology, shown in FIG. 6B.
  • The embodiment has an encapsulated region, only on the top of the substrate and defined by the substrate perimeter 820. Consequently, the encapsulation material covers the whole top substrate area of the device, including the chip. The encapsulation forms contact apertures 703 at the pad locations for permitting external communication with the pad metal surfaces 103; preferably, the apertures have the shape of cones. The surfaces of the aperture sidewalls include compound structures, which have been modified from the otherwise smooth surface by the process employed to clean up the pad metal surfaces and thus bear witness of the selected process.
  • As an example, when the compound structures on the sidewalls include thermally modified compound particles, such as rounded particles, they indicate that a laser technique has been used to remove an incidental compound layer from the pad surface and thus expose the pad metal.
  • Alternatively, when the aperture sidewalls have a roughened surface, they indicate that a plasma clean-up process has been used to expose the pad metal.
  • In another situation, the aperture sidewalls may have surface structures recognizable by one skilled in the art as residues of a chemical etch process used to expose the pad metal.
  • In one row of apertures, FIG. 8C depicts elongated grooves in the contact apertures operable as gas release channels. While allowing trapped gas to escape in the process of reflowing a solder ball in the aperture, these grooves may end up being filled with solder. The support function is especially beneficial during the process step of attaching another semiconductor device 902 with solder bodies 910 to the first substrate surface of the first device 901 in order to produce a package-on-package semiconductor product as shown in FIG. 9. In this attachment process, the pad surfaces 103 are contacted by the solder bodies 910 of the second device 902, creating the package-on-package assembly. FIG. 9 stresses the preferred combination of devices, wherein not only the molding compound 920 of first device 901 extends to the substrate perimeter 901 a, but also the molding compound 930 of second device 902 extends to the substrate perimeter 902 a. This combination minimizes the risk of device warpage in the assembly process.
  • While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the invention applies to products using any type of semiconductor chip, discrete or integrated circuit, and the material of the semiconductor chip may comprise silicon, silicon germanium, gallium arsenide, or any other semiconductor or compound material used in integrated circuit manufacturing.
  • As another example, the metal protrusions of the top mold portion may be shaped as cylinders, cubes, rhomboids, or any other 3-dimensional configuration. It is therefore intended that the appended claims encompass any such modifications or embodiment.

Claims (24)

  1. 1. A method for fabricating a semiconductor device comprising the steps of:
    providing a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, the substrate having a first surface with chip assembly sites and contact pads in pad locations, and a second surface;
    providing semiconductor chips;
    attaching a chip to each assembly site;
    providing a mold having top and bottom portions, the top portion forming a cavity for holding semiconductor devices;
    the top portion including protrusions at locations matching the pad locations, the protrusions shaped as truncated cones of a height suitable to approach the pad metal surface when the mold is in a closed form;
    the bottom portion being without corresponding protrusions;
    loading the substrate with the chips onto the bottom mold portion, resting the second substrate surface on the mold and positioning the first surface with the contact pads away from the bottom mold portion;
    closing the mold by clamping the top portion onto the bottom portion so that the protrusions are aligned with the contact pads, approaching the pad surface;
    pressuring molding compound into the cavity to fill the cavity, thereby creating an encapsulation;
    opening the mold and removing the substrate together with the encapsulated chips from the mold, the encapsulation having apertures to the pad locations; and
    removing any residual compound on the pads to expose the metal surface.
  2. 2. The method according to claim 1 wherein the protrusions approach the pad metal surface in the closed cavity to a distance between 0 and 100 μm.
  3. 3. The method according to claim 1 wherein the protrusion touches the pad metal surface in the closed mold.
  4. 4. The method according to claim 1 wherein the metal protrusions further include a ridge operable to create an aperture having a gas release channel in the aperture.
  5. 5. The method according to claim 1 wherein the step of removing residual compound from the pad surface is performed by the process of shining laser light into the encapsulation apertures, thereby depositing compound particles on the otherwise smooth sidewalls.
  6. 6. The method according to claim 1 wherein the step of removing residual compound from the pad surface is performed by a plasma clean-up process, thereby creating a roughened surface on the aperture sidewalls.
  7. 7. The method according to claim 1 wherein the step of removing residual compound from the pad surface is performed by a chemical etch process, thereby leaving etch structures on the aperture sidewalls.
  8. 8. The method according to claim 1 further including, before the step of loading the substrate, the step of placing a compliant film over the top portion loaded with the inserts.
  9. 9. The method according to claim 8 further including, after the step of opening the mold, the step of peeling the compliant film off the top portion.
  10. 10. The method according to claim 1 wherein the step of attaching the chip includes wire bonding.
  11. 11. The method according to claim 1 wherein the step of attaching the chip includes a flip-chip process.
  12. 12. The method according to claim 1 further including the step of attaching solder balls to the second substrate surface.
  13. 13. The method according to claim 1 further including the step of filling the encapsulation apertures to the pads with solder material.
  14. 14. The method according to claim 1 further including the step of singulating individual units from the sheet-like substrate.
  15. 15. The method according to claim 14 wherein the step of singulating is performed by a sawing process, thereby creating a surface with saw marks.
  16. 16. The method according to claim 15 further including the step of attaching another semiconductor device with solder balls to the first substrate surface of the singulated unit so that the exposed pad surfaces are contacted by the solder balls, thereby creating a package-on-package semiconductor assembly.
  17. 17. The method according to claim 1 wherein the pad metal surface has a layer including gold or palladium.
  18. 18. An apparatus for the fabrication of a semiconductor device comprising:
    a mold having top and bottom portions, the top portion having a cavity for holding semiconductor devices, the device includes a semiconductor chip attached to a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, the substrate having contact pads in pad locations;
    the mold operable to be closed by clamping the top portion onto the bottom portion;
    the top portion including protrusions at locations matching the pad locations, the protrusions shaped as truncated cones of a height suitable to approach the pad metal surface in the closed mold; and
    the bottom portion being without corresponding protrusions.
  19. 19. A device comprising:
    a sheet-like insulating substrate integral with two or more patterned layers of conductive lines and vias, the substrate having a first surface with a chip assembly site and contact pads in pad locations, and a second surface;
    a semiconductor chip attached to the assembly site; and
    an encapsulated region on the first surface, extending to the edge of the substrate, enclosing the chip and having contact apertures at the pad locations for external communication with the metal surfaces, the apertures having a not-smooth sidewall surfaces.
  20. 20. The device according to claim 19 wherein the not-smooth aperture sidewall surfaces include laser spalled compound particles.
  21. 21. The device according to claim 19 wherein the not-smooth aperture sidewalls include a plasma-roughened surface.
  22. 22. The device according to claim 19 wherein the not-smooth aperture sidewall surfaces have chemically etched structures.
  23. 23. The device according to claim 19 wherein the semiconductor chip is attached to the substrate by wire bonding.
  24. 24. The device according to claim 19 wherein the semiconductor chip is attached on the substrate by a flip-chip process.
US11750757 2007-05-18 2007-05-18 Method for Fabricating Array-Molded Package-On-Package Abandoned US20080284045A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11750757 US20080284045A1 (en) 2007-05-18 2007-05-18 Method for Fabricating Array-Molded Package-On-Package

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11750757 US20080284045A1 (en) 2007-05-18 2007-05-18 Method for Fabricating Array-Molded Package-On-Package
PCT/US2008/064040 WO2008144605A1 (en) 2007-05-18 2008-05-19 Array-molded package-on-package semiconductor device and method
US13050177 US20110165731A1 (en) 2007-05-18 2011-03-17 Method for Fabricating Array-Molded Package-on-Package
US13789109 US8574967B2 (en) 2007-05-18 2013-03-07 Method for fabricating array-molded package-on-package
US14043305 US20140030851A1 (en) 2007-05-18 2013-10-01 Method for Fabricating Array-Molded Package-on-Package

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13050177 Division US20110165731A1 (en) 2007-05-18 2011-03-17 Method for Fabricating Array-Molded Package-on-Package

Publications (1)

Publication Number Publication Date
US20080284045A1 true true US20080284045A1 (en) 2008-11-20

Family

ID=40026709

Family Applications (4)

Application Number Title Priority Date Filing Date
US11750757 Abandoned US20080284045A1 (en) 2007-05-18 2007-05-18 Method for Fabricating Array-Molded Package-On-Package
US13050177 Abandoned US20110165731A1 (en) 2007-05-18 2011-03-17 Method for Fabricating Array-Molded Package-on-Package
US13789109 Active US8574967B2 (en) 2007-05-18 2013-03-07 Method for fabricating array-molded package-on-package
US14043305 Abandoned US20140030851A1 (en) 2007-05-18 2013-10-01 Method for Fabricating Array-Molded Package-on-Package

Family Applications After (3)

Application Number Title Priority Date Filing Date
US13050177 Abandoned US20110165731A1 (en) 2007-05-18 2011-03-17 Method for Fabricating Array-Molded Package-on-Package
US13789109 Active US8574967B2 (en) 2007-05-18 2013-03-07 Method for fabricating array-molded package-on-package
US14043305 Abandoned US20140030851A1 (en) 2007-05-18 2013-10-01 Method for Fabricating Array-Molded Package-on-Package

Country Status (2)

Country Link
US (4) US20080284045A1 (en)
WO (1) WO2008144605A1 (en)

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070148822A1 (en) * 2005-12-23 2007-06-28 Tessera, Inc. Microelectronic packages and methods therefor
US20080308918A1 (en) * 2007-06-18 2008-12-18 Seung Taek Yang Semiconductor package with passive elements
US20080315385A1 (en) * 2007-06-22 2008-12-25 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US20100148360A1 (en) * 2008-12-12 2010-06-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US20110183466A1 (en) * 2007-08-17 2011-07-28 Yu-Ren Chen Packaging method involving rearrangement of dice
US20110233747A1 (en) * 2010-03-25 2011-09-29 Seongmin Lee Integrated circuit packaging system with stacking option and method of manufacture thereof
US20120231582A1 (en) * 2008-11-26 2012-09-13 Infineon Technologies Ag Device including a semiconductor chip
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8753926B2 (en) 2010-09-14 2014-06-17 Qualcomm Incorporated Electronic packaging with a variable thickness mold cap
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8853849B2 (en) * 2013-03-06 2014-10-07 Infineon Technologies Austria Ag Package arrangement and a method of manufacturing a package arrangement
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US20150115463A1 (en) * 2013-10-31 2015-04-30 Perry H. Pelley Stacked semiconductor devices
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9076664B2 (en) 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9269887B1 (en) * 2015-01-06 2016-02-23 Triquint Semiconductor, Inc. Ultrathin flip-chip packaging techniques and configurations
US9293401B2 (en) 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10115678B2 (en) 2017-11-06 2018-10-30 Invensas Corporation Wire bond wires for interference shielding

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010002669A1 (en) 2010-03-08 2011-09-08 Gühring Ohg Rotatably drivable cutting tool
KR101388892B1 (en) * 2012-08-20 2014-04-29 삼성전기주식회사 Package substrate, manufacturing method thereof and manufacturing mold thereof
FR3018630A1 (en) * 2014-03-11 2015-09-18 St Microelectronics Grenoble 2 Electronic Case punches and method of manufacture

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5732465A (en) * 1994-07-15 1998-03-31 Shinko Electric Industries Co., Ltd. Method of manufacturing one side resin sealing type semiconductor devices
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6250606B1 (en) * 1999-06-29 2001-06-26 Sharp Kabushiki Kaisha Substrate for semiconductor device, semiconductor device and manufacturing method thereof
US6338813B1 (en) * 1999-10-15 2002-01-15 Advanced Semiconductor Engineering, Inc. Molding method for BGA semiconductor chip package
US6420201B1 (en) * 2001-01-03 2002-07-16 Amkor Technology, Inc. Method for forming a bond wire pressure sensor die package
US6498055B2 (en) * 2000-05-17 2002-12-24 Kabushiki Kaisha Toshiba Semiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing system
US6534338B1 (en) * 2001-06-29 2003-03-18 Amkor Technology, Inc. Method for molding semiconductor package having a ceramic substrate
US6767767B2 (en) * 2001-08-31 2004-07-27 Renesas Technology Corp. Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate
US7185426B1 (en) * 2002-05-01 2007-03-06 Amkor Technology, Inc. Method of manufacturing a semiconductor package
US20080036050A1 (en) * 2006-08-08 2008-02-14 Lin Paul T Package with solder-filled via holes in molding layers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3308934B2 (en) * 1999-06-22 2002-07-29 九州日本電気株式会社 Method for producing a resin molded bga semiconductor device
US6247229B1 (en) * 1999-08-25 2001-06-19 Ankor Technology, Inc. Method of forming an integrated circuit device package using a plastic tape as a base
US6379988B1 (en) * 2000-05-16 2002-04-30 Sandia Corporation Pre-release plastic packaging of MEMS and IMEMS devices

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5732465A (en) * 1994-07-15 1998-03-31 Shinko Electric Industries Co., Ltd. Method of manufacturing one side resin sealing type semiconductor devices
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6250606B1 (en) * 1999-06-29 2001-06-26 Sharp Kabushiki Kaisha Substrate for semiconductor device, semiconductor device and manufacturing method thereof
US6338813B1 (en) * 1999-10-15 2002-01-15 Advanced Semiconductor Engineering, Inc. Molding method for BGA semiconductor chip package
US6498055B2 (en) * 2000-05-17 2002-12-24 Kabushiki Kaisha Toshiba Semiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing system
US6420201B1 (en) * 2001-01-03 2002-07-16 Amkor Technology, Inc. Method for forming a bond wire pressure sensor die package
US6534338B1 (en) * 2001-06-29 2003-03-18 Amkor Technology, Inc. Method for molding semiconductor package having a ceramic substrate
US6767767B2 (en) * 2001-08-31 2004-07-27 Renesas Technology Corp. Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate
US7185426B1 (en) * 2002-05-01 2007-03-06 Amkor Technology, Inc. Method of manufacturing a semiconductor package
US20080036050A1 (en) * 2006-08-08 2008-02-14 Lin Paul T Package with solder-filled via holes in molding layers

Cited By (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927337B2 (en) 2004-11-03 2015-01-06 Tessera, Inc. Stacked packaging improvements
US8531020B2 (en) 2004-11-03 2013-09-10 Tessera, Inc. Stacked packaging improvements
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US20070148822A1 (en) * 2005-12-23 2007-06-28 Tessera, Inc. Microelectronic packages and methods therefor
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US20100232129A1 (en) * 2005-12-23 2010-09-16 Tessera, Inc. Microelectronic packages and methods therefor
US8093697B2 (en) 2005-12-23 2012-01-10 Tessera, Inc. Microelectronic packages and methods therefor
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7834437B2 (en) * 2007-06-18 2010-11-16 Hynix Semiconductor Inc. Semiconductor package with passive elements
US20080308918A1 (en) * 2007-06-18 2008-12-18 Seung Taek Yang Semiconductor package with passive elements
US7944034B2 (en) * 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US20080315385A1 (en) * 2007-06-22 2008-12-25 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US20110183466A1 (en) * 2007-08-17 2011-07-28 Yu-Ren Chen Packaging method involving rearrangement of dice
US8431437B2 (en) * 2007-08-17 2013-04-30 Chipmos Technologies Inc Packaging method involving rearrangement of dice
US20120231582A1 (en) * 2008-11-26 2012-09-13 Infineon Technologies Ag Device including a semiconductor chip
US9293401B2 (en) 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US9847324B2 (en) 2008-12-12 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9768155B2 (en) 2008-12-12 2017-09-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20100148360A1 (en) * 2008-12-12 2010-06-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US8796846B2 (en) 2008-12-12 2014-08-05 Stats Chippac, Ltd. Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSP
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9401331B2 (en) 2008-12-12 2016-07-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20110233747A1 (en) * 2010-03-25 2011-09-29 Seongmin Lee Integrated circuit packaging system with stacking option and method of manufacture thereof
KR101801834B1 (en) * 2010-03-25 2017-11-27 스태츠 칩팩 피티이. 엘티디. Integrated circuit packaging system with stacking option and method of manufacture thereof
US8378476B2 (en) * 2010-03-25 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with stacking option and method of manufacture thereof
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US8907466B2 (en) 2010-07-19 2014-12-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8753926B2 (en) 2010-09-14 2014-06-17 Qualcomm Incorporated Electronic packaging with a variable thickness mold cap
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8659164B2 (en) 2010-11-15 2014-02-25 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8637991B2 (en) 2010-11-15 2014-01-28 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US9076664B2 (en) 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9041227B2 (en) 2011-10-17 2015-05-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US8994185B2 (en) 2011-12-14 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9095074B2 (en) 2012-12-20 2015-07-28 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US8853849B2 (en) * 2013-03-06 2014-10-07 Infineon Technologies Austria Ag Package arrangement and a method of manufacturing a package arrangement
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9633979B2 (en) 2013-07-15 2017-04-25 Invensas Corporation Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US20150115463A1 (en) * 2013-10-31 2015-04-30 Perry H. Pelley Stacked semiconductor devices
US9082757B2 (en) * 2013-10-31 2015-07-14 Freescale Semiconductor, Inc. Stacked semiconductor devices
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9893033B2 (en) 2013-11-12 2018-02-13 Invensas Corporation Off substrate kinking of bond wire
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9812433B2 (en) 2014-03-31 2017-11-07 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9356006B2 (en) 2014-03-31 2016-05-31 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10032647B2 (en) 2014-05-29 2018-07-24 Invensas Corporation Low CTE component with wire bond interconnects
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9269887B1 (en) * 2015-01-06 2016-02-23 Triquint Semiconductor, Inc. Ultrathin flip-chip packaging techniques and configurations
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10115678B2 (en) 2017-11-06 2018-10-30 Invensas Corporation Wire bond wires for interference shielding

Also Published As

Publication number Publication date Type
WO2008144605A1 (en) 2008-11-27 application
US20110165731A1 (en) 2011-07-07 application
US20130189814A1 (en) 2013-07-25 application
US20140030851A1 (en) 2014-01-30 application
US8574967B2 (en) 2013-11-05 grant

Similar Documents

Publication Publication Date Title
US6268648B1 (en) Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device
US5606198A (en) Semiconductor chip with electrodes on side surface
US7883991B1 (en) Temporary carrier bonding and detaching processes
US7361533B1 (en) Stacked embedded leadframe
US6528351B1 (en) Integrated package and methods for making same
US7749882B2 (en) Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7138706B2 (en) Semiconductor device and method for manufacturing the same
US7394152B2 (en) Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same
US7834464B2 (en) Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US20070045836A1 (en) Stacked chip package using warp preventing insulative material and manufacturing method thereof
US20070287265A1 (en) Substrate treating method and method of manufacturing semiconductor apparatus
US8759964B2 (en) Wafer level package structure and fabrication methods
US20090236031A1 (en) Method of manufacturing wiring substrate and method of manufacturing semiconductor device
US20070045812A1 (en) Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
US6710461B2 (en) Wafer level packaging of micro electromechanical device
US20090146301A1 (en) Semiconductor device and method of manufacturing the same
US20070069389A1 (en) Stackable device, device stack and method for fabricating the same
US6701614B2 (en) Method for making a build-up package of a semiconductor
US6822324B2 (en) Wafer-level package with a cavity and fabricating method thereof
US6582992B2 (en) Stackable semiconductor package and wafer level fabrication method
US20130049205A1 (en) Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps
US7495179B2 (en) Components with posts and pads
US6818998B2 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
US20070158809A1 (en) Multi-chip package system
US20090115042A1 (en) Semiconductor device having three-dimensional stacked structure and method of fabricating the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GERBER, MARK A.;WALTER, DAVID N.;REEL/FRAME:019504/0746

Effective date: 20070522