KR20010018694A - Manufacturing method for three demensional stack chip package - Google Patents

Manufacturing method for three demensional stack chip package Download PDF

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Publication number
KR20010018694A
KR20010018694A KR1019990034753A KR19990034753A KR20010018694A KR 20010018694 A KR20010018694 A KR 20010018694A KR 1019990034753 A KR1019990034753 A KR 1019990034753A KR 19990034753 A KR19990034753 A KR 19990034753A KR 20010018694 A KR20010018694 A KR 20010018694A
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South Korea
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electrode pad
wafer
semiconductor chips
semiconductor chip
circuit pattern
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KR1019990034753A
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Korean (ko)
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KR100565961B1 (en
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송근호
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윤종용
삼성전자 주식회사
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Priority to KR1019990034753A priority Critical patent/KR100565961B1/en
Publication of KR20010018694A publication Critical patent/KR20010018694A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a three-dimensional stacked chip package is provided to simplify a manufacturing process, by electrically interconnecting semiconductor chips located in upper and lower portions not in a stacked state of the semiconductor chips but in a wafer state. CONSTITUTION: A passivation layer(12) is formed on an active surface of a wafer having a predetermined integrated circuit and electrode pad(11), to cover the integrated circuit and the electrode pad. Holes penetrating the wafer are formed along a scribe line to divide the wafer into individual unit semiconductor chips(10). A circuit pattern(15) adjacent to the holes is formed on a surface opposite to the active surface of the wafer. The electrode pad has an opened portion to eliminate the passivation layer from the holes to the electrode pad. A metal layer(16) in contact with the electrode pad and the circuit pattern is formed. An external terminal is formed on the electrode pad, projected from the passivation layer by a predetermined height. The scribe line is cut to separate the unit semiconductor chips from the wafer. The external terminal of the semiconductor chip located in an upper portion and the circuit pattern of the semiconductor chip located in a lower portion are connected to stack at least the two unit semiconductor chips.

Description

3차원 적층 칩 패키지 제조 방법{Manufacturing method for three demensional stack chip package}Manufacturing method for three demensional stack chip package

본 발명은 반도체 장치에 관한 것으로서, 더욱 상세하게는 복수의 단위 반도체 칩이 수직으로 적층되어 전기적으로 상호 접속되어 구성되는 3차원 적층 칩 패키지와 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a three-dimensional stacked chip package in which a plurality of unit semiconductor chips are vertically stacked and electrically interconnected, and a manufacturing method thereof.

반도체 소자와 그에 대한 패키지 기술은 상호 부합되어 고밀도화, 고속도화, 소형화 및 박형화를 목표로 계속적인 발전을 거듭해 왔다. 패키지 구조에 있어서 핀 삽입형에서 표면 실장형으로 급격히 진행되어 회로기판에 대한 실장 밀도를 높여 왔으며, 최근에는 베어 칩(bare chip)의 특성을 그대로 패키지 상태에서 유지하면서도 취급이 용이하고 패키지 크기가 크게 줄어든 칩 크기 패키지(CSP; Chip Scale Package)가 여러 제조 회사에서 개발되어 있으며 꾸준한 연구가 진행되고 있다. 또한, 용량과 실장밀도의 증가를 위하여 여러 개의 단위 반도체 칩 또는 단위 반도체 칩 패키지를 적층시킨 형태의 3차원 적층 기술도 주목을 받게 되었다. 특히, 최근에는 반도체 칩 레벨의 3차원 적층 기술에 대한 연구가 활발하다.Semiconductor devices and their packaging technologies have been matched to each other and have continued to develop with the goal of increasing density, high speed, miniaturization and thinning. In the package structure, it has been rapidly progressed from a pin insertion type to a surface mount type, thereby increasing the mounting density of the circuit board. Recently, the bare chip characteristics have been kept in the package state, while being easy to handle and greatly reduced in package size. Chip scale packages (CSPs) have been developed by various manufacturing companies and are being steadily researched. In addition, three-dimensional stacking technology in which a plurality of unit semiconductor chips or unit semiconductor chip packages are stacked in order to increase capacity and mounting density has also received attention. In particular, recent studies on three-dimensional stacking technology at the semiconductor chip level have been actively conducted.

3차원 적층 기술이 대표적으로 적용된 것은 개별적으로 조립 공정이 완료된 단위 반도체 칩 패키지를 여러 개 적층하여 구성되는 적층형 반도체 칩 패키지와 그와는 달리 패키징(packaging)되지 않은 반도체 칩을 여러 개 적층시키는 적층 칩 패키지가 있다. 대표적인 것으로서, 기존의 와이어나 BGA 구조의 패키지에서 사용하는 빔 리드(beam lead)를 사용하지 않고 반도체 칩의 패드를 연결하는 방법은 솔더 범프를 이용하여 반도체 칩을 기판에 실장하는 방법이 있다. 여기서, 적층 칩 패키지에 대한 실시예를 소개하기로 한다.Typical applications of three-dimensional stacking technology include stacked semiconductor chip packages formed by stacking a plurality of unit semiconductor chip packages in which individual assembly processes have been completed, and stacked chips in which several unpacked semiconductor chips are stacked. There is a package. As a representative example, a method of connecting a pad of a semiconductor chip without using a beam lead used in a conventional wire or BGA structure package includes mounting a semiconductor chip on a substrate using solder bumps. Herein, an embodiment of a multilayer chip package will be described.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 칩의 적층 상태의 구조를 나타낸 단면도이다.1A to 1C are cross-sectional views illustrating a structure of a stacked state of a semiconductor chip according to the prior art.

종래에 많이 알려젼 적층 칩 패키지(110)는 도 1a에 도시된 바와 같이 하부에 위치한 반도체 칩(111) 위에 다른 반도체 칩(113)이 부착되고 동일한 기능을 수행하는 각 반도체 칩(111,113)의 전극패드(112,114)를 도전성 금속선(116)으로 리드(115)에 와이어 본딩하여 에폭시 성형 수지로 패키지 몸체(117)를 형성한 형태의 것과, 도 1b에 도시된 바와 같이 기판(121)을 중심으로 상면과 하면에 솔더 범프(122)를 이용하여 각각 반도체 칩(123,124)을 실장하여 구성되는 형태의 것이 있다. 그러나, 전자의 패키지(110) 경우에 와이어 루프(wire loop)의 높이를 확보해야 하는 등의 요인으로 패키지 크기가 크게 증가되고 반도체 칩을 2개 이상의 적층하는 것도 용이하지 않다. 또한, 후자의 경우 하나의 반도체 칩(123,124)을 기판(121)에 부착하고 나면 그 반도체 칩(123,124)들의 상부에 두번 째 반도체 칩을 적층하여 전기적인 연결을 하기가 어렵다. 즉, 반도체 칩을 3차원으로 적층하기 위해서는 플립 칩 방법으로 한계가 있다는 것이다.Conventionally known multi-layer chip package 110 is the electrode of each semiconductor chip (111, 113) that is attached to the other semiconductor chip 113 on the semiconductor chip 111 located at the bottom as shown in Figure 1a performs the same function The pads 112 and 114 are wire-bonded to the lead 115 with a conductive metal wire 116 to form the package body 117 with an epoxy molding resin, and the upper surface of the upper surface of the substrate 121 as shown in FIG. The semiconductor chips 123 and 124 may be mounted on the upper and lower surfaces by using the solder bumps 122, respectively. However, in the case of the former package 110, the package size is greatly increased due to factors such as the need to secure the height of the wire loop, and it is not easy to stack two or more semiconductor chips. In the latter case, once one semiconductor chip 123 or 124 is attached to the substrate 121, it is difficult to electrically connect a second semiconductor chip on top of the semiconductor chips 123 and 124. In other words, there is a limit to the flip chip method for stacking semiconductor chips in three dimensions.

이와 같은 문제점을 해결하기 위한 것으로서 IBM사에서 개발된 형태가 도 1c에 도시된 바와 같은 형태의 적층 칩 패키지(130)이다. 이 적층 칩 패키지(130)는 가장 하부에 위치한 반도체 칩(131)은 플립 칩 본딩(flip chip bonding) 방법으로 기판(141)에 실장할 수 있도록 솔더 볼(132)이 형성되어 있고 그 반도체 칩(131)에 적층되는 반도체 칩들(133)은 솔더 볼이 형성되어 있지 않은 것으로서, 적층되는 각 반도체 칩들(131,133)간에는 에지(edge) 부분이 전기 전도성의 금속 재질로 메탈리제이션(metalization)되어 금속층(135)이 형성되어 있고 그 금속층(135)들이 전기 전도성질을 갖는 접착제(136)에 의해 접합되므로써 상호 접속된 구조이다.In order to solve this problem, a form developed by IBM is a stacked chip package 130 having a form as illustrated in FIG. 1C. In the stacked chip package 130, the lowermost semiconductor chip 131 is formed with solder balls 132 to be mounted on the substrate 141 by flip chip bonding. The semiconductor chips 133 stacked on the 131 have no solder balls, and an edge portion is metallized with an electrically conductive metal material between the semiconductor chips 131 and 133 to be stacked. 135 is formed and the metal layers 135 are interconnected by being joined by an adhesive 136 having electrical conductivity.

이와 같은 적층 칩 패키지의 경우에 에지 부분의 메탈리제이션은 웨이퍼에서 반도체 칩을 소잉(sawing)한 후 반도체 칩을 튜브(tube)안에 쌓아서 측면을 금속 증착(metal deposition)하는 방법을 사용한다. 그런데 이와 같은 방법은 반도체 칩 하나의 네면을 모두 에지 부분에서 메탈리제이션 하기 위해서 웨이퍼를 소잉한 후 낱개로 분리된 반도체 칩들을 튜브안에 넣어 칩 에지를 메탈리제이션하기 때문에 생산 효율에 문제가 있다. 웨이퍼 상태에서 소잉되어 분리된 각각의 반도체 칩을 낱개로 취급해야 하기 때문에 각각의 반도체 칩에 대하여 균일한 금속 증착이 이루어지지 않으며 금속 증착 효율이 떨어지게 된다. 또한, 같은 종류의 칩을 2가지로 만들어야 하고 가장자리만 접속되기 때문에 설계 레이아웃(layout)을 제한하게 된다.In the case of such a stacked chip package, the metallization of the edge portion uses a method of sawing the semiconductor chip on the wafer and then stacking the semiconductor chip in a tube to metal-deposit the sides. However, this method has a problem in production efficiency because all four surfaces of a semiconductor chip are metallized by inserting the separated semiconductor chips into a tube after sawing the wafer in order to metallize all the edges at the edge portion. Since each of the semiconductor chips that are sawed and separated in the wafer state must be handled individually, uniform metal deposition is not performed for each semiconductor chip, and metal deposition efficiency is lowered. Also, because two chips of the same type must be made and only the edges are connected, the design layout is limited.

본 발명의 목적은 상기한 바와 같은 문제점을 개선하기 위하여 단위 반도체 칩을 복수 개 적층하여 적층 칩 패키지를 제조할 때 각 반도체 칩들간의 상호 접속을 하는 공정이 용이하게 이루어질 수 있는 3차원 적층 패키지 제조 방법을 제공하는 데에 있다.An object of the present invention is to manufacture a three-dimensional stacked package that can be easily made a process of interconnecting each semiconductor chip when manufacturing a stacked chip package by stacking a plurality of unit semiconductor chips in order to improve the problems as described above To provide a way.

도 1a 내지 도 1c는 종래 기술에 따른 3차원 적층 칩 패키지들의 실시예로서, 여러 가지 상호 연결(interconnection)구조를 개략적으로 나타낸 단면도.1A to 1C are cross-sectional views schematically showing various interconnect structures as an embodiment of a three-dimensional stacked chip package according to the prior art.

도 2 내지 도 9는 본 발명에 따른 3차원 적층 칩 패키지의 제조 공정을 나타낸 단면도.2 to 9 are cross-sectional views showing the manufacturing process of the three-dimensional stacked chip package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 반도체 칩 11,112,114: 전극패드10: semiconductor chip 11,112,114: electrode pad

12: 보호막 13: 스크라이브 라인(scribe line)12: Shield 13: scribe line

14: 구멍 15: 회로패턴14: hole 15: circuit pattern

16: 금속층 17: 솔더16: metal layer 17: solder

18: 솔더 볼 30: 웨이퍼18: solder ball 30: wafer

50: 3차원 적층 칩 패키지50: 3D stacked chip package

이와 같은 목적을 달성하기 위한 본 발명에 따른 3차원 적층 패키지 제조 방법은, ⒜ 소정의 집적회로와 전극패드가 형성된 웨이퍼의 활성면에 상기 집적회로와 전극패드를 덮도록 보호막을 형성하는 단계, ⒝ 상기 웨이퍼를 단위 반도체 칩으로 분리하기 위한 스크라이브 라인을 따라 상기 웨이퍼를 관통하는 구멍을 형성하는 단계, ⒞ 상기 웨이퍼의 활성면에 대응되는 반대면에 상기 구멍에 인접하는 회로패턴을 형성하는 단계, ⒟ 상기 전극패드가 개방된 부분을 갖도록 하여 상기 구멍으로부터 상기 전극패드까지의 보호막을 제거하는 단계, ⒠ 상기 전극패드와 상기 회로패턴에 접속되는 금속층을 형성하는 단계, ⒡ 상기 전극패드의 상부에 상기 보호막으로부터 소정의 높이로 돌출되는 외부 접속 단자를 형성하는 단계, ⒢ 상기 스크라이브 라인을 절단하여 단위 반도체 칩으로 분리시키는 단계, 및 ⒣ 상기 단위 반도체 칩들을 상부에 위치한 반도체 칩의 외부 접속 단자와 하부에 위치한 반도체 칩의 회로패턴이 접속되도록 하여 적어도 두 개 이상의 단위 반도체 칩들을 적층하여 접합시키는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a three-dimensional multilayer package, the method comprising: forming a protective film on an active surface of a wafer on which a predetermined integrated circuit and an electrode pad are formed to cover the integrated circuit and the electrode pad; Forming a hole that penetrates the wafer along a scribe line for separating the wafer into unit semiconductor chips, and (f) forming a circuit pattern adjacent to the hole on an opposite surface corresponding to the active surface of the wafer; Removing the protective film from the hole to the electrode pad by having the open portion of the electrode pad, forming a metal layer connected to the electrode pad and the circuit pattern, and forming the protective film on the electrode pad. Forming an external connection terminal protruding to a predetermined height from the second scribe line Cutting and separating the unit semiconductor chips into unit semiconductor chips, and (b) stacking and bonding at least two unit semiconductor chips such that the unit semiconductor chips are connected to an external connection terminal of an upper semiconductor chip and a circuit pattern of a lower semiconductor chip. It characterized in that it comprises a step of.

이하 본 발명에 따른 3차원 적층 칩 패키지의 제조 방법을 도 2내지 도 8을 참조하여 상세하게 설명하기로 한다.Hereinafter, a method of manufacturing a 3D stacked chip package according to the present invention will be described in detail with reference to FIGS. 2 to 8.

도 2 내지 도 9는 본 발명에 따른 3차원 적층 칩 패키지의 제조 공정을 나타낸 단면도이다. 먼저 도 2에 도시된 바와 같이 소정의 집적회로 형성 공정이 완료되어 전극패드(11)가 형성된 웨이퍼(30)의 활성면에 전극패드(11)가 덮여지도록 하여 보호막(12)을 형성한다. 일반적인 웨이퍼 제조 공정(Fabrication)에서 전극패드(12)를 외부로 노출시키기 위한 공정을 진행하지 않으면 도 2와 같은 상태의 웨이퍼(30)를 얻을 수가 있다. 이때, 웨이퍼(30)는 스크라이브 라인(13)의 절단에 의해 복수의 단위 반도체 칩(10)이 될 것이다.2 to 9 are cross-sectional views illustrating a manufacturing process of a three-dimensional stacked chip package according to the present invention. First, as shown in FIG. 2, a predetermined integrated circuit forming process is completed to form the protective layer 12 by covering the electrode pad 11 on the active surface of the wafer 30 on which the electrode pad 11 is formed. If the process for exposing the electrode pad 12 to the outside is not performed in a general wafer fabrication process, the wafer 30 as shown in FIG. 2 can be obtained. In this case, the wafer 30 may be a plurality of unit semiconductor chips 10 by cutting the scribe line 13.

이 상태의 웨이퍼(30)에서 도 3에 도시된 바와 같이 스크라이브 라인(도 2의 13)을 따라서 전극패드(11)에 인접하도록 하여 웨이퍼(30)를 관통하는 구멍(14)을 형성한다. 이 구멍(14)은 이웃하는 반도체 칩(10)들의 각각의 전극패드(11) 사이에 위치하도록 하는 직경을 갖도록 한다. 보통 구멍(14)은 전극패드(11)의 폭과 패드 피치(pad pitch)를 고려하여 50-200㎛의 직경을 갖도록 한다. 구멍(14)의 형성은 화학적 에칭(etching)이나 FIB의 방법으로 형성하는 것이 가능하나, 화학적 에칭의 경우에 구멍을 뚫기가 쉽지 않으며 반도체 칩(10)의 표면에 형성된 금속 또는 보호막에 손상을 줄 수 있기 때문에 레이저(laser)를 이용하여 형성한다. 바람직하게는 실리콘 에칭(silicon etching) 용액으로 일부분(약20-30%)을 에칭한 후 나머지를 레이저나 FIB를 이용하여 구멍을 형성한다.In the wafer 30 in this state, as shown in FIG. 3, the hole 14 penetrating the wafer 30 is formed along the scribe line (13 in FIG. 2) so as to be adjacent to the electrode pad 11. The hole 14 has a diameter so as to be positioned between each electrode pad 11 of the neighboring semiconductor chips 10. Usually, the holes 14 have a diameter of 50-200 μm in consideration of the width of the electrode pad 11 and the pad pitch. The hole 14 may be formed by chemical etching or FIB. However, in the case of chemical etching, the hole 14 may not be easily drilled and may damage the metal or the protective film formed on the surface of the semiconductor chip 10. Since it can be formed using a laser (laser). Preferably, a portion (about 20-30%) is etched with a silicon etching solution and the remainder is formed using a laser or FIB.

구멍을 뚫고 나서 세정을 한 후에 도 4에 도시된 바와 같이 집적회로가 형성된 활성면에 대응되는 반대면인 웨이퍼(30)의 밑면에서 각각의 구멍에 접하도록 소정의 회로패턴(15)을 형성한다. 이때, 회로패턴(15)은 독립적으로 구멍(14)에 접하도록 형성한다.After cleaning after the hole is formed, a predetermined circuit pattern 15 is formed to contact each hole on the bottom surface of the wafer 30, which is the opposite side corresponding to the active surface on which the integrated circuit is formed, as shown in FIG. . At this time, the circuit pattern 15 is formed to be in contact with the hole 14 independently.

그리고, 구멍(14)의 주변에 형성된 보호막(12)을 에칭으로 제거하여 도 5에서와 같이 전극패드(11)가 노출되도록 구멍(14)으로부터 전극패드(11)까지의 표면을 개방시키고, 알루미늄 금속이나 알루미늄 합금을 스퍼터링(sputtering)이나 금속 증착(deposition) 방법으로 도 6a와 도 6b에 도시된 바와 같이 전극패드(11)와 웨이퍼(30) 밑면에 형성된 회로패턴(15)을 전기적으로 연결하는 금속층(16)을 형성한다. 즉, 구멍(14)에 의해 형성된 내벽면과 전극패드(11) 및 회로패턴(15)을 전기 전도성이 우수한 알루미늄이나 알루미늄 합금 재질의 금속층(16)으로 연결되도록 하여 전극패드(11)와 회로패턴(15)이 전기적으로 도통되도록 한다. 두께 8000-15000Å의 일반적인 전극패드(11)를 갖는 반도체 칩(10)의 경우에 구멍(14)의 내벽면에 형성되는 금속층(16)의 두께는 500-1000Å이 되도록 증착하여 도통시킨다.Then, the protective film 12 formed around the hole 14 is removed by etching to open the surface from the hole 14 to the electrode pad 11 so that the electrode pad 11 is exposed as shown in FIG. As shown in FIGS. 6A and 6B, the electrode pattern 11 and the circuit pattern 15 formed on the bottom surface of the wafer 30 are electrically connected to each other by sputtering or metal deposition of a metal or an aluminum alloy. The metal layer 16 is formed. That is, the electrode pad 11 and the circuit pattern are connected to the inner wall surface formed by the hole 14, the electrode pad 11, and the circuit pattern 15 by the metal layer 16 made of aluminum or aluminum alloy having excellent electrical conductivity. Let (15) be electrically conductive. In the case of the semiconductor chip 10 having the general electrode pad 11 having a thickness of 8000-15000 kPa, the thickness of the metal layer 16 formed on the inner wall surface of the hole 14 is deposited so as to be 500-1000 kPa.

다음에 도 7과 도 8에 도시된 것과 같이 외부와의 전기적 연결을 위한 솔더 볼(18)의 형성을 위하여 전극패드(11)와 반도체 칩(10) 상면의 금속층(16) 부분의 상부에 솔더(17)를 도포하여 외부 접속 수단으로 솔더 볼(18)을 형성한다. 이때, 솔더 볼(18)은 반도체 칩(10)의 상면, 즉 보호막(12)으로부터 소정의 높이만큼 돌출되도록 형성한다. 솔더 볼(18) 대신에 일반적인 금 범프나 솔더 범프를 형성하는 것도 가능하다.Next, as shown in FIGS. 7 and 8, the solder pad 18 is formed on the upper portion of the electrode pad 11 and the metal layer 16 on the upper surface of the semiconductor chip 10 to form the solder balls 18 for electrical connection with the outside. (17) is apply | coated and the solder ball 18 is formed by an external connection means. In this case, the solder balls 18 are formed to protrude from the upper surface of the semiconductor chip 10, that is, the protective film 12 by a predetermined height. Instead of the solder balls 18, it is also possible to form common gold bumps or solder bumps.

전술한 일련의 공정으로 전극패드(11)와 회로패턴(15)이 금속층(16)으로 연결되고 솔더 볼(18)이 형성되면, 웨이퍼(30)의 스크라이브 라인(도 2의 13)을 절단하여 웨이퍼(30)로부터 각각의 반도체 칩(10)을 분리시킨다. 이때, 구멍(14)의 중앙 부위가 절단되어 각각의 반도체 칩(10)이 전극패드(11)와 회로패턴(15)을 연결하는 금속층(16)을 갖는 적층에 유리한 구조의 단위 반도체 칩(10)이 완성된다.When the electrode pad 11 and the circuit pattern 15 are connected to the metal layer 16 and the solder balls 18 are formed by the above-described series of processes, the scribe lines (13 in FIG. 2) of the wafer 30 are cut off. Each semiconductor chip 10 is separated from the wafer 30. At this time, the central portion of the hole 14 is cut so that each semiconductor chip 10 has an advantageous structure for stacking with the metal layer 16 connecting the electrode pad 11 and the circuit pattern 15. ) Is completed.

다음에 도 9에 도시된 바와 같이 복수의 단위 반도체 칩(10)들을 적층하여 접합시킨다. 상부에 위치한 반도체 칩(10)의 솔더 볼(18)과 하부에 위치한 반도체 칩(10)의 회로패턴(15)이 접속되는 형태로 여러 개의 반도체 칩(10)을 적층한 후 리플로우(reflow) 공정을 거치면 반도체 칩(10)들이 접합되어 하부에 위치한 반도체 칩(10)의 전극패드(11)와 상부에 위치한 반도체 칩(10)의 전극패드(11)가 전기적으로 도통될 수 있게 된다. 반도체 칩(10)들간의 접합력 향상을 위하여 솔더 페이스트(solder paste)와 같은 별도의 접착제를 사용할 수도 있다. 또한, 단위 반도체 칩(10)은 측면의 금속층(16)이 형성된 부분이 홈이 형성된 형태이기 때문에 별도의 솔더 볼을 부착하여 상부와 하부의 반도체 칩(10)들을 상호 연결시켜 줄 수 있다.Next, as illustrated in FIG. 9, the plurality of unit semiconductor chips 10 are stacked and bonded to each other. Reflow after stacking a plurality of semiconductor chips 10 in such a way that the solder ball 18 of the semiconductor chip 10 located on the upper side and the circuit pattern 15 of the semiconductor chip 10 located on the lower side are connected. Through the process, the semiconductor chips 10 are bonded to each other so that the electrode pads 11 of the semiconductor chip 10 located below and the electrode pads 11 of the semiconductor chip 10 located above may be electrically conductive. In order to improve the bonding strength between the semiconductor chips 10, a separate adhesive such as solder paste may be used. In addition, since the unit semiconductor chip 10 has a groove-formed portion of the side metal layer 16, a separate solder ball may be attached to interconnect the upper and lower semiconductor chips 10.

이상에서 살펴본 바와 같이 본 발명에 따른 3차원 적층 칩 패키지 제조 방법은 웨이퍼 상태에서 반도체 칩들간의 경계인 스크라이브 라인을 따라서 구멍을 형성하고 전극패드와 반도체 칩의 밑면에 형성된 회로패턴을 접속시키는 금속층을 형성하여 각각의 단위 반도체 칩으로 분리 후 솔더 리플로우 공정으로 3차원 적층 칩 패키지의 구현이 가능하다. 금속층의 두께가 낮을 경우에는 별도로 알루미늄을 증착하거나 솔더 재질을 도금할 수 있다. 그리고, 외부 접속 단자로서 솔더 볼을 이용하는 것을 앞에서 소개하였으나 솔더 범프나 금 범프 등을 이용하는 것이 가능하고, 기존의 플립 칩 패드 메탈리제이션 공정을 이용하여 솔더 범프를 만들 수도 있다. 한편, 웨이퍼에서 단위 반도체 칩으로 소잉을 진행할 때 스크라이브 라인에 접하지 않도록 하여 솔더 볼이 스크라이브 라인을 따라 구동되는 절단수단에 접촉되어 솔더 볼의 접합된 상태에 손상이 발생되지 않도록 한다. 솔더 볼이 스크라이브 라인에 접하게 되면 플립 칩 공정에서 솔더 범핑 공정을 진행할 때 반도체 칩의 전극패드 쪽으로 솔더 볼을 이동시켜 형성할 수 있다.As described above, in the method of manufacturing a 3D multilayer chip package according to the present invention, a hole is formed along a scribe line which is a boundary between semiconductor chips in a wafer state, and a metal layer is formed to connect an electrode pad and a circuit pattern formed on the bottom surface of the semiconductor chip. After the separation into each unit semiconductor chip, a solder reflow process may be used to implement a three-dimensional stacked chip package. When the thickness of the metal layer is low, aluminum may be deposited separately or the solder material may be plated. In addition, although the introduction of solder balls as external connection terminals has been introduced above, it is possible to use solder bumps, gold bumps, and the like, and solder bumps may be made using a conventional flip chip pad metallization process. Meanwhile, when the sawing is performed from the wafer to the unit semiconductor chip, the solder ball is not in contact with the scribe line so that the solder ball is in contact with the cutting means driven along the scribe line, thereby preventing damage to the bonded state of the solder ball. When the solder ball contacts the scribe line, the solder ball may be formed by moving the solder ball toward the electrode pad of the semiconductor chip during the solder bumping process in the flip chip process.

이상에서와 같은 본 발명의 3차원 적층 칩 패키지 제조 방법은 단위 반도체 칩을 적층하여 구성되는 적층 칩 패키지를 제조하기 위하여 상부에 위치한 반도체 칩과 하부에 위치한 반도체 칩의 전기적인 상호 연결이 반도체 칩을 적층한 상태에서 이루어지지 않고 웨이퍼 상태에서 이루어진다. 따라서, 종래와 같이 단위 반도체 칩의 상호 연결을 위하여 글래스 튜브에 담는 작업이 필요하지 않는 등 적층 칩 패키지를 구성하기 위한 작업이 단순화되어 취급시 발생될 수 있는 손상을 감소시킬 수 있다. 그리고, 웨이퍼 상태에서 상호 연결을 위한 작업이 실시되기 때문에 각각의 반도체 칩을 적층하여 상호 연결시키는 방법보다도 수율이 향상될 수 있다.According to the method of manufacturing a 3D stacked chip package of the present invention as described above, an electrical interconnection between a semiconductor chip disposed at an upper side and a semiconductor chip positioned at a lower side is used to manufacture a laminated chip package formed by stacking unit semiconductor chips. This is not done in the stacked state but in the wafer state. Therefore, the work for constructing the laminated chip package, such as the need for the glass tube for the interconnection of the unit semiconductor chip as in the prior art is simplified to reduce the damage that may occur during handling. In addition, since the work for interconnection is performed in the wafer state, the yield can be improved compared to the method of stacking and interconnecting each semiconductor chip.

Claims (3)

⒜소정의 집적회로와 전극패드가 형성된 웨이퍼의 활성면에 상기 집적회로와 전극패드를 덮도록 보호막을 형성하는 단계, ⒝상기 웨이퍼를 단위 반도체 칩으로 분리하기 위한 스크라이브 라인을 따라 상기 웨이퍼를 관통하는 구멍을 형성하는 단계, ⒞상기 웨이퍼의 활성면에 대응되는 반대면에 상기 구멍에 인접하는 회로패턴을 형성하는 단계, ⒟상기 전극패드가 개방된 부분을 갖도록 하여 상기 구멍으로부터 상기 전극패드까지의 보호막을 제거하는 단계, ⒠상기 전극패드와 상기 회로패턴에 접속되는 금속층을 형성하는 단계, ⒡상기 전극패드의 상부에 상기 보호막으로부터 소정의 높이로 돌출되는 외부 접속 단자를 형성하는 단계, ⒢상기 스크라이브 라인을 절단하여 단위 반도체 칩으로 분리시키는 단계, 및 ⒣상기 단위 반도체 칩들을 상부에 위치한 반도체 칩의 외부 접속 단자와 하부에 위치한 반도체 칩의 회로패턴이 접속되도록 하여 적어도 두 개 이상의 단위 반도체 칩들을 적층하여 접합시키는 단계를 포함하는 것을 특징으로 하는 3차원 적층 칩 패키지 제조 방법.Forming a protective film on the active surface of the wafer on which the predetermined integrated circuit and the electrode pad are formed to cover the integrated circuit and the electrode pad, and penetrating the wafer along a scribe line for separating the wafer into unit semiconductor chips. Forming a hole; (b) forming a circuit pattern adjacent to the hole on an opposite surface corresponding to the active surface of the wafer; (b) making the electrode pad have an open portion to protect the protective film from the hole to the electrode pad; Removing the steps;, forming a metal layer connected to the electrode pad and the circuit pattern; ⒡ forming an external connection terminal projecting to a predetermined height from the passivation layer on the electrode pad, ⒢ the scribe line Cutting the chip into unit semiconductor chips, and ⒣ the unit semiconductor chips In a three-dimensional stacked chip package production method to ensure that the circuit pattern of the semiconductor chips connected in the external connection terminal and lower portions of a semiconductor chip comprising the step of bonding by lamination at least two or more units of the semiconductor chip. 제 1항에 있어서, 상기 ⒡단계는 상기 전극패드와 접합되도록 솔더 볼을 형성하는 단계인 것을 특징으로 하는 3차원 적층 칩 패키지 제조 방법.The method of claim 1, wherein the step (b) comprises forming solder balls to be bonded to the electrode pads. 제 1항에 있어서, 상기 ⒝단계는 레이저에 의해 형성하는 것을 특징으로 하는 3차원 적층 칩 패키지 제조 방법.The method of claim 1, wherein the step (b) is formed by a laser.
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