KR100967642B1 - Semiconductor chip package - Google Patents

Semiconductor chip package Download PDF

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KR100967642B1
KR100967642B1 KR1020070139651A KR20070139651A KR100967642B1 KR 100967642 B1 KR100967642 B1 KR 100967642B1 KR 1020070139651 A KR1020070139651 A KR 1020070139651A KR 20070139651 A KR20070139651 A KR 20070139651A KR 100967642 B1 KR100967642 B1 KR 100967642B1
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semiconductor chip
semiconductor
wire bonding
present
bonding
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KR1020070139651A
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KR20090071767A (en
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박초응
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주식회사 동부하이텍
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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 칩 패키지에 관한 것으로서, 반도체 칩의 측면에 와이어 본딩이 이루어지도록 반도체 기판을 소잉(sawing)함으로써 반도체 칩의 측면으로 노출되는 탑메탈에 와이어 본딩이 이루어지는 것을 특징으로 한다. 따라서 본 발명에 의하면 반도체 칩의 측면으로 와이어 본딩이 이루어질 수 있도록 본딩 위치를 변경함으로써, 와이어의 본딩 길이를 줄일 수 있게 되어 Ron 특성을 개선하였으며, 또한, 종래의 스페이서 설치 공정이 필요 없이 각 반도체 칩에 형성된 패시베이션막을 직접 맞대어 설치할 수 있으므로 반도체 칩의 간격을 줄여 사이즈를 축소할 수 있는 효과가 있다.The present invention relates to a semiconductor chip package, characterized in that wire bonding is performed on a top metal exposed to the side of the semiconductor chip by sawing the semiconductor substrate so that wire bonding is performed on the side of the semiconductor chip. Therefore, according to the present invention, by changing the bonding position so that the wire bonding can be made to the side of the semiconductor chip, it is possible to reduce the bonding length of the wire to improve the Ron characteristics, and also, each semiconductor chip without the need for a conventional spacer installation process The passivation film formed on the substrate can be directly faced to each other, thereby reducing the size of the semiconductor chip.

반도체 칩, 와이어 본딩, Ron, 소잉, 탑메탈, 하부메탈 Semiconductor Chip, Wire Bonding, Ron, Sawing, Top Metal, Bottom Metal

Description

반도체 칩 패키지{Semiconductor chip package} Semiconductor chip package

본 발명은 반도체 칩 패키지에 관한 것으로, 더욱 상세하게는 와이어의 본딩 위치를 변경하여 Ron 특성을 개선한 반도체 칩 패키지에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package having improved Ron characteristics by changing the bonding position of the wire.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다.In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 용량 증대, 즉, 메모리칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. 그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법 으로서 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 활발히 진행되고 있다.In addition, as miniaturization of electric and electronic products and high performance is required, various technologies for providing a high capacity semiconductor module have been researched and developed. As a method for providing a high capacity semiconductor module, there is an increase in the capacity of the memory chip, that is, high integration of the memory chip, which can be realized by integrating a larger number of cells in a limited space of the semiconductor chip. have. However, the high integration of such a memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, as another method for providing a high-capacity semiconductor module, research on a multi chip package has been actively conducted.

멀티 칩 패키지는 서로 다른 기능을 갖는 두 개 이상의 반도체 칩들을 하나의 패키지로 제작한 형태로서, 통상, 여러 개의 반도체 칩들을 기판 상에 단순 나열하여 패키징하는 방법, 또는, 두 개 이상의 반도체 칩들을 적층 구조로 쌓아 올려 패키징하는 방법으로 제작된다. 특히, 후자의 방법은 실장 면적을 감소시킬 수 있다는 잇점을 갖는다.A multi-chip package is a form in which two or more semiconductor chips having different functions are manufactured in one package. In general, a multi-chip package is a method of packaging a plurality of semiconductor chips by simply arranging them on a substrate, or by stacking two or more semiconductor chips. It is produced by stacking and packaging as a structure. In particular, the latter method has the advantage of reducing the mounting area.

그러나, 최근 다양한 종류의 멀티 칩 패키지가 등장하면서 그 제조 공정, 특히, 반도체 칩과 기판을 전기적으로 연결하는 본딩 와이어(bonding wire) 형성 공정이 점차 어려워지고 있다.However, with the advent of various types of multi-chip packages, a manufacturing process, in particular, a bonding wire forming process for electrically connecting a semiconductor chip and a substrate has become increasingly difficult.

이하에서는, 도 1을 참조하여, 종래의 멀티 칩 패키지의 한 종류로서 크기가 서로 다른 반도체 칩들이 적층된 멀티 칩 패키를 도시한 측면도이다.Hereinafter, referring to FIG. 1, a side view illustrating a multi-chip package in which semiconductor chips having different sizes are stacked as one type of a conventional multi-chip package.

도 1을 참조하면, 종래의 멀티 칩 패키지에서는 패키지 몸체 부분은 생략되어 있다.Referring to FIG. 1, the package body part is omitted in a conventional multichip package.

기판(10) 상에 제 1 반도체 칩(11)과 제 1 반도체 칩(11) 보다 작은 크기를 갖는 제 2 반도체 칩(12)이 실리콘 재질로 이루어진 스페이서(14)를 매개로 하여 접착제로 스택킹(stacking)된 구조이다.The first semiconductor chip 11 and the second semiconductor chip 12 having a smaller size than the first semiconductor chip 11 are stacked on the substrate 10 with an adhesive via a spacer 14 made of a silicon material. It's a stacked structure.

여기서, 제 1, 2 반도체 칩(11)(12)을 기판(10)에 전기적으로 연결시키기 위해서는 각 반도체 칩(11)(12)의 상면상에 본딩 패드(11a)(12a)을 통하여 롱 와이어 본딩(long wire bonding) 공정이 실시된다. Here, in order to electrically connect the first and second semiconductor chips 11 and 12 to the substrate 10, the long wire may be connected to the upper surface of each semiconductor chip 11 and 12 through bonding pads 11a and 12a. A long wire bonding process is performed.

미설명된 도면부호 15는 제 1 본딩 와이어이고, 16은 제 2 본딩 와이어이고, 20는 솔더볼, 22는 볼랜드를 각각 나타낸다.Unexplained reference numeral 15 is a first bonding wire, 16 is a second bonding wire, 20 is a solder ball, and 22 is a ball land, respectively.

그런데, 롱 와이어 사용시 롱 와이어의 길이 만큼의 저항값을 갖는다. 이는 도 2와 도 3의 표와 같이 와이어의 길이에 따라 Ron값에 큰 차이가 나타나는 것을 알 수 있다. 더욱이 와이어가 길어짐으로 하여 단락(short)이 유발되고 제조 수율이 저하되는 문제점이 있다.By the way, when using a long wire has a resistance value as long as the length of the long wire. This can be seen that the large difference in Ron value according to the length of the wire as shown in the table of FIG. In addition, there is a problem in that the wire is lengthened, causing short-circuit and a decrease in production yield.

따라서 본 발명에서는, 반도체 기판의 소잉으로 드러나는 반도체 칩의 측면으로 와이어 본딩이 이루어질 수 있도록 본딩 위치를 변경함으로써, 와이어의 본딩 길이를 줄일 수 있게 되어 Ron 특성을 개선한 반도체 칩 패키지를 제공하는 것을 그 목적으로 한다.Therefore, in the present invention, by changing the bonding position so that the wire bonding to the side of the semiconductor chip exposed by the sawing of the semiconductor substrate, it is possible to reduce the bonding length of the wire to provide a semiconductor chip package with improved Ron characteristics The purpose.

또한, 본 발명의 다른 목적으로는 반도체 칩의 측면으로 와이어 본딩이 이루어짐으로써 적층되는 반도체 칩의 상, 하부의 위치 바뀜이 가능하고, 이에 따라 종래의 스페이서 설치 공정이 필요 없이 각 반도체 칩에 형성된 패시베이션막을 직접 맞대어 설치할 수 있으므로 반도체 칩의 간격을 줄여 사이즈를 축소할 수 있는 반도체 칩 패키지를 제공하는 것을 그 목적으로 한다.In addition, another object of the present invention is the wire bonding to the side of the semiconductor chip is possible to change the position of the upper and lower positions of the stacked semiconductor chip, and thus passivation formed on each semiconductor chip without the need for a conventional spacer installation process It is an object of the present invention to provide a semiconductor chip package that can directly reduce the size of the semiconductor chip, thereby reducing the size of the semiconductor chip.

상기 목적을 달성하기 위하여 본 발명은, 측면이 소잉(sawing)되고, 소잉된 측면으로 노출되는 탑메탈에 와이어 본딩이 설치되는 반도체 칩을 포함하며, 반도체 칩의 저면에 절연층인 패시베이션막을 위치시키고, 다른 반도체 칩의 상면에 패시베이션막을 위치시켜서 패시베이션막이 직접 맞대어 반도체 칩이 적층되는 반도체 칩 패키지를 제공한다.In order to achieve the above object, the present invention includes a semiconductor chip having a side sawed (sawing), wire bonding is installed on the top metal exposed to the sawed side, and the passivation film which is an insulating layer on the bottom surface of the semiconductor chip and The present invention provides a semiconductor chip package in which a passivation film is placed on an upper surface of another semiconductor chip so that the passivation film is directly opposed to the semiconductor chip.

그리고 바람직하게 반도체 칩의 측면으로 들러난 탑메탈에 와이어 본딩을 위한 공간 확보를 위하여 탑메탈의 측벽 노출부위에 트렌치를 형성시키고, 이 트렌치를 통하여 노출되는 탑메탈과 하부메탈을 콘택시키도록 비아를 형성시켰다.Preferably, a trench is formed in the exposed portion of the sidewall of the top metal to secure a space for wire bonding to the top metal raised to the side of the semiconductor chip, and a via is formed to contact the top metal and the bottom metal exposed through the trench. Formed.

삭제delete

이상 설명한 바와 같이 본 발명의 반도체 칩 패키지에 따르면, 반도체 칩의 측면으로 와이어 본딩이 이루어질 수 있도록 본딩 위치를 변경함으로써, 와이어의 본딩 길이를 줄일 수 있게 되어 Ron 특성을 개선하였으며, 또한, 종래의 스페이서 설치 공정이 필요 없이 각 반도체 칩에 형성된 패시베이션막을 직접 맞대어 설치할 수 있으므로 반도체 칩의 간격을 줄여 사이즈를 축소할 수 있는 효과가 있다.As described above, according to the semiconductor chip package of the present invention, by changing the bonding position so that the wire bonding can be made to the side of the semiconductor chip, the bonding length of the wire can be reduced, thereby improving the Ron characteristic, and the conventional spacer. Since the passivation film formed on each semiconductor chip can be directly faced to each other without the installation process, the size of the semiconductor chip can be reduced by reducing the gap between the semiconductor chips.

이하 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be made based on the contents throughout the specification.

도 4는 본 발명의 실시예에 따른 반도체 칩 패키지의 측면도이고, 도 5는 본 발명의 실시예에 따른 반도체 칩 패키지의 일부 측단면도이고, 도 6은 본 발명의 실시예에 따른 반도체 칩 패키지의 사시도이다. 4 is a side view of a semiconductor chip package according to an embodiment of the present invention, FIG. 5 is a partial side cross-sectional view of a semiconductor chip package according to an embodiment of the present invention, and FIG. 6 is a view of a semiconductor chip package according to an embodiment of the present invention. Perspective view.

도 4에 도시된 반도체 칩 패키지는 패키지 몸체 부분은 생략된 것으로서, 반도체 기판(100) 상에 제 1 반도체 칩(110)과 제 2 반도체 칩(120)이 적층 구조로 설치되며, 이 제 1 반도체 칩(110)과 제 2 반도체 칩(120)을 반도체 기판(100)에 전기적으로 연결시키기 위해서는 롱 와이어 본딩(long wire bonding) 공정이 요구된다. In the semiconductor chip package shown in FIG. 4, the package body is omitted, and the first semiconductor chip 110 and the second semiconductor chip 120 are stacked on the semiconductor substrate 100, and the first semiconductor is stacked. In order to electrically connect the chip 110 and the second semiconductor chip 120 to the semiconductor substrate 100, a long wire bonding process is required.

여기서 본 발명의 특징에 따라 제 1, 2 반도체 칩(110)(120)의 측면으로 와이어 본딩이 이루어진다.In this case, wire bonding is performed to side surfaces of the first and second semiconductor chips 110 and 120 according to the present invention.

이는 반도체 기판(100)을 소잉(sawing)함으로써 제 1, 2 반도체 칩(110)(120)의 측면으로 노출되는 탑메탈(도 5에 도시:130)에 와이어 본딩(112)(122)이 이루어지게 된다.This is achieved by wire bonding 112 and 122 to the top metal (shown in FIG. 5: 130) exposed to side surfaces of the first and second semiconductor chips 110 and 120 by sawing the semiconductor substrate 100. You lose.

참고로, 웨이퍼 소잉 공정은, 반도체 제조 공정 중 웨이퍼 제조 공정으로 불리는 전(前)공정과 어셈블리(assembly) 공정으로 불리는 후(後)공정 사이에 위치하는 공정으로서, 다수의 반도체 칩이 형성된 웨이퍼를 절단하여 개개의 반도체 칩으로 분리시키는 공정을 말한다. 이때 일반적인 웨이퍼 소잉 공정은 고속으로 회전하는 블레이드(blade)를 이용, 웨이퍼 상에 형성된 다수의 반도체 칩 사이의 스크라이브 레인(scribe lane)을 따라 절단을 수행함으로써 이루어진다.For reference, a wafer sawing process is a process located between a pre-process called a wafer fabrication process and a post-process called an assembly process in a semiconductor manufacturing process. The process of cutting | disconnection and separating into individual semiconductor chips. In this case, a general wafer sawing process is performed by cutting along a scribe lane between a plurality of semiconductor chips formed on a wafer by using a blade rotating at a high speed.

일반적으로 웨이퍼 레벨의 칩 사이즈 패키지는 웨이퍼 상태에서 반제품으로 조립한 다음, 최종적으로 소잉하여 개개의 칩으로 분리함으로써 패키지의 제조도 완료하는 패키지를 말한다.Generally, wafer-level chip size packages are packages that are assembled into semi-finished products in a wafer state and then finally sawed and separated into individual chips to complete the manufacture of the package.

이와 같이 다수의 반도체 칩 사이의 스크라이브 레인(scribe lane)을 따라 절단을 수행하고, 이에 따라 절단된 제 1, 2 반도체 칩(110)(120)의 측면으로 노출된 탑메탈(130)에 와이어 본딩(112)(122)이 이루어진다.As such, cutting is performed along a scribe lane between the plurality of semiconductor chips, and wire bonding is performed on the top metal 130 exposed to the side surfaces of the first and second semiconductor chips 110 and 120 that are cut accordingly. 112, 122 is made.

한편, 위와 같이 제 1, 2 반도체 칩(110)(120)의 측면으로 와이어 본딩(112)(122)을 하기 위해서는 메탈 콘택(contact) 부분의 일정한 접촉 면적을 필요로 하며, 이는 Fab 공정의 메탈 두께에 의해 결정될 수 있다. 그러나, Fab 공정에서 메탈의 두께는 30000Å 정도로 와이어 본딩(112)(122)이 이루어지기에는 충분치 않을 수 있다.Meanwhile, in order to wire bond 112 and 122 to the side surfaces of the first and second semiconductor chips 110 and 120 as described above, a constant contact area of a metal contact portion is required, which is a metal of a Fab process. Can be determined by thickness. However, in the Fab process, the thickness of the metal may not be sufficient for the wire bonding 112 and 122 to be made to about 30000 mm 3.

이에 따라 도 5에 도시된 바와 같이, 각 제 1, 2 반도체 칩(110)(120)의 측면으로 일정 깊이의 트렌치(150)를 형성하여 탑메탈(130)과 하부메탈(132)을 노출시키게 된다.Accordingly, as shown in FIG. 5, the trench 150 having a predetermined depth is formed on the side surfaces of the first and second semiconductor chips 110 and 120 to expose the top metal 130 and the lower metal 132. do.

트렌치(150)는 레이저 가공 등으로 가능하다.The trench 150 may be formed by laser processing or the like.

그리고 노출된 탑메탈(130)과 하부메탈(132)에 노출형 비아(152)를 형성시키고 이 모두를 스택(stack) 형태로 형성함으로써 와이어 본딩(112)(122)의 콘택이 원활하게 이루어질 수 있는 구성을 가진다.In addition, the wire bonding 112 and 122 may be smoothly contacted by forming the exposed via 152 on the exposed top metal 130 and the lower metal 132 and forming both of them in a stack form. Has a configuration.

미설명된 도면부호 140은 솔더볼이고, 142는 볼랜드를 각각 나타낸다.Unexplained reference numeral 140 denotes solder balls, and 142 denotes ball lands, respectively.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 설명하기로 한 다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

먼저, 스크라이브 레인을 따라 소잉 블레이드(미도시)로 절단하여 개개의 칩으로 분리하고, 이와 같이 분리된 제 1 반도체 칩(110)과 제 2 반도체 칩(120)을 부착하여 하나의 패키지로 완성한다.First, a saw blade (not shown) is cut along the scribe lane and separated into individual chips, and the first semiconductor chip 110 and the second semiconductor chip 120 separated as described above are attached to each other to form a single package. .

이때, 제 1 반도체 칩(110)과 제 2 반도체 칩(120)의 측면에 소잉 공정으로 드러난 탑메탈(130)에 와이어 본딩(112)(122)을 실시하게 된다.In this case, wire bonding 112 and 122 may be performed on the top metal 130 exposed by the sawing process on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120.

여기서 탑메탈(130)만으로 와어어 본딩(112)(122)의 콘택이 어려울 경우 제 1 반도체 칩(110)과 제 2 반도체 칩(120)의 측면에 트렌치(150) 형태로 홀을 형성하고, 이 트렌치(150)로 드러난 탑메탈(130)과 하부메탈(132)을 연결하는 비아(152)를 형성하여 스택 형태로 형성시키며, 이 스택 부분을 통한 콘택 면적의 확대로 와이어 본딩(112)(122)을 보다 원활히 실시할 수 있다.In this case, when the contact of the wire bonding 112 and 122 is difficult using only the top metal 130, holes are formed in the trench 150 on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120. Vias 152 connecting the top metal 130 and the lower metal 132 exposed by the trench 150 are formed to form a stack, and the wire bonding 112 is formed by expanding the contact area through the stack portion. 122) can be carried out more smoothly.

다음과 같이 제 1 반도체 칩(110)과 제 2 반도체 칩(120)의 측면으로 와이어본딩(112)(122)이 가능하여 짐으로 하여 종래에 제 1 반도체 칩과 제 2 반도체 칩의 적층시 필요시 되는 스페이서의 사용이 필요 없게 되었다.Wire bonding 112 and 122 are possible on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120 as follows, so that it is necessary to stack the first semiconductor chip and the second semiconductor chip. There is no need for the use of spacers.

즉, 제 1 반도체 칩(110)과 제 2 반도체 칩(120)은 각각 금속 층간 절연층과 단위 패턴 단위들로 이루어진 복수의 금속배선이 형성된 반도체 기판(100)을 제공하게 된다.That is, the first semiconductor chip 110 and the second semiconductor chip 120 each provide a semiconductor substrate 100 having a plurality of metal wirings formed of a metal interlayer insulating layer and unit pattern units.

이때, 각 제 1 반도체 칩(110)과 제 2 반도체 칩(120)에서 최상의 탑메탈(130)에는 패시베이션막(114)(124)이 형성된다. 종래에는 이 패시베이션막을 개방시켜 그 부분에 알루미늄과 같은 금속으로 본딩 패드를 구성하고 이 본딩 패드에 와이어 본딩이 이루어졌으나, 본 발명에서는 반도체 칩의 상부면에 본딩 패드의 구성이 필요 없으므로 제 1 반도체 칩(110)과 제 2 반도체 칩(120)에 각각 형성된 패시베이션막(114)(124)을 마주하도록 위치시켜서 이 패시베이션막(114)(124)을 절연층으로 하여 두 반도체 칩간의 직접적인 접착이 가능하다.In this case, passivation layers 114 and 124 are formed on the top metals 130 of the first semiconductor chip 110 and the second semiconductor chip 120. Conventionally, the passivation film is opened to form a bonding pad made of a metal such as aluminum at the portion thereof, and wire bonding is performed on the bonding pad. However, in the present invention, since the bonding pad is not formed on the upper surface of the semiconductor chip, the first semiconductor chip is not required. The passivation films 114 and 124 respectively formed on the 110 and second semiconductor chips 120 are disposed to face each other, and the passivation films 114 and 124 are used as an insulating layer to directly bond the two semiconductor chips. .

이로서 전체적인 패키지의 사이즈를 줄일 수 있다. This can reduce the overall size of the package.

따라서, 본 발명은 롱 와이어 사용시 유발되는 와이어 스위핑(sweeping) 등의 문제를 방지할 수 있는 바, 제품의 신뢰성 및 생산성을 개선할 수 있으며, 와이어 본딩의 길이가 짧아짐에 따라 패키지의 전기적 특성을 향상시킬 수 있다.Therefore, the present invention can prevent problems such as wire sweeping caused by using long wires, and can improve product reliability and productivity, and improve the electrical characteristics of a package as the length of wire bonding becomes short. You can.

또한, 본 발명에서는 제 1, 2 반도체 칩(110)(120)의 측면으로 와이어 본딩이 이루어짐으로써 적층되는 제 1, 2 반도체 칩(110)(120)의 적층 간격을 줄여 전체적인 패키지의 사이즈를 축소할 수 있게 되었다.In addition, in the present invention, wire bonding is performed on the side surfaces of the first and second semiconductor chips 110 and 120 to reduce the stacking interval of the first and second semiconductor chips 110 and 120 to be stacked, thereby reducing the overall size of the package. I can do it.

이상에서 설명한 것은 본 발명에 따른 반도체 칩 패키지는 하나의 바람직한 실시예에 불과한 것으로서, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와 같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다.As described above, the semiconductor chip package according to the present invention is only one preferred embodiment, and the present invention is not limited to the above-described embodiments, and the present invention is not limited to the scope of the present invention as claimed in the following claims. Without departing from the scope of the present invention, those skilled in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

도 1은 종래의 멀티 칩 패키지의 한 종류를 도시한 측면도이고,1 is a side view showing one type of a conventional multi-chip package,

도 2 내지 도 3은 종래 기술에 따라 와이어의 길이에 따라 Ron의 차이점을 보여주는 도표이고, 2 to 3 is a diagram showing the difference between Ron according to the length of the wire according to the prior art,

도 4는 본 발명의 실시예에 따른 반도체 칩 패키지의 측면도이고,4 is a side view of a semiconductor chip package according to an embodiment of the present invention;

도 5는 본 발명의 실시예에 따른 반도체 칩 패키지의 일부 측단면도이고,5 is a partial side cross-sectional view of a semiconductor chip package according to an embodiment of the present invention,

도 6은 본 발명의 실시예에 따른 반도체 칩 패키지의 사시도이다. 6 is a perspective view of a semiconductor chip package according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 110, 120 : 제 1, 2 반도체 칩100: semiconductor substrate 110, 120: first and second semiconductor chips

112, 122 : 와이어 본딩 130 : 탑메탈112, 122: wire bonding 130: top metal

132 : 하부메탈 140 : 솔더볼132: lower metal 140: solder ball

142 : 볼랜드 150 : 트렌치142: Borland 150: trench

152 : 비아152: Via

Claims (4)

측면이 소잉(sawing)되고, 소잉된 측면으로 노출되는 각각의 탑메탈에 와이어 본딩이 설치되는 제 1 및 제 2 반도체 칩을 포함하며,A first and a second semiconductor chip having a side sawed and wire bonding installed on each top metal exposed to the sawed side, 상기 제 1 반도체 칩의 저면에 절연층인 패시베이션막을 위치시키고, 상기 제 2 반도체 칩의 상면에 상기 패시베이션막을 위치시켜서 상기 패시베이션막이 직접 맞대어 상기 반도체 칩이 적층되고,Placing the passivation film as an insulating layer on the bottom surface of the first semiconductor chip, placing the passivation film on the upper surface of the second semiconductor chip, and directly stacking the semiconductor chip, 상기 반도체 칩들의 측면으로 드러난 상기 각각의 탑메탈에 상기 와이어 본딩을 위한 공간 확보를 위하여 상기 탑메탈의 측벽 노출부위에 트렌치를 형성시킨 반도체 칩 패키지.And forming a trench in the sidewall exposed portion of the top metal to secure a space for the wire bonding on each top metal exposed to the sides of the semiconductor chips. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 트렌치를 통하여 노출되는 상기 탑메탈과 하부메탈을 콘택시키도록 비아를 형성시킨 반도체 칩 패키지.And a via formed to contact the top metal and the bottom metal exposed through the trench. 삭제delete
KR1020070139651A 2007-12-28 2007-12-28 Semiconductor chip package KR100967642B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017011049A3 (en) * 2015-04-28 2017-02-16 Invensas Corporation Coupling of side surface contacts to a circuit platform

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010018694A (en) * 1999-08-21 2001-03-15 윤종용 Manufacturing method for three demensional stack chip package
JP2004342883A (en) * 2003-05-16 2004-12-02 Oki Electric Ind Co Ltd Semiconductor device and its fabricating process
KR20060051783A (en) * 2004-09-30 2006-05-19 가부시끼가이샤 도시바 Semiconductor device and manufacture method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010018694A (en) * 1999-08-21 2001-03-15 윤종용 Manufacturing method for three demensional stack chip package
JP2004342883A (en) * 2003-05-16 2004-12-02 Oki Electric Ind Co Ltd Semiconductor device and its fabricating process
KR20060051783A (en) * 2004-09-30 2006-05-19 가부시끼가이샤 도시바 Semiconductor device and manufacture method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017011049A3 (en) * 2015-04-28 2017-02-16 Invensas Corporation Coupling of side surface contacts to a circuit platform

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