CN218385219U

CN218385219U - Semiconductor device with a plurality of transistors

Info

Publication number: CN218385219U
Application number: CN202222076476.6U
Authority: CN
Inventors: 凯·史提芬·艾斯格; 博恩·卡尔·艾皮特; 颜尤龙
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2022-08-08
Filing date: 2022-08-08
Publication date: 2023-01-24
Anticipated expiration: 2032-08-08

Abstract

The present application provides a semiconductor device. The present application uses a thin or ultra-thin coreless substrate instead of a conventional substrate to form a dual-sided SiP package based on a coreless substrate by encapsulating electronic components on both sides of the coreless substrate. The thickness of the coreless substrate is usually less than 100 μm, and the minimum thickness can be less than 50 μm, which is obviously lower than that of the traditional cored substrate, so that the total thickness of the double-sided SIP packaging can be effectively reduced.

Description

Semiconductor device with a plurality of transistors

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor device.

Background

In the fields of 3C (Computer, communication, consumer electronics, computer, communication and consumer electronics) and automobiles, system In Package (SiP) is increasingly In demand. Compared with single-sided SiP, double-sided SiP packaging can reduce module size and increase power consumption, thereby achieving better performance. However, current double-sided SiP packages have difficulty reducing the overall thickness because the intermediate substrate requires a certain thickness, typically greater than 100 μm, to provide the load-bearing requirements.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides a semiconductor device.

In a first aspect, the present disclosure provides a semiconductor device comprising: the circuit structure is provided with a first surface and a second surface opposite to the first surface, the first surface is provided with a first circuit, the second surface is provided with a second circuit, the first circuit is an embedded circuit, and the second circuit is a non-embedded circuit; the first connecting piece is arranged on the first surface and is configured to be connected with an external device.

In some optional embodiments, the circuit structure further comprises: a dielectric layer encapsulating the first line; wherein a bottom surface of the first line is substantially flush with a bottom surface of the dielectric layer.

In some optional embodiments, the circuit structure further comprises: the protective layer partially covers the second circuit; wherein a top surface of the protective layer is higher than a top surface of the second line.

In some optional embodiments, the semiconductor device further comprises: the first electronic element is arranged on the first surface and is electrically connected with the first circuit through a plurality of first conductive bumps; the second electronic element is arranged on the second surface and is electrically connected with the second circuit through a plurality of second conductive bumps; wherein the pitch of the first conductive bumps is smaller than the pitch of the second conductive bumps.

In some optional embodiments, the semiconductor device further comprises: and the second connecting piece is arranged on the second surface and is configured to be connected with an external device.

In some optional embodiments, the line structure has a first opening therethrough, and the semiconductor device further includes: the first electronic element is arranged on the first surface and covers the first opening; and a first conductive member extending through the first opening to electrically connect the first electronic component to the second line.

In some optional embodiments, the semiconductor device further comprises: and the second electronic element is arranged on the second surface, covers the first opening and is electrically connected with the second circuit.

In some optional embodiments, the line structure further has a second opening therethrough, and the semiconductor device further includes: a third electronic element arranged on the first surface and stacked on the first electronic element; and a second conductive member extending through the second opening to electrically connect the third electronic component to the second wiring.

In some optional embodiments, the line structure has a first opening therethrough, and the semiconductor device further includes: and the first electronic element is arranged in the first opening and is electrically connected with the second circuit.

In some optional embodiments, the semiconductor device further comprises: the second electronic element is arranged on the second surface, covers the first opening and the first electronic element and is electrically connected with the second circuit; wherein the first electronic component is electrically connected to the second electronic component.

In some optional embodiments, the semiconductor device further comprises: and the third electronic element is arranged on the first surface, covers the first opening and the first electronic element and is electrically connected with the first circuit.

In some alternative embodiments, the wiring structure does not include a core layer.

In order to solve the problem that the total thickness of the existing double-sided SiP package is difficult to reduce, the application provides a semiconductor device. The present application uses a thin or ultra-thin coreless substrate (thickness less than 100 μm) instead of the conventional substrate, the coreless substrate does not include a core layer, and the circuit structure has a feature that the circuit on one side surface is an embedded circuit and the circuit on the other side surface is a non-embedded circuit due to the process. The application can form double-sided SiP packaging based on the coreless substrate by packaging the electronic elements on two sides of the coreless substrate. The thickness of the coreless substrate is usually less than 100 μm, and the minimum thickness can be less than 50 μm, which is obviously lower than that of the traditional cored substrate, so that the total thickness of the double-sided SIP packaging can be effectively reduced. The manufacturing process of the coreless substrate can depend on the manufacture of the auxiliary carrier plate, namely, the carrier plate can be used for providing mechanical support during the assembling and packaging process of the first surface of the coreless substrate, and the assembling and packaging process can be carried out on the second surface of the coreless substrate after the carrier plate is stripped, so that the electronic element can be packaged on two surfaces of the coreless substrate, and the technical problems that a thin or ultrathin substrate (the thickness is less than 100 mu m) is easy to bend, the bearing force is insufficient, the processing is difficult in the assembling process and the like can be solved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1A is a schematic longitudinal sectional structure of one embodiment 1A of a semiconductor device according to the present application;

fig. 1B is a schematic longitudinal sectional structure of one embodiment 1B of a semiconductor device according to the present application;

fig. 1C is a schematic longitudinal sectional structure of one embodiment 1C of a semiconductor device according to the present application;

fig. 2A is a schematic longitudinal cross-sectional structure of one embodiment 2A of a semiconductor device according to the present application;

fig. 2B is a schematic longitudinal cross-sectional structure of one embodiment 2B of a semiconductor device according to the present application;

fig. 2C is a schematic longitudinal cross-sectional structure of one embodiment 2C of a semiconductor device according to the present application;

fig. 2D is a schematic longitudinal cross-sectional structure of one embodiment 2D of a semiconductor device according to the present application;

fig. 2E is a schematic longitudinal cross-sectional structure of one embodiment 2E of a semiconductor device according to the present application;

fig. 3A is a schematic longitudinal cross-sectional structure of one embodiment 3A of a semiconductor device according to the present application;

fig. 3B is a schematic longitudinal cross-sectional structure of one embodiment 3B of a semiconductor device according to the present application;

FIGS. 4A-4K are schematic diagrams illustrating, respectively, the steps of fabricating an embodiment of a semiconductor device of the present application;

FIGS. 5A-5H are schematic diagrams illustrating steps, respectively, in the fabrication of another embodiment of a semiconductor device of the present application;

fig. 6A to 6L are schematic views of manufacturing steps of still another embodiment of the semiconductor device of the present application, respectively.

Reference numerals/symbol description:

10-a line structure; 101-a first surface; 102-a second surface; 11-a first line; 12-a second line; 13-a dielectric layer; 14-a protective layer; 15-a first opening; 16-a second opening; 21-a first connector; 22-a second connector; 23-solder balls; 31-a first electronic component; 311-first conductive bump; 32-a second electronic component; 321-a second conductive bump; 33-passive devices; 34-a bonding wire; 35-a first electrically conductive member; 36-a third electronic component; 361-third conductive bump; 37-a fourth electronic component; 371-fourth conductive bumps; 38-through silicon vias; 39-a second electrically conductive member; 41-a first encapsulant; 42-a second encapsulant; 43-a shielding layer; 51-a first carrier plate; 52-a second carrier; 60-external devices; 61-outer wiring layer; 62-outer packaging material; 63-external electronic components.

Detailed Description

The following description of the embodiments of the present application will be provided with reference to the accompanying drawings and examples, and those skilled in the art will readily understand the technical problems and effects that are solved by the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be readily understood that the meaning of "in.. On," "over,", and "above" in this application should be interpreted in the broadest sense such that "in.. On" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

The term "layer" as used herein refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a lesser extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure or therebetween. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may be of the same or different materials.

The term "substrate" as used herein refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that the structures, proportions, sizes, and other elements shown in the drawings are only used for understanding and reading the contents of the specification, and are not used for limiting the conditions under which the present application can be implemented, so they do not have the technical significance, and any structural modifications, changes in proportion, or adjustments of sizes, which do not affect the efficacy and achievement of the purposes of the present application, shall still fall within the scope of the technical content disclosed in the present application. In addition, the terms "above", "first", "second" and "a" used in the present specification are used for the sake of clarity only, and are not intended to limit the scope of the present application, and changes and modifications of the relative relationship thereof are also considered to be the scope of the present application without substantial technical changes.

It should be further noted that, in the embodiments of the present application, the corresponding longitudinal section may be a section corresponding to a front view direction, the transverse section may be a section corresponding to a right view direction, and the horizontal section may be a section corresponding to an upper view direction.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 1A, fig. 1A is a schematic longitudinal sectional structure of one embodiment 1A of a semiconductor device according to the present application. As shown in fig. 1A, a semiconductor device 1A of the present application includes:

a circuit structure 10 having a first surface 101 and a second surface 102 opposite to the first surface 101, the first surface 101 having a first circuit 11, the second surface 102 having a second circuit 12, the first circuit 11 being an embedded circuit, the second circuit 12 being a non-embedded circuit;

the first connector 21 is disposed on the first surface 101 and configured to connect to an external device.

Here, the wiring structure 10 is a thin substrate or an ultra-thin substrate, which has a thickness of less than 100 μm, and a minimum thickness of less than 50 μm. The circuit structure 10 has the following features: the first traces 11 on the first surface 101 are buried traces, and the second traces 12 on the second surface 102 are non-buried traces, which is a feature of the coreless substrate for manufacturing reasons. The coreless substrate does not include a core layer, and is usually formed on a carrier by a lamination process, so that the coreless substrate has the above-mentioned features.

In some alternative embodiments, the wiring structure 10 does not include a core layer, nor does it include fiberglass.

In some alternative embodiments, the circuit structure 10 further includes a dielectric layer 13, and the dielectric layer 13 is located between the layers of the circuit structure 10 as an insulating isolation layer. Here, the dielectric layer 13 encapsulates the first wire 11, or the first wire 11 is embedded in the dielectric layer 13, and the bottom surface of the first wire 11 is substantially flush with the bottom surface of the dielectric layer 13. The second line 12 is a non-buried line, i.e., protrudes above the dielectric layer 13.

In some alternative embodiments, the circuit structure 10 further comprises: a protective layer 14 partially covering the second wiring 12; wherein the top surface of the protection layer 14 is higher than the top surface of the second wire 12, i.e. the thickness of the protection layer 14 is larger than the thickness of the second wire 12. The second line 12 is partially exposed out of the protective layer 14 to facilitate connection of the components. Here, the material of the protective layer 14 includes, but is not limited to, solder resist material such as green oil.

In some alternative embodiments, the wiring structure 10 further comprises at least one through hole, buried hole or blind hole to realize the wiring connection. It should be noted that the size or direction of the through hole, buried hole or blind hole is not particularly limited. If through holes, buried holes or blind holes are provided, the through holes, buried holes or blind holes may be filled with or contain a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

In some optional embodiments, the semiconductor device 1a of the present application further includes: a first electronic element 31 disposed on the first surface 101 and electrically connected to the first line 11; and a second electronic element 32 disposed on the second surface 102 and electrically connected to the second circuit 12. And optionally, may also include: a first encapsulant 41 disposed on the first surface 101 and encapsulating the first electronic component 31 therein; the second encapsulant 42 is disposed on the second surface 102, and encapsulates the second electronic element 32 therein. Thereby forming a coreless substrate based dual-sided SiP package.

Here, the first electronic element 31 and the second electronic element 32 may be bare chips (Die) that implement various functions, for example, logic chips that implement logic operations or memory chips that implement data storage.

Here, the first and

second potting materials

41 and 42 are formed of a Molding Compound (Molding Compound). Examples of the molding material include Epoxy resin (Epoxy resin), filler (Filler), catalyst (Catalyst), pigment (Pigment), release Agent (Release Agent), flame Retardant (Flame Retardant), coupling Agent (Coupling Agent), hardener (hardner), low Stress absorbent (Low Stress absorbent), adhesion Promoter (Adhesion Promoter), ion trap (Ion Trapping Agent), and the like.

In some optional embodiments, at least one passive device 33 may be further included, disposed on the first surface 101 and/or the second surface 102, electrically connected to the first wire 11 and/or the second wire 12, and encapsulated by the first encapsulant 41 and/or the second encapsulant 42. The passive components 33 may for example comprise capacitors or inductors.

In some alternative embodiments, the active surface of the first electronic component 31 faces the first surface 101 and is electrically connected to the first circuit 11 through a plurality of first conductive bumps 311; the active surface of the second electronic component 32 faces the second surface 102 and is electrically connected to the second wire 12 through a plurality of second conductive bumps 321. Optionally, the distance between the first conductive bumps 311 is smaller than the distance between the second conductive bumps 321, so as to realize a high-density structure on one side of the circuit structure 10 and a low-density structure on the other side.

In some alternative embodiments, the first connection member 21 includes, but is not limited to, a conductive pillar, such as a plated copper pillar. Here, the root of the first connector 21 is electrically connected to the first wiring 11, and the end is exposed from the first encapsulant 41 to facilitate connection to an external device. And further, a solder ball 23 may be connected to an end of the first connector 21 so as to electrically connect an external device through the solder ball 23.

In order to solve the problem that the total thickness of the existing double-sided SiP package is difficult to reduce, the present application proposes a semiconductor device 1a. The present application uses the wiring structure 10 instead of a conventional substrate, the wiring structure 10 being a thin or ultra-thin coreless substrate (thickness less than 100 μm). By encapsulating the first electronic component 31 and the second electronic component 32 on both sides of the circuit structure 10, a coreless substrate based double-sided SiP package can be formed. Since the thickness of the coreless substrate is usually less than 100 μm and can be less than 50 μm at minimum, which is significantly lower than that of the traditional cored substrate, the total thickness of the double-sided SIP package can be effectively reduced.

The present application can rely on the manufacturing of the auxiliary carrier, that is, the carrier can be used to provide mechanical support during the assembly and packaging process on the first surface 101 of the circuit structure 10, and the assembly and packaging process can be performed on the second surface 102 of the circuit structure after the carrier is peeled off, so as to realize the assembly and packaging process on both sides of the circuit structure 10, thereby solving the technical problem that the thin or ultra-thin substrate (with a thickness less than 100 μm) cannot be used in the dual-sided SIP package due to easy bending, insufficient bearing force, difficult handling during the assembly process, etc.

In addition, in the current double-sided SiP package based on the common substrate, if a laser drilling process or a mechanical drilling process is used to punch a molding layer to form Through Molding Vias (TMVs) or solder balls are stacked to realize signal transmission, the signal path pitch can be reduced to compress the occupied space of the chip at the bottom of the package, but the throughput of the TMVs or the stacked solder balls in the production is very low, and the production efficiency is not high.

In some embodiments of the present application, pads are formed to connect the solder balls 23 by using electroplated copper pillars as the first electrical connections 21 (the dielectric layer is exposed by grinding) instead of TMV. The electroplated copper columns are used as the electric connecting pieces to achieve signal transmission, fine spacing is achieved, the throughput is higher compared with TMV or stacked solder balls, and production efficiency is improved.

Referring to fig. 1B, fig. 1B is a schematic longitudinal sectional structure of one embodiment 1B of a semiconductor device according to the present application. The semiconductor device 1B shown in fig. 1B is similar to the semiconductor device 1A shown in fig. 1A except that:

in the semiconductor device 1b, the active surface of the second electronic component 32 faces away from the second surface 102, and the second electronic component 32 is electrically connected to the second line 12 through the bonding wire 34.

Referring to fig. 1C, fig. 1C is a schematic longitudinal sectional structure of one embodiment 1C of a semiconductor device according to the present application. The semiconductor device 1C shown in fig. 1C is similar to the semiconductor device 1A shown in fig. 1A except that:

the semiconductor device 1c further includes: and a second connector 22 disposed on the second surface 102 and configured to connect to an external device. The second connecting member 22 includes, but is not limited to, a conductive pillar, such as a plated copper pillar. Here, the root portion of the second connector 22 is electrically connected to the second wire 12, and the end portion is exposed from the second encapsulant 42 to facilitate connection with an external device. And optionally, the end of the second connector 22 may be connected with a solder ball 23, and may be electrically connected to an external device through the solder ball 23.

In some alternative embodiments, the semiconductor device 1c further includes: the packaged external devices 60 are stacked. For example, the external device 60 may be stacked and packaged on the surface of the second packaging material 42 and electrically connected to the second connecting member 22 through the solder balls 23, the external device 60 may also be stacked and packaged on the surface of the first packaging material 41 and electrically connected to the first connecting member 21 through the solder balls 23, or the external device 60 may also have two external devices, which are stacked and packaged on the surfaces of the first packaging material 41 and the second packaging material 42 respectively.

Among them, the external device 60 may include: an external wiring layer 61, an external electronic component 63 provided on the external wiring layer 61, and an external packaging material 62 packaging the external electronic component 63. The external electronic component 63 may be electrically connected to the external circuit layer 61 through a bonding wire, or may be electrically connected to the external circuit layer 61 through a conductive bump.

As described above, the present application may provide an ultra-thin stacked System-In-package (SiPoP) by plating copper posts on one side of a coreless substrate, and may also provide an ultra-thin double-sided stacked System-In-package (SiPoP) by plating copper posts on both sides of the coreless substrate.

Referring to fig. 2A, fig. 2A is a schematic longitudinal sectional structure of one embodiment 2A of a semiconductor device according to the present application. The semiconductor device 2A shown in fig. 2A is similar to the semiconductor device 1A shown in fig. 1A except that:

in the semiconductor device 2a, the line structure 10 has a first opening 15 therethrough; the first electronic element 31 is disposed on the first surface 101 and covers the first opening 15; a first conductive member 35, extending through the first opening 15, electrically connects the first electronic component 31 to the second wire 12. Here, the active surface of the first electronic component 31 faces the opening 15. Here, the first conductive member 35 includes, but is not limited to, a bonding wire.

In some optional embodiments, the semiconductor device 2a further comprises: the second electronic element 32 is disposed on the second surface 102, covers the first opening 15, and is electrically connected to the second circuit 12. Optionally, the active surface of the second electronic component 32 faces the second surface and is electrically connected to the second line 12 through a plurality of second conductive bumps 321.

In some optional embodiments, the semiconductor device 2a further comprises: the third electronic element 36 is disposed on the first surface 101, stacked under the first electronic element 31, and covers the first electronic element 31. Optionally, the third electronic element 36 has a larger width/area than the first electronic element, and is electrically connected to the first line 11 through a plurality of third conductive bumps 361.

The semiconductor device 2a of the present application, by providing the first opening 15, makes the first electronic component 31 disposed on the first surface 101 electrically connected to the second line 12 of the second surface 102 through the first conductive member 35, and since the first conductive bump 311 (see fig. 1A) is not necessary, the distance between the first electronic component 31 and the first surface 101 is reduced, which helps to further reduce the total thickness of the double-sided SIP package.

Referring to fig. 2B, fig. 2B is a schematic longitudinal sectional structure of one embodiment 2B of a semiconductor device according to the present application. The semiconductor device 2B shown in fig. 2B is similar to the semiconductor device 2A shown in fig. 2A, except that:

the semiconductor device 2b further includes: the fourth electronic element 37 is disposed on the second surface 102 and stacked on the second electronic element 32. Optionally, the fourth electronic element 37 is electrically connected to the second line 12 through a bonding wire 34. Optionally, the fourth electronic component 37 has a smaller width/area than the second electronic component 32.

Referring to fig. 2C, fig. 2C is a schematic longitudinal sectional structure of one embodiment 2C of a semiconductor device according to the present application. The semiconductor device 2C shown in fig. 2C is similar to the semiconductor device 2A shown in fig. 2A, except that:

in the semiconductor device 2c, the line structure 10 further has at least one second opening 16 therethrough.

The semiconductor device 2c further includes: a third electronic component 36 and a second conductive member 39; the third electronic element 36 is disposed on the first surface 101, stacked below the first electronic element 31, and covers the first electronic element 31, and the width/area of the third electronic element 36 is greater than that of the first electronic element 31; a second electrically conductive member 39 extends through second opening 16 to electrically connect third electrical component 36 to second circuit 12. Here, the second conductive member 39 includes, but is not limited to, a bonding wire.

The semiconductor device 2c of the present application, by providing the second opening 16, enables the third electronic component 36 disposed on the first surface 101 to be electrically connected to the second circuit 12 on the second surface 102 through the second conductive member 39, which helps to further reduce the total thickness of the double-sided SIP package.

Referring to fig. 2D, fig. 2D is a schematic longitudinal sectional structure of one embodiment 2D of a semiconductor device according to the present application. The semiconductor device 2D shown in fig. 2D is similar to the semiconductor device 2B shown in fig. 2B, except that:

in the semiconductor device 2d, a Through Silicon Via (TSV) 38 is disposed on the second electronic element 32, and the TSV 38 is electrically connected to the second circuit 12. The fourth electronic element 37 stacked on the second electronic element 32 may be flip-chip mounted, and electrically connected to the through-silicon via 38 through a plurality of fourth conductive bumps 371, and further electrically connected to the second line 12 through the through-silicon via 38.

In some alternative embodiments, since the through-silicon vias 38 occupy the space of the second electronic element 32, so that the number of the second conductive bumps 321 is reduced, the second electronic element 32 may be connected to the second wire 12 by the bonding wires 34 in addition to the second wire 12 connected by the second conductive bumps 321.

Referring to fig. 2E, fig. 2E is a schematic longitudinal sectional structure of one embodiment 2E of a semiconductor device according to the present application. The semiconductor device 2E shown in fig. 2E is similar to the semiconductor device 2B shown in fig. 2B, except that:

in the semiconductor device 2e, further included is: and a shielding layer 43 covering the upper surface and the side surface of the semiconductor device 2e for shielding electromagnetic wave interference.

Referring to fig. 3A, fig. 3A is a schematic longitudinal sectional structure of one embodiment 3A of a semiconductor device according to the present application. The semiconductor device 3A shown in fig. 3A is similar to the semiconductor device 2A shown in fig. 2A except that:

in the semiconductor device 3a, the first electronic component 31 is directly disposed within the first opening 15, thereby further reducing the overall thickness of the dual-sided SIP package. Here, the first electronic component 31 may be electrically connected to the first wiring 11, and may also be electrically connected to the second wiring 12.

In some alternative embodiments, the semiconductor device 3a further includes: a second electronic element 32 disposed on the second surface 102, covering the first opening 15 and the first electronic element 31, and electrically connected to the second circuit 12 through a plurality of second conductive bumps 321; optionally, the active surface of the first electronic component 31 faces the active surface of the second electronic component 32, and is electrically connected to the second electronic component 32 through the plurality of second conductive bumps 321, and is electrically connected to the second trace 12 through the second electronic component 32.

In some optional embodiments, the semiconductor device 3a further comprises: the third electronic element 36 is disposed on the first surface 101, covers the first opening 15 and the first electronic element 31, and is electrically connected to the first circuit 11 through a plurality of third conductive bumps 361.

Referring to fig. 3B, fig. 3B is a schematic longitudinal cross-sectional structure of one embodiment 3B of a semiconductor device according to the present application. The semiconductor device 3B shown in fig. 3B is similar to the semiconductor device 3A shown in fig. 3A, except that:

the semiconductor device 3b further includes: the fourth electronic element 37 is stacked on the second electronic element 32. Here, the fourth electronic element 37 is electrically connected to the second wiring 12 through the bonding wire 34. Optionally, the fourth electronic component 37 has a smaller width/area than the second electronic component 32.

Referring to fig. 4A-4K, fig. 4A-4K are schematic diagrams of fabrication steps, respectively, of one embodiment of a semiconductor device of the present application.

Referring to fig. 4A, a first carrier 51 is provided, and the first carrier 51 may be, for example, a double-sided copper-clad plate or a single-sided copper-clad plate. In this embodiment, the first carrier 51 is used as a carrier, and a semiconductor device is manufactured on the first carrier, optionally, the semiconductor device may be manufactured on one side surface of the first carrier, or the semiconductor device may be manufactured on both side surfaces of the first carrier simultaneously, only a manufacturing process of one side is described herein, and a manufacturing process of the other side is similar and will not be described in detail. First, the first wiring 11 is formed on the copper layer of one surface of the first carrier plate 51.

Referring to fig. 4B, a circuit structure 10 is formed on the first circuit 11 by a build-up process, wherein the circuit structure 10 includes, for example, the first circuit 11, the second circuit 12 and the dielectric layer 13 therebetween, wherein the first circuit 11 is a buried circuit embedded in the dielectric layer 13, and a bottom surface of the first circuit 11 is substantially flush with a bottom surface of the dielectric layer 13. The second lines 12 are non-buried lines and protrude from the surface of the dielectric layer 13. Optionally, the second line 12 is further covered with a protective layer 14, and the material of the protective layer 14 includes, but is not limited to, solder mask material such as green oil. Wherein the second circuit 12 is partially exposed out of the passivation layer 14 for connecting components. To this end, the wiring structure 10 is formed.

Referring to fig. 4C, a second carrier 52 is disposed under the protective layer 14, and the second carrier 52 may be a metal plating layer formed by electroplating, such as a copper plating layer. The first carrier plate 51 is then removed. The thicker copper layer is plated as the second carrier 52 in the process of processing and assembling after the first carrier 51 is removed, which is helpful to solve the problem of low throughput of the double-sided SiP package process.

Referring to fig. 4D and with reference to fig. 4C, after the first carrier 51 is removed, the second carrier 52 is used as a carrier of the circuit structure 10. Here, the exposed side of the circuit structure 10 after removing the first carrier 51, i.e. the side where the first circuit 11 is located, is defined as a first surface 101, and the opposite side surface is defined as a second surface 102, and the second circuit 12 is located on (adjacent to) the second surface 102.

Referring to fig. 4E, a conductive pillar, such as a copper plated pillar (Cu pillar), is formed on the first surface 101 as the first connecting member 21.

Referring to fig. 4F, the first electronic component 31 is provided on the first surface 101, and at least one passive device 33 such as a capacitor, an inductor, etc. may be further provided. Here, the first electronic component 31 may be disposed in a flip chip manner, and electrically connected to the first wire 11 through the plurality of first conductive bumps 311.

Referring to fig. 4G, molding is performed to form a first encapsulant 41, and the first encapsulant 41 encapsulates the first electronic component 31, the passive component 33 and the first connecting component 21 on the first surface 101 therein. The root of the first connecting member 21 is electrically connected to the first circuit 11, and the end is exposed from the first encapsulant 41, so as to connect to an external device. Then, the second carrier plate 52 is removed (see fig. 4F).

Next, reference may be made to fig. 4H and 4I:

referring to fig. 4H, a second electronic component 32 is disposed on the second surface 102, and at least one passive device 33 such as a capacitor, an inductor, etc. may also be disposed. Here, the second electronic component 32 may be disposed in a flip chip manner, and electrically connected to the second line 12 through a plurality of second conductive bumps 321.

Referring to fig. 4I, the second encapsulant 42 is formed by molding, and the second electronic element 32 and the passive component 33 on the second surface 102 are encapsulated by the second encapsulant 42. And, a solder ball 23 may be disposed at an end of the first connecting element 21, and the solder ball 23 may be used for electrically connecting an external device.

Thus, a double-sided SiP packaged semiconductor device is manufactured.

Alternatively, after fig. 4G, reference may also be made to fig. 4J and 4K:

referring to fig. 4J, a second electronic component 32 is disposed on the second surface 102, and at least one passive device 33, such as a capacitor, an inductor, etc., may also be disposed. Alternatively, the second electronic element 32 may be electrically connected to the second wiring 12 by a bonding wire 34.

Referring to fig. 4K, the second encapsulant 42 is formed by molding, and the second electronic component 32 and the passive component 33 on the second surface 102 are encapsulated by the second encapsulant 42. And, a solder ball 23 may be disposed at an end of the first connecting element 21, and the solder ball 23 may be used for electrically connecting an external device.

Thus, a double-sided SiP packaged semiconductor device is manufactured.

Referring to fig. 5A-5H, fig. 5A-5H are schematic diagrams of fabrication steps, respectively, of another embodiment of a semiconductor device of the present application.

Referring to fig. 5A, a first carrier 51 is provided, and the first carrier 51 may be, for example, a double-sided copper-clad plate or a single-sided copper-clad plate. In this embodiment, the first carrier 51 is used as a carrier, and a semiconductor device is manufactured on the first carrier, optionally, the semiconductor device may be manufactured on one side surface of the first carrier, or the semiconductor device may be manufactured on both side surfaces of the first carrier simultaneously, only a manufacturing process of one side is described herein, and a manufacturing process of the other side is similar and will not be described in detail. First, the first circuit 11 is formed on the copper layer of one surface of the first carrier 51.

Referring to fig. 5B, a circuit structure 10 is formed on the first circuit 11 by a build-up process, where the circuit structure 10 includes, for example, the first circuit 11, the second circuit 12 and a dielectric layer 13 therebetween, wherein the first circuit 11 is a buried circuit embedded in the dielectric layer 13, and a bottom surface of the first circuit 11 is substantially flush with a bottom surface of the dielectric layer 13. The second lines 12 are non-buried lines and protrude from the surface of the dielectric layer 13. Optionally, the second line 12 is further covered with a protective layer 14, and the material of the protective layer 14 includes, but is not limited to, solder mask material such as green oil. Wherein, the second circuit 12 is partially exposed out of the passivation layer 14 for connecting the components. Thus, the wiring structure 10 is formed. Here, one side of the circuit structure 10 contacting the first carrier 51, i.e. the side where the first circuit 11 is located, is defined as a first surface 101, and the opposite other surface is defined as a second surface 102, where the second circuit 12 is located (adjacent).

Referring to fig. 5C, a conductive pillar, such as a copper plated pillar (Cu pillar), is formed on the second surface 102 as the second connection member 22.

Referring to fig. 5D, a second electronic component 32 is provided on the second surface 102, and at least one passive device 33, such as a capacitor, an inductor, etc., may also be provided. Here, the second electronic component 32 may be disposed in a flip chip manner, and electrically connected to the second wire 12 through a plurality of second conductive bumps 321.

Then, the second encapsulant 42 is formed by molding, and the second electronic element 32, the passive component 33 and the second connecting member 22 on the second surface 102 are encapsulated by the second encapsulant 42. The root of the second connecting member 22 is electrically connected to the second circuit 12, and the end is exposed from the second encapsulant 42, so as to connect to an external device. Then, the first carrier plate 51 is removed.

Optionally, a removable second carrier 52 may be disposed as a carrier before the surface of the semiconductor device being fabricated on the other side of the first carrier 51, for example, between the mounting and molding processes on one side of the first carrier 51. The second carrier 52 can be, for example, a peelable adhesive tape, and its main function is to flatten the originally uneven surface.

Referring to fig. 5E and with reference to fig. 5D, after the first carrier 51 is removed, the first surface 101 of the circuit structure 10 is exposed. Next, a conductive pillar, such as an electroplated copper pillar, is formed on the first surface 101 as the first connecting member 21.

Referring to fig. 5F, the first electronic component 31 is provided on the first surface 101, and at least one passive device 33 such as a capacitor, an inductor, or the like may be further provided. Here, the first electronic component 31 may be disposed in a flip chip manner, and electrically connected to the first wiring 11 through the plurality of first conductive bumps 311.

Referring to fig. 5G, the first encapsulant 41 is formed by molding, and the first encapsulant 41 encapsulates the first electronic element 31, the passive component 33 and the first connecting element 21 on the first surface 101. The root of the first connecting member 21 is electrically connected to the first wire 11, and the end is exposed from the first encapsulant 41, so as to connect to an external device.

Referring to fig. 5H, solder balls 23 are disposed at the ends of the first connecting element 21 and the second connecting element 22, respectively, and the solder balls 23 can be used for electrically connecting to an external device.

Alternatively, an external device 60 may be stacked above the wiring structure 10, for example. The external device 60 may be electrically connected to the first connection 21 through the solder balls 23.

Alternatively, an external component 60 can also be arranged, for example, stacked below the circuit structure 10. The external device 60 may be electrically connected to the second connection 22 through the solder ball 23.

Illustratively, the external device 60 includes: an external wiring layer 61, an external electronic component 63 provided on the external wiring layer 61, and an external packaging material 62 packaging the external electronic component 63. The external electronic component 63 may be electrically connected to the external circuit layer 61 through a bonding wire, or may be electrically connected to the external circuit layer 61 through a conductive bump.

Thus, a double-sided SiPoP packaged semiconductor device is manufactured.

Referring to fig. 6A-6L, fig. 6A-6L are schematic diagrams of fabrication steps, respectively, of yet another embodiment of a semiconductor device of the present application.

Referring to fig. 6A, a first carrier 51 is provided, and the first carrier 51 may be, for example, a double-sided copper-clad plate or a single-sided copper-clad plate. In this embodiment, the first carrier 51 is used as a carrier, and a semiconductor device is manufactured on the first carrier, optionally, the semiconductor device may be manufactured on one side surface of the first carrier, or the semiconductor device may be manufactured on both side surfaces of the first carrier simultaneously, only a manufacturing process of one side is described herein, and a manufacturing process of the other side is similar and will not be described in detail. First, the first wiring 11 is formed on the copper layer of one surface of the first carrier plate 51.

Referring to fig. 6B, a circuit structure 10 is formed on the first circuit 11 by a build-up process, wherein the circuit structure 10 includes, for example, the first circuit 11, the second circuit 12 and the dielectric layer 13 therebetween, wherein the first circuit 11 is a buried circuit embedded in the dielectric layer 13, and a bottom surface of the first circuit 11 is substantially flush with a bottom surface of the dielectric layer 13. The second lines 12 are non-buried lines and protrude from the surface of the dielectric layer 13. Optionally, the second line 12 is further covered with a protective layer 14, and the material of the protective layer 14 includes, but is not limited to, solder mask material such as green oil. Wherein the second circuit 12 is partially exposed out of the passivation layer 14 for connecting components. To this end, the wiring structure 10 is formed. Here, one side of the circuit structure 10 contacting the first carrier 51, i.e. the side where the first circuit 11 is located, is defined as a first surface 101, and the opposite other surface is defined as a second surface 102, and the second circuit 12 is located on (adjacent to) the second surface 102. In this embodiment, a first opening 15 penetrating from the second surface 102 to the first surface 101 is also formed on the circuit structure 10.

Referring to fig. 6C, a peelable carrier is laminated on the second surface 102 of the circuit structure 10 as the second carrier 52, and then the first carrier 51 is removed. The second carrier 52 may be, for example, a peelable adhesive tape.

Referring to fig. 6D and with reference to fig. 6C, after the first carrier 51 is removed, the first surface 101 of the circuit structure 10 is exposed. Next, a conductive pillar, such as a copper plated pillar (Cu pillar), is formed on the first surface 101 as the first connecting member 21.

Referring to fig. 6E, the first electronic component 31 is disposed on the first surface 101, and at least one passive device 33 such as a capacitor, an inductor, etc. may also be disposed. Here, the first electronic component 31 may be disposed at the first opening 15 and cover the first opening 15 with the active surface facing the first opening 15. Optionally, a third electronic element 36 may be stacked on the first surface 101, and the third electronic element 36 may be stacked on and cover the first electronic element 31, and may be electrically connected to the first circuit 11 through a plurality of third conductive bumps 361 by using a flip chip method.

Next, molding is performed to form a first packaging material 41, and the first packaging material 41 packages the first electronic element 31, the third electronic element 36, the passive device 33 and the first connecting component 21 on the first surface 101 therein. The root of the first connecting member 21 is electrically connected to the first wire 11, and the end is exposed from the first encapsulant 41, so as to connect to an external device.

Then, the second carrier plate 52 is removed.

Referring to fig. 6F and with reference to fig. 6E, after the second carrier 52 is removed, the second surface 102 and the first opening 15 of the circuit structure 10 are exposed.

Next, reference may be made to FIGS. 6G-6I:

referring to fig. 6G, the first electronic component 31 is electrically connected to the second wiring 12 by the first conductive member 35 extending through the first opening 15. Here, the first conductive member 35 includes, but is not limited to, a bonding wire. Next, a second electronic component 32 may be provided on the second surface 102, and at least one passive component 33, such as a capacitor, an inductor, etc., may also be provided.

Referring to fig. 6H, the second encapsulant 42 is formed by molding, and the second electronic element 32 and the passive component 33 on the second surface 102 are encapsulated by the second encapsulant 42.

Referring to fig. 6I, a solder ball 23 is disposed at an end of the first connecting element 21, and the solder ball 23 can be used to electrically connect to an external device.

Thus, a double-sided SiPoP packaged semiconductor device was fabricated.

Alternatively, after FIG. 6F, reference may also be made to FIGS. 6J-6L:

referring to fig. 6J, the first electronic component 31 is electrically connected to the second wiring 12 by the first conductive member 35 extending through the first opening 15. Here, the first conductive member 35 includes, but is not limited to, a bonding wire.

Next, a second electronic component 32 may be provided on the second surface 102, and at least one passive component 33, such as a capacitor, an inductor, etc., may also be provided.

Optionally, a fourth electronic component 37 may be stacked above the second electronic component 32. Alternatively, the fourth electronic element 37 may be electrically connected to the second wiring 12 using a bonding wire.

Referring to fig. 6K, the second encapsulant 42 is formed by molding, and the second encapsulant 42 encapsulates the second electronic element 32, the fourth electronic element 37, and the passive component 33 on the second surface 102.

Referring to fig. 6L, a solder ball 23 is disposed at an end of the first connecting element 21, and the solder ball 23 can be used to electrically connect to an external device.

Thus, a double-sided SiPoP packaged semiconductor device was fabricated.

In the above, the present application exemplarily illustrates the manufacturing steps of the semiconductor device of the present application by fig. 4A to 4K, fig. 5A to 5H, and fig. 6A to 6L, respectively. In which fig. 4A to 4K show the manufacturing steps of the semiconductor device 1A shown in fig. 1A and the semiconductor device 1B shown in fig. 1B, fig. 5A to 5H show the manufacturing steps of the semiconductor device 1C shown in fig. 1C, and fig. 6A to 6L show the manufacturing steps of the semiconductor device 2A shown in fig. 2A and the semiconductor device 2B shown in fig. 2B.

As for the steps of manufacturing the semiconductor device 2C shown in fig. 2C, the semiconductor device 2D shown in fig. 2D, the semiconductor device 2E shown in fig. 2E, the semiconductor device 3A shown in fig. 3A, and the semiconductor device 3B shown in fig. 3B, reference may be made to fig. 4A to 4I, fig. 5A to 5H, and fig. 6A to 6I and the foregoing description, and details will not be repeated here.

While the present application has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present application. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present application due to variables in the manufacturing process and the like. There may be other embodiments of the application that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present application. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present application.

Claims

1. A semiconductor device, comprising:

the circuit structure is provided with a first surface and a second surface opposite to the first surface, the first surface is provided with a first circuit, the second surface is provided with a second circuit, the first circuit is an embedded circuit, and the second circuit is a non-embedded circuit;

the first connecting piece is arranged on the first surface and is configured to be connected with an external device.

2. The semiconductor device of claim 1, wherein the line structure further comprises:

a dielectric layer encapsulating the first line; wherein a bottom surface of the first line is substantially flush with a bottom surface of the dielectric layer.

3. The semiconductor device of claim 2, wherein the line structure further comprises:

a protective layer partially covering the second line; wherein a top surface of the protective layer is higher than a top surface of the second line.

4. The semiconductor device according to claim 1, further comprising:

the first electronic element is arranged on the first surface and is electrically connected with the first circuit through a plurality of first conductive bumps;

the second electronic element is arranged on the second surface and is electrically connected with the second circuit through a plurality of second conductive bumps;

wherein the pitch of the first conductive bumps is smaller than the pitch of the second conductive bumps.

5. The semiconductor device according to claim 1, further comprising:

and the second connecting piece is arranged on the second surface and is configured to be connected with an external device.

6. The semiconductor device of claim 1, wherein the line structure has a first opening therethrough, the semiconductor device further comprising:

the first electronic element is arranged on the first surface and covers the first opening;

and a first conductive member extending through the first opening to electrically connect the first electronic component to the second line.

7. The semiconductor device according to claim 6, further comprising:

and the second electronic element is arranged on the second surface, covers the first opening and is electrically connected with the second circuit.

8. The semiconductor device of claim 1, wherein the line structure has a first opening therethrough, the semiconductor device further comprising:

and the first electronic element is arranged in the first opening and is electrically connected with the second circuit.

9. The semiconductor device according to claim 8, further comprising:

the second electronic element is arranged on the second surface, covers the first opening and the first electronic element and is electrically connected with the second circuit;

wherein the first electronic component is electrically connected to the second electronic component.

10. The semiconductor device according to claim 9, further comprising:

and the third electronic element is arranged on the first surface, covers the first opening and the first electronic element and is electrically connected with the first circuit.