CN114171406A - Packaging method and packaging structure of fan-out type stacked chip - Google Patents

Packaging method and packaging structure of fan-out type stacked chip Download PDF

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Publication number
CN114171406A
CN114171406A CN202111493911.9A CN202111493911A CN114171406A CN 114171406 A CN114171406 A CN 114171406A CN 202111493911 A CN202111493911 A CN 202111493911A CN 114171406 A CN114171406 A CN 114171406A
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chip
dummy
layer
wafer
forming
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杜茂华
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN202111493911.9A priority Critical patent/CN114171406A/en
Publication of CN114171406A publication Critical patent/CN114171406A/en
Priority to PCT/CN2022/137248 priority patent/WO2023104095A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Abstract

The invention provides a packaging method and a packaging structure of fan-out type stacked chips, wherein the method comprises the following steps: fixing a first chip in a groove body on a dummy chip, wherein the first chip and the dummy chip are both provided with a plurality of conductive through holes; respectively carrying out hybrid bonding on the second chip, the dummy chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip is positioned on the inner side of the dummy chip; forming a first plastic packaging layer; forming a second plastic packaging layer; and forming a rewiring layer on the surfaces of the dummy chip and the first chip, which are far away from the second chip, wherein the rewiring layer is electrically connected with the first chip through the conductive through hole. According to the invention, the first chip and the second chip are respectively expanded and wafer-level hybrid bonding is carried out by utilizing the dummy wafer and the first plastic package layer through a wafer expansion technology, so that the production efficiency is improved while high-density interconnection is realized. And the through silicon via technology and the fan-out rewiring technology reduce the packaging size, and in addition, because the first chip and the second chip are directly bonded by wafer mixing, the ultrathin multilayer high-density stacked packaging is realized.

Description

Packaging method and packaging structure of fan-out type stacked chip
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a packaging method and a packaging structure of fan-out stacked chips.
Background
The electronic products have smaller and smaller volumes and stronger functions. With the consequent need for thinner and lighter semiconductor packages and higher interconnect densities. Conventional packages cannot meet future demands. Fig. 1 shows a typical conventional multilayer chip package structure, in which chips 1, 2 are vertically stacked on a substrate 6 via adhesive films 3, 4, and the chips 1, 2 are connected to the substrate 6 via gold wires 5. The chips 1, 2 and the gold wires 5 are protected by a molding compound 7. The whole package is connected to the outside by solder balls 8. In the current package, the height from the plastic package to the surface of the chip 2 is strictly limited due to the height limitation of the gold wire molding and the protection distance from the plastic package to the gold wire, and cannot be continuously reduced. Meanwhile, due to the limitation of materials and the limitation of substrate strength, the production difficulty of the ultrathin substrate is very high, and the application of the traditional package in ultrathin multilayer package is limited. And no matter the traditional routing connection or the reverse welding connection, the distance between the bonding pads is over 30um, and the difficulty of continuous reduction is extremely high.
In view of the above problems, there is a need for a package method and a package structure for fan-out stacked chips that are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a fan-out stacked chip packaging structure and a packaging method.
One aspect of the present invention provides a packaging method of fan-out stacked chips, the method comprising:
fixing a first chip in a groove body on a dummy chip, wherein the first chip and the dummy chip are both provided with a plurality of conductive through holes;
performing hybrid bonding on a second chip and the dummy chip and the first chip respectively, wherein the orthographic projection of the second chip on the dummy chip is located on the inner side of the dummy chip;
forming a first plastic packaging layer, wherein the second chip is wrapped by the first plastic packaging layer;
forming a second plastic packaging layer, wherein the second plastic packaging layer wraps the first chip, the dummy wafer, the second chip and the first plastic packaging layer;
and forming a rewiring layer on the surfaces of the dummy chip and the first chip, which are far away from the second chip, wherein the rewiring layer is electrically connected with the first chip through the conductive through hole.
Optionally, the surfaces of the first chip and the dummy wafer facing the second chip are provided with a first passivation layer and a first metal pad, and the surface of the second chip facing the first chip is provided with a second passivation layer and a second metal pad;
the hybrid bonding of the second chip with the dummy chip and the first chip respectively includes:
bonding the first passivation layers of the first chip and the dummy wafer with the second passivation layer of the second chip; and the number of the first and second groups,
and bonding the first metal bonding pads of the first chip and the dummy wafer with the second metal bonding pads of the second chip.
Optionally, before the hybrid bonding of the second chip with the dummy chip and the first chip, respectively, the method further includes:
forming an adhesive glue on the surfaces of the dummy chip and the first chip, and filling part of the adhesive glue into a gap between the dummy chip and the first chip;
and removing the adhesive glue on the surfaces of the dummy wafer and the first chip to expose the first passivation layer and the first metal pad of the dummy wafer and the first chip.
Optionally, the forming the second plastic package layer includes:
thinning the bonded first chip and the dummy wafer to expose the conductive through holes of the first chip and the dummy wafer;
and fixing the thinned surfaces of the first chip and the dummy chip, which deviate from the second chip, on a temporary carrier plate, and then forming the second plastic packaging layer.
Optionally, the forming a redistribution layer on the dummy chip and the surface of the first chip away from the second chip includes:
separating the first chip and the dummy wafer from the temporary carrier plate;
forming a dielectric layer on the surfaces of the second plastic packaging layer, the dummy chip and the first chip, which are far away from the second chip;
patterning the dielectric layer, and forming a rewiring layer on the patterned dielectric layer;
and patterning the redistribution layer, and forming solder balls on the patterned redistribution layer.
Optionally, the surface of the first chip is flush with the surface of the dummy sheet.
Optionally, the conductive via is a through silicon via.
The invention provides a packaging structure of fan-out stacked chips, which comprises a dummy wafer, a first chip, a second chip, a hybrid bonding structure, a first plastic packaging layer, a second plastic packaging layer and a rewiring layer, wherein the dummy wafer is arranged on the first chip;
the dummy sheet is provided with a groove body, the groove body is provided with the first chip, and the first chip and the dummy sheet are both provided with a plurality of conductive through holes;
the second chip is stacked on the first chip and the dummy chip, the second chip is respectively connected with the dummy chip and the first chip in hybrid bonding through the hybrid bonding structure, and the orthographic projection of the second chip on the dummy chip falls on the inner side of the dummy chip;
the first plastic packaging layer wraps the second chip;
the second plastic packaging layer wraps the first chip, the dummy sheet, the second chip and the first plastic packaging layer;
the rewiring layer is arranged on the dummy chip and the surface, away from the second chip, of the first chip, and the rewiring layer is electrically connected with the first chip through the conductive through hole.
Optionally, the hybrid bonding structure includes a first passivation layer and a first metal pad disposed on the surfaces of the first chip and the dummy wafer facing the second chip, and a second passivation layer and a second metal pad disposed on the surface of the second chip facing the first chip;
the first passivation layer is in bonding connection with the second passivation layer, and the first metal pad is in bonding connection with the second metal pad.
Optionally, the surface of the first chip is flush with the surface of the dummy sheet.
Optionally, the chip package structure further includes a dielectric layer and solder balls, the dielectric layer is disposed on the second plastic package layer, the dummy chip and the surface of the first chip away from the second chip, the redistribution layer is disposed on the dielectric layer, and the solder balls are disposed on the redistribution layer.
According to the packaging method and the packaging structure of the fan-out stacked chip, the first chip is fixed in the groove body on the dummy chip, and the first chip and the dummy chip are both provided with a plurality of conductive through holes; respectively carrying out hybrid bonding on the second chip, the dummy chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip is positioned on the inner side of the dummy chip; forming a first plastic packaging layer, wherein the second chip is wrapped by the first plastic packaging layer; forming a second plastic packaging layer, wherein the first chip, the dummy wafer, the second chip and the first plastic packaging layer are wrapped by the second plastic packaging layer; and forming a rewiring layer on the surfaces of the dummy chip and the first chip, which are far away from the second chip, wherein the rewiring layer is electrically connected with the first chip through the conductive through hole. According to the invention, through a wafer expansion technology, the first chip and the second chip are respectively expanded by using the dummy wafer and the first plastic package layer, and the first chip and the second chip are subjected to wafer-level hybrid bonding, so that the production efficiency is improved while high-density interconnection is realized; the conductive through hole technology and the fan-out rewiring technology replace the traditional substrate interconnection, the packaging size is reduced, in addition, the first chip and the second chip are in direct wafer hybrid bonding, the thickness after bonding is the same as the thickness of the chip body, the packaging height is reduced to the greatest extent, and the ultrathin multilayer high-density stacked packaging is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional multi-layered chip package structure according to the prior art;
FIG. 2 is a flow chart illustrating a method for packaging fan-out stacked chips according to another embodiment of the invention;
fig. 3 to 12 are schematic views illustrating a packaging process of fan-out stacked chips according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2, an aspect of the present invention provides a packaging method S100 for a fan-out stacked chip, where the packaging method S100 includes:
s110, fixing a first chip in a groove body on a dummy chip, wherein the first chip and the dummy chip are provided with a plurality of conductive through holes.
Specifically, as shown in fig. 3, the back surface of the first chip 110 may be fixed in a groove on the dummy wafer 120 by a patch adhesive 121, wherein the surface of the first chip 110 is flush with the surface of the dummy wafer 120, and the surface of the first chip 110 is flush with the surface of the dummy wafer 120, so that hybrid bonding with the second chip 140 can be better performed. The chip functional area of the first chip 110 can be expanded through the dummy wafer 120, the front surface of the first chip 110 and the front surface of the dummy wafer 120 are provided with a plurality of conductive through holes 130, and the plurality of conductive through holes 130 can be distributed at equal intervals, wherein the conductive through holes can be through silicon vias. And the vertical electrical interconnection of the silicon through holes is realized by adopting a silicon through hole technology, so that the packaging height is reduced.
And S120, respectively carrying out hybrid bonding on a second chip and the dummy chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip is located on the inner side of the dummy chip.
Specifically, as shown in fig. 3, 4 and 5, the surfaces of the first chip 110 and the dummy sheet 120 facing the second chip 140 are provided with a first passivation layer 111 and first metal pads 112, wherein each first metal pad 112 on the first chip 110 corresponds to each conductive via 130 of the first chip 110, and each first metal pad 112 on the dummy sheet 120 corresponds to each conductive via 130 of the dummy sheet 120. As shown in fig. 6, a surface of the second chip 140 facing the first chip 110 is provided with a second passivation layer 141 and a second metal pad 142.
Illustratively, before the hybrid bonding of the second chip with the dummy chip and the first chip, respectively, the method further comprises:
firstly, forming an adhesive glue on the surfaces of the dummy piece and the first chip, and filling part of the adhesive glue into a gap between the dummy piece and the first chip.
Specifically, as shown in fig. 4, an adhesive 122 is formed on the surfaces of the dummy sheet 120 and the first chip 110, and a part of the adhesive 122 is filled into the gap between the dummy sheet 120 and the first chip 110, so as to completely fix the first chip 110 in the groove of the dummy sheet 120.
And secondly, removing the adhesive glue on the surfaces of the dummy wafer and the first chip to expose the first passivation layer and the first metal bonding pad of the dummy wafer and the first chip.
Specifically, the adhesive 122 may be subjected to surface grinding and polishing, and the adhesive 122 on the surfaces of the dummy sheet 120 and the first chip 110 is removed, as shown in fig. 5, to expose the first passivation layer 111 and the first metal pad 112 on the dummy sheet 120 and the first chip 110.
The hybrid bonding of the second chip 140 to the dummy wafer 120 and the first chip 110, respectively, includes:
first, the first passivation layers 111 of the first chip 110 and the dummy wafer 120 are bonded to the second passivation layer 141 of the second chip 140. The first passivation layer 111 and the second passivation layer 141 may be made of silicon dioxide, or other materials having a passivation effect. Specifically, the first passivation layer 111 and the second passivation layer 141 are aligned, and then the first passivation layer 111 and the second passivation layer 141 are bonded by high temperature lamination.
Next, the first metal pads 112 of the first chip 110 and the dummy wafer 120 are bonded to the second metal pads 142 of the second chip 140. In this embodiment, the material of the first metal pad 112 and the second metal pad 142 may be copper, or may be other metal materials, which is not limited in this embodiment. Specifically, the first metal pad 112 and the second metal pad 142 are aligned, and then the connection is realized by utilizing the thermal expansion of copper through high-temperature pressing.
The second chip is respectively in wafer-level hybrid bonding with the first chip and the dummy wafer, so that the production efficiency is improved while high-density interconnection is realized.
As shown in fig. 6, the orthographic projection of the second chip 140 on the dummy sheet 120 falls on the inner side of the dummy sheet 120, that is, the size of the second chip 140 is smaller than that of the dummy sheet 120.
S130, forming a first plastic package layer, wherein the second chip is wrapped by the first plastic package layer.
Specifically, as shown in fig. 7, since the size of the second chip 140 is smaller than that of the dummy wafer 120, a first molding compound layer 150 may be formed on the second chip 140, and the first molding compound layer 150 protects the second chip 140, so that the size of the first molding compound layer 150 covering the second chip 140 may be the same as that of the dummy wafer 120, that is, the first molding compound layer 150 expands the second chip 140. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
S140, forming a second plastic package layer, wherein the first chip, the dummy wafer, the second chip and the first plastic package layer are wrapped by the second plastic package layer.
Firstly, thinning the bonded first chip and the dummy wafer to expose the conductive through holes of the first chip and the dummy wafer.
Specifically, as shown in fig. 8, the back surfaces of the bonded first chip 110 and dummy wafer 120 may be thinned through a grinding and polishing process, and then the conductive through holes 130, i.e., through silicon vias, of the first chip 110 and dummy wafer 120 are exposed through an etching process. Wherein, the residual thickness of the first chip 110 and the dummy sheet 120 after thinning is less than 40 um. By thinning the back surfaces of the first chip 110 and the dummy wafer 120, the conductive through holes 130 are exposed to realize electrical connection, and the package height is further reduced. In this embodiment, the first molding layer 150 and the second chip 140 are also thick, so the first molding layer 150 and the second chip 140 are also thinned.
Secondly, fixing the thinned surfaces of the first chip and the dummy wafer, which deviate from the second chip, on a temporary carrier plate, and then forming the second plastic packaging layer.
Specifically, the above packaging steps are to package the plurality of first chips 110, the plurality of dummy wafers 120, and the plurality of second chips 140 at the same time, and after the first chips 110 and the dummy wafers 120 are thinned, the thinned plurality of chip assemblies need to be cut to form a plurality of independent chip assemblies as shown in fig. 8. Then, as shown in fig. 9, the thinned surfaces of the first chip 110 and the dummy wafer 120 away from the second chip 140 are fixed to the temporary carrier 160 by using a bonding adhesive, that is, the back surfaces of the first chip 110 and the dummy wafer 120 are used as contact surfaces, and the temporary carrier 160 with the temporary bonding adhesive is attached one by one according to the final package size, and then the package is performed to form a second plastic package layer 170 as shown in fig. 10, where the second plastic package layer 170 wraps the first chip 110, the dummy wafer 120, the second chip 140 and the first plastic package layer 150. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
S150, forming a rewiring layer on the dummy chip and the surface of the first chip, which is far away from the second chip, wherein the rewiring layer is electrically connected with the first chip through the conductive through hole.
Illustratively, the forming a redistribution layer on the dummy chip and the surface of the first chip facing away from the second chip includes:
first, the first chip and the dummy wafer are separated from the temporary carrier board.
Specifically, as shown in fig. 11, the first chip 110 and the dummy wafer 120 are separated from the temporary carrier board 160, that is, the temporary carrier board 160 is removed. The separation method can adopt methods such as thermal separation, laser separation, ultraviolet light separation, mechanical separation and the like, which are all common temporary bonding separation methods at present, the embodiment of the separation method is not particularly limited, and the separation method can be selected according to actual needs.
And secondly, forming a dielectric layer on the surfaces of the second plastic packaging layer, the dummy chip and the first chip, which are far away from the second chip.
Specifically, as shown in fig. 12, a dielectric layer 180 is coated on the surfaces of the second molding layer 170, the dummy wafer 120 and the first chip 110 facing away from the second chip 140. That is, the dielectric layer 180 is formed on the back surfaces of the second molding layer 170, the thinned first chip 110 and the dummy wafer 120. The material of the dielectric layer 180 may be Polyimide (PI), Polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in this embodiment.
And patterning the dielectric layer, and forming a rewiring layer on the patterned dielectric layer.
Specifically, as shown in fig. 12, the dielectric layer 180 is patterned by a photolithography process, and a redistribution layer 190 is formed on the patterned dielectric layer 180. The redistribution layer 190 is electrically connected to the first chip 110 through the conductive via 130. The method for forming the redistribution layer 190 may be sputtering, electroplating, etc., and this embodiment is not particularly limited. The redistribution layer 190 may be made of titanium and copper, or may be made of other metal materials, which is not specifically limited in this embodiment.
And finally, patterning the redistribution layer, and forming solder balls on the patterned redistribution layer.
Specifically, as shown in fig. 12, the redistribution layer 190 is patterned by a photolithography process, and a plurality of solder balls 200 are formed by ball-mounting on the patterned redistribution layer 190 and electrically connected to the outside through the solder balls 200.
According to the invention, the first chip and the second chip are respectively expanded by using the dummy wafer and the first plastic package layer through a wafer expansion technology, and the first chip and the second chip are subjected to wafer-level hybrid bonding, so that the production efficiency is improved while high-density interconnection is realized; the conductive through hole technology and the fan-out rewiring technology replace the traditional substrate interconnection, the packaging size is reduced, in addition, the first chip and the second chip are in direct wafer hybrid bonding, the thickness after bonding is the same as the thickness of the chip body, the packaging height is reduced to the greatest extent, and the ultrathin multilayer high-density stacked packaging is realized.
As shown in fig. 12, another aspect of the present invention provides a fan-out stacked chip package structure 100, which includes a dummy wafer 120, a first chip 110, a second chip 140, a hybrid bonding structure (not shown), a first molding compound layer 150, a second molding compound layer 170, and a redistribution layer 180; the dummy wafer 120 is provided with a groove body, the groove body is provided with a first chip 110, the first chip 110 and the dummy wafer 120 are both provided with a plurality of conductive through holes 130, the conductive through holes 130 can be through silicon holes, the through silicon holes are vertically and electrically interconnected by adopting a through silicon hole technology, and the packaging height is reduced.
The second chip 140 is stacked on the first chip 110 and the dummy wafer 120, the second chip 140 is hybrid-bonded to the dummy wafer 120 and the first chip 110 respectively by a hybrid-bonding structure, and an orthographic projection of the second chip 140 on the dummy wafer 120 falls on an inner side of the dummy wafer 120, that is, the size of the second chip 140 is smaller than that of the dummy wafer 120.
The first molding compound layer 150 wraps the second chip 140 to protect the second chip 140. Since the size of the second chip 140 is smaller than that of the dummy wafer 120, a first molding layer may be formed on the second chip 140, so that the size of the first molding layer surrounding the second chip 140 may be the same as that of the dummy wafer 120. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
The second molding compound layer 170 wraps the first chip 110, the dummy wafer 120, the second chip 140, and the first molding compound layer 150. The second molding compound layer 170 protects the first chip 110, the dummy wafer 120, the second chip 140, and the first molding compound layer 150. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
The redistribution layer 190 is disposed on the dummy wafer 120 and a surface of the first chip 110 facing away from the second chip 140, and the redistribution layer 190 is electrically connected to the first chip 110 through the conductive via 130.
Illustratively, as shown in fig. 12, the hybrid bonding structure includes a first passivation layer 111 and a first metal pad 112 disposed on the surfaces of the first chip 110 and the dummy wafer 120 facing the second chip 140, and a second passivation layer 141 and a second metal pad 142 disposed on the surface of the second chip 140 facing the first chip 110; the first passivation layer 111 and the second passivation layer 141 are bonded, and the first metal pad 112 and the second metal pad 142 are bonded.
Illustratively, as shown in fig. 12, the surface of the first chip 110 is flush with the surface of the dummy sheet 120.
Exemplarily, as shown in fig. 12, the package further includes a dielectric layer 180 and solder balls 200, the dielectric layer 180 is disposed on the surfaces of the second molding compound layer 170, the dummy wafer 120 and the first chip 110 facing away from the second chip 140, and a redistribution layer 190 is disposed on the dielectric layer 180; solder balls 200 are disposed on the redistribution layer 190, and the package structure 100 is electrically connected to the outside through the solder balls 200.
According to the packaging structure of the fan-out stacked chip, the first chip and the second chip are respectively expanded through the dummy chip and the first chip, and the second chip is respectively in hybrid bonding connection with the dummy chip and the first chip through the hybrid bonding structure, so that the packaging height is reduced to the greatest extent, high-density interconnection is realized, and the production efficiency is improved; the first chip and the dummy wafer are provided with the conductive through holes, so that the packaging height is reduced, and high-density and ultra-thin packaging is realized.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (11)

1. A method of packaging fan-out stacked die, the method comprising:
fixing a first chip in a groove body on a dummy chip, wherein the first chip and the dummy chip are both provided with a plurality of conductive through holes;
performing hybrid bonding on a second chip and the dummy chip and the first chip respectively, wherein the orthographic projection of the second chip on the dummy chip is located on the inner side of the dummy chip;
forming a first plastic packaging layer, wherein the second chip is wrapped by the first plastic packaging layer;
forming a second plastic packaging layer, wherein the second plastic packaging layer wraps the first chip, the dummy wafer, the second chip and the first plastic packaging layer;
and forming a rewiring layer on the surfaces of the dummy chip and the first chip, which are far away from the second chip, wherein the rewiring layer is electrically connected with the first chip through the conductive through hole.
2. The method of claim 1, wherein the surfaces of the first chip and the dummy wafer facing the second chip are provided with a first passivation layer and a first metal pad, and the surface of the second chip facing the first chip is provided with a second passivation layer and a second metal pad;
the hybrid bonding of the second chip with the dummy chip and the first chip respectively includes:
bonding the first passivation layers of the first chip and the dummy wafer with the second passivation layer of the second chip; and the number of the first and second groups,
and bonding the first metal bonding pads of the first chip and the dummy wafer with the second metal bonding pads of the second chip.
3. The method of claim 2, wherein prior to hybrid bonding the second chip with the dummy chip and the first chip, respectively, the method further comprises:
forming an adhesive glue on the surfaces of the dummy chip and the first chip, and filling part of the adhesive glue into a gap between the dummy chip and the first chip;
and removing the adhesive glue on the surfaces of the dummy wafer and the first chip to expose the first passivation layer and the first metal pad of the dummy wafer and the first chip.
4. The method of claim 1, wherein the forming the second molding layer comprises:
thinning the bonded first chip and the dummy wafer to expose the conductive through holes of the first chip and the dummy wafer;
and fixing the thinned surfaces of the first chip and the dummy chip, which deviate from the second chip, on a temporary carrier plate, and then forming the second plastic packaging layer.
5. The method of claim 4, wherein forming a redistribution layer on the dummy wafer and the surface of the first chip facing away from the second chip comprises:
separating the first chip and the dummy wafer from the temporary carrier plate;
forming a dielectric layer on the surfaces of the second plastic packaging layer, the dummy chip and the first chip, which are far away from the second chip;
patterning the dielectric layer, and forming a rewiring layer on the patterned dielectric layer;
and patterning the redistribution layer, and forming solder balls on the patterned redistribution layer.
6. The method of any of claims 1 to 5, wherein the surface of the first chip is flush with the surface of the dummy wafer.
7. The method of any of claims 1 to 5, wherein the conductive vias are through silicon vias.
8. A packaging structure of fan-out stacked chips is characterized by comprising a dummy wafer, a first chip, a second chip, a hybrid bonding structure, a first plastic packaging layer, a second plastic packaging layer and a rewiring layer;
the dummy sheet is provided with a groove body, the groove body is provided with the first chip, and the first chip and the dummy sheet are both provided with a plurality of conductive through holes;
the second chip is stacked on the first chip and the dummy chip, the second chip is respectively connected with the dummy chip and the first chip in hybrid bonding through the hybrid bonding structure, and the orthographic projection of the second chip on the dummy chip falls on the inner side of the dummy chip;
the first plastic packaging layer wraps the second chip;
the second plastic packaging layer wraps the first chip, the dummy sheet, the second chip and the first plastic packaging layer;
the rewiring layer is arranged on the dummy chip and the surface, away from the second chip, of the first chip, and the rewiring layer is electrically connected with the first chip through the conductive through hole.
9. The package structure of claim 8, wherein the hybrid bond structure comprises a first passivation layer and a first metal pad disposed on a surface of the first chip and the dummy wafer facing the second chip, and a second passivation layer and a second metal pad disposed on a surface of the second chip facing the first chip;
the first passivation layer is in bonding connection with the second passivation layer, and the first metal pad is in bonding connection with the second metal pad.
10. The package structure of claim 8, wherein a surface of the first chip is flush with a surface of the dummy wafer.
11. The package structure of claim 10, further comprising a dielectric layer and solder balls,
the dielectric layer is arranged on the surfaces, away from the second chip, of the second plastic package layer, the dummy chip and the first chip, the redistribution layer is arranged on the dielectric layer, and the solder balls are arranged on the redistribution layer.
CN202111493911.9A 2021-12-08 2021-12-08 Packaging method and packaging structure of fan-out type stacked chip Pending CN114171406A (en)

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PCT/CN2022/137248 WO2023104095A1 (en) 2021-12-08 2022-12-07 Fan-out packaging method and packaging structure of stacked chips thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104095A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104095A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof

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