CN114188316A - Packaging method and packaging structure of fan-out type stacked chip - Google Patents

Packaging method and packaging structure of fan-out type stacked chip Download PDF

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Publication number
CN114188316A
CN114188316A CN202111493788.0A CN202111493788A CN114188316A CN 114188316 A CN114188316 A CN 114188316A CN 202111493788 A CN202111493788 A CN 202111493788A CN 114188316 A CN114188316 A CN 114188316A
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chip
layer
plastic packaging
forming
dummy
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杜茂华
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN202111493788.0A priority Critical patent/CN114188316A/en
Publication of CN114188316A publication Critical patent/CN114188316A/en
Priority to PCT/CN2022/137246 priority patent/WO2023104094A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a packaging method and a packaging structure of fan-out type stacked chips, wherein the method comprises the following steps: fixing the first chip in the groove body on the dummy chip; the second chip and the first chip are mixed and bonded, and the orthographic projection of the second chip on the dummy chip is superposed with the dummy chip; separating the dummy chip from the second chip, and forming a plurality of conductive convex columns on the surface of the second chip facing the first chip and on the outer side of the first chip; forming a first plastic packaging layer, wherein the first plastic packaging layer wraps the first chip and the plurality of conductive convex columns; forming a second plastic packaging layer, wherein the first chip, the second chip and the first plastic packaging layer are wrapped by the second plastic packaging layer; and forming a rewiring layer on the surfaces of the first chip and the first plastic packaging layer, which are deviated from the second chip, wherein the rewiring layer is electrically connected with the second chip through a plurality of conductive convex columns. According to the invention, wafer-level hybrid bonding is carried out by a wafer expansion technology, so that the production efficiency is improved while high-density interconnection is realized, the packaging size is reduced by the conductive convex column and the heavy wiring layer, and ultrathin multilayer stacked packaging is realized.

Description

Packaging method and packaging structure of fan-out type stacked chip
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a packaging method and a packaging structure of fan-out stacked chips.
Background
The electronic products have smaller and smaller volumes and stronger functions. With the consequent need for thinner and lighter semiconductor packages and higher interconnect densities. Conventional packages cannot meet future demands. Fig. 1 shows a typical conventional multilayer chip package structure, in which chips 1, 2 are vertically stacked on a substrate 6 via adhesive films 3, 4, and the chips 1, 2 are connected to the substrate 6 via gold wires 5. The chips 1, 2 and the gold wires 5 are protected by a molding compound 7. The whole package is connected to the outside by solder balls 8. In the current package, the height from the plastic package to the surface of the chip 2 is strictly limited due to the height limitation of the gold wire molding and the protection distance from the plastic package to the gold wire, and cannot be continuously reduced. Meanwhile, due to the limitation of materials and the limitation of substrate strength, the production difficulty of the ultrathin substrate is very high, and the application of the traditional package in ultrathin multilayer package is limited. And no matter the traditional routing connection or the reverse welding connection, the distance between the bonding pads is over 30um, and the difficulty of continuous reduction is extremely high.
In view of the above problems, there is a need for a package method and a package structure for fan-out stacked chips that are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a fan-out stacked chip packaging structure and a packaging method.
One aspect of the present invention provides a packaging method of fan-out stacked chips, the method comprising:
fixing the first chip in the groove body on the dummy chip;
carrying out hybrid bonding on a second chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip is superposed with the dummy chip;
separating the dummy chip from the second chip, and forming a plurality of conductive convex columns on the surface of the second chip facing the first chip and on the outer side of the first chip;
forming a first plastic packaging layer, wherein the first plastic packaging layer wraps the first chip and the plurality of conductive convex columns;
forming a second plastic packaging layer, wherein the second plastic packaging layer wraps the first chip, the second chip and the first plastic packaging layer;
and forming a rewiring layer on the surfaces of the first chip and the first plastic packaging layer, which are away from the second chip, wherein the rewiring layer is electrically connected with the second chip through the plurality of conductive convex columns.
Optionally, a first passivation layer and a first metal pad are disposed on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad are disposed on a surface of the second chip facing the first chip;
the hybrid bonding of the second chip and the first chip includes:
bonding a first passivation layer of the first chip with the second passivation layer of the second chip; and the number of the first and second groups,
bonding a first metal pad of the first chip with the second metal pad of the second chip.
Optionally, before the hybrid bonding of the second chip and the first chip, the method further includes:
forming an adhesive glue on the first surfaces of the dummy piece and the first chip, and filling part of the adhesive glue into a gap between the dummy piece and the first chip;
and completely removing the adhesive glue on the first surface of the first chip, and simultaneously keeping part of the adhesive glue on the surface of the dummy sheet to expose the first passivation layer and the first metal pad of the first chip.
Optionally, the forming the second plastic package layer includes:
thinning one side of the first plastic packaging layer, which is far away from the second chip, to expose the plurality of conductive convex columns so that the first plastic packaging layer is flush with the second surface of the first chip;
and fixing the thinned first plastic packaging layer and the second surface of the first chip onto a temporary carrier plate, and then forming the second plastic packaging layer.
Optionally, the forming a redistribution layer on the surface of the first chip and the surface of the first plastic package layer away from the second chip includes:
separating the first chip and the first plastic packaging layer from the temporary carrier plate;
forming a dielectric layer on the surfaces of the first chip and the first plastic packaging layer, which are far away from the second chip;
patterning the dielectric layer, and forming a rewiring layer on the patterned dielectric layer;
and patterning the redistribution layer, and forming solder balls on the patterned redistribution layer.
Optionally, the first surface of the first chip protrudes from the surface of the dummy wafer.
The invention provides a packaging structure of fan-out stacked chips, which comprises a first chip, a second chip, a plurality of conductive convex columns, a hybrid bonding structure, a first plastic packaging layer, a second plastic packaging layer and a rewiring layer, wherein the first chip is arranged on the first chip;
the second chip is stacked and arranged on the first chip through the hybrid key and the structure;
the plurality of conductive convex columns are arranged on one side, facing the first chip, of the second chip and are arranged on the outer side of the first chip;
the first plastic packaging layer wraps the first chip and the plurality of conductive convex columns;
the second plastic packaging layer wraps the first chip, the second chip and the first plastic packaging layer;
the rewiring layer is arranged on the surfaces, away from the second chip, of the first chip and the first plastic packaging layer, and the rewiring layer is electrically connected with the second chip through the plurality of conductive convex columns.
Optionally, the hybrid bonding structure includes a first passivation layer and a first metal pad disposed on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad disposed on a surface of the second chip facing the first chip;
the first passivation layer is in bonding connection with the second passivation layer, and the first metal pad is in bonding connection with the second metal pad.
Optionally, the package structure further includes a dielectric layer and a solder ball;
the dielectric layer is arranged on the surfaces, away from the second chip, of the second plastic packaging layer and the first chip, the redistribution layer is arranged on the dielectric layer, and the solder balls are arranged on the redistribution layer.
Optionally, the conductive pillar corresponds to the second metal pad.
According to the packaging method and the packaging structure of the fan-out stacked chip, the first chip is fixed in the groove on the dummy chip, the first chip and the second chip with two different sizes are adjusted to be the same size through the dummy chip, then wafer-level hybrid bonding is carried out on the first chip and the second chip, and wafer-level hybrid bonding is carried out through a wafer expansion technology, so that high-density interconnection is realized, and meanwhile, the production efficiency is improved.
According to the invention, the dummy wafer is separated from the second chip, the surface of the second chip facing the first chip is provided with a plurality of conductive convex columns, the outer side of the first chip is provided with a plurality of conductive convex columns, partial signals of the second chip are led out through the plurality of conductive convex columns, the surfaces of the first chip and the first plastic packaging layer, which are deviated from the second chip, are provided with the rewiring layer, and the traditional substrate interconnection is replaced by the conductive convex columns and the fan-out rewiring layer, so that the packaging size is reduced.
According to the invention, as the first chip and the second chip are directly bonded by the wafer, the thickness after bonding is the same as that of the chip body, the packaging height is reduced to the greatest extent, and ultrathin multilayer high-density stacked packaging is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional multi-layered chip package structure according to the prior art;
FIG. 2 is a flow chart illustrating a method for packaging fan-out stacked chips according to another embodiment of the invention;
fig. 3 to 16 are schematic views illustrating a packaging process of fan-out stacked chips according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2, an aspect of the present invention provides a packaging method S100 for a fan-out stacked chip, where the packaging method S100 includes:
and S110, fixing the first chip in the groove body on the dummy chip.
Specifically, as shown in fig. 1, the back surface of the first chip 110 is fixed in the groove on the dummy wafer 120 by the adhesive 121, wherein the first surface of the first chip 110 protrudes from the surface of the dummy wafer 120, that is, the front surface of the first chip 110 protrudes from the surface of the dummy wafer 120.
As shown in fig. 3, a first passivation layer 111 and a first metal pad 112 are disposed on a first surface of the first chip 110, that is, the front surface of the first chip 110 is provided with the first passivation layer 111 and the first metal pad 112, in this embodiment, the material of the first passivation layer 111 is a silicon dioxide passivation layer, or other materials that can perform a passivation function, and this embodiment is not particularly limited. In this embodiment, the material of the first metal pad 112 is copper, but may be other metal materials, and this embodiment is not limited in particular.
And S120, carrying out hybrid bonding on a second chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip is superposed with the dummy chip.
For example, before the hybrid bonding of the second chip and the first chip, the method further includes:
firstly, forming an adhesive glue on the first surfaces of the dummy sheet and the first chip, and filling part of the adhesive glue into a gap between the dummy sheet and the first chip.
Specifically, as shown in fig. 4, an adhesive 122 is formed on the first surfaces of the dummy chip 120 and the first chip 110, and a part of the adhesive 121 is filled into the gap between the dummy chip 120 and the first chip 110, so as to completely fix the first chip 110 in the groove of the dummy chip 120. Since the first surface of the first chip 110 protrudes from the surface of the dummy sheet 120, the adhesive 122 on the dummy sheet 120 is thicker than the adhesive 122 on the first surface of the first chip 110, so that the second chip 140 can be adhered to the dummy sheet 120 when the first chip 110 and the second chip 140 are mixedly bonded.
And completely removing the adhesive glue on the first surface of the first chip, and simultaneously keeping part of the adhesive glue on the surface of the dummy sheet to expose the first passivation layer and the first metal pad of the first chip.
Specifically, as shown in fig. 5, the adhesive 121 on the first surface of the first chip 110 may be subjected to surface grinding and polishing and chemical cleaning, so as to completely remove the adhesive 122 on the first surface of the first chip 110, that is, remove the adhesive 122 on the front surface of the first chip 110, while leaving part of the adhesive 122 on the surface of the dummy sheet 120, and expose the first passivation layer 111 and the first metal pad 112 of the first chip 110. The adhesive 122 on part of the surface of the dummy sheet 120 can fix the dummy sheet 120 on the second chip 140.
Specifically, as shown in fig. 6, a surface of the second chip 140 facing the first chip 110 is provided with a second passivation layer 141 and a second metal pad 142. In this embodiment, the material of the second passivation layer 141 may be a silicon dioxide layer or a silicon nitride layer, or other materials that can perform a passivation function. The material of the second metal pad 142 is copper, and may be other metal materials, which is not specifically limited in this embodiment.
Illustratively, the hybrid bonding the second chip and the first chip includes:
first, a first passivation layer of the first chip is bonded with the second passivation layer of the second chip.
Specifically, as shown in fig. 6, the first passivation layer 111 of the first chip 110 is bonded with the second passivation layer 141 of the second chip 140. The first passivation layer 111 is aligned with the second passivation layer 141, and then the first passivation layer 111 is connected with the second passivation layer 141 through high temperature lamination.
And secondly, bonding the first metal pad of the first chip with the second metal pad of the second chip.
Specifically, as shown in fig. 6, the first metal pads 112 of the first chip 110 are bonded to the second metal pads 142 of the second chip 140. The first metal pad 112 is now aligned with the second metal pad 142 and then the connection is made by thermal expansion of copper through high temperature bonding.
As shown in fig. 6, the orthographic projection of the second chip 140 on the dummy wafer 120 coincides with the dummy wafer 120, that is, the size of the second chip 140 coincides with the size of the dummy wafer 120. The first chip 110 and the second chip 140 with two different sizes are adjusted to be the same size by adopting a dummy wafer, and wafer-level hybrid bonding is carried out by a wafer expansion technology, so that the production efficiency is improved while high-density interconnection is realized.
S130, separating the dummy wafer from the second chip, and forming a plurality of conductive convex columns on the surface of the second chip facing the first chip and on the outer side of the first chip.
Specifically, as shown in fig. 7, the back surfaces of the bonded first chip 110 and dummy wafer 120 are thinned. Wherein, the residual thickness of the first chip 110 and the dummy sheet 120 after thinning is less than 40 um. The package height is further reduced by thinning the back surfaces of the first chip 110 and the dummy sheet 120.
As shown in fig. 8, the first chip 110 and the dummy chip 120 are irradiated with laser or ultraviolet light, which is determined according to the characteristics of the adhesive 122, and the adhesive 122 loses its adhesiveness by the energy of the light wave, so that, as shown in fig. 9, the dummy chip 120 is detached from the second chip 140, i.e., the second chip 140 is separated from the dummy chip 120, leaving the first chip 110 and the second chip 140 mixed with the bonding. It should be noted that other methods may be used to separate the second chip 140 from the dummy wafer 120, and this embodiment is not limited in particular.
As shown in fig. 10, after the second chip 140 is separated from the dummy wafer 120, a plurality of conductive posts 150 are formed on the surface of the second chip 140 facing the first chip 110 and the outer side of the first chip 110 by electroplating or the like. That is, the plurality of conductive posts 150 are located at the dummy wafer 120 before the second chip 140 is separated from the dummy wafer 120. The plurality of conductive posts 150 are plated on the second metal pad 142, corresponding to the second metal pad 142, and the conductive posts 150 can be plated according to actual requirements. And a part of signals of the second chip 140 can be led out by adopting the plurality of conductive convex columns 150, and the vertical electrical interconnection is realized by adopting the conductive convex columns 150 relative to the interconnection of the substrates, so that the packaging height is reduced.
In the embodiment, the conductive pillar 150 is a copper pillar, and other metal materials may be selected according to the requirement.
S140, forming a first plastic package layer, wherein the first chip and the plurality of conductive convex columns are wrapped by the first plastic package layer.
Specifically, as shown in fig. 11, after the plurality of conductive pillars 150 are formed, a first molding layer 160 is formed on a side of the first chip 110 away from the second chip 140, the first molding layer 160 wraps the plurality of conductive pillars 150 and the first chip 110, and the first molding layer 160 protects the plurality of conductive pillars 150 and the first chip. The plastic packaging method can be membrane layer vacuum lamination or traditional plastic packaging process, and the embodiment is not particularly limited
S150, forming a second plastic package layer, wherein the first chip, the second chip and the first plastic package layer are wrapped by the second plastic package layer.
Firstly, thinning one side of the first plastic packaging layer, which is far away from the second chip, and exposing the conductive convex column so as to enable the first plastic packaging layer to be flush with the second surface of the first chip.
Specifically, as shown in fig. 12, a side of the first molding compound layer 160 away from the second chip 140 is thinned by grinding, polishing and chemical cleaning, and the conductive posts 150 are exposed, so that the first molding compound layer 160 is flush with the second surface of the thinned first chip 110. That is, the first molding compound layer 160 is made flush with the back surface of the thinned first chip 110
And secondly, fixing the thinned first plastic packaging layer and the second surface of the first chip on a temporary carrier plate, and then forming the second plastic packaging layer.
Specifically, in the above packaging step, the plurality of first chips 110, the plurality of dummy wafers 120, and the plurality of second chips 140 are packaged simultaneously, and after the side of the first molding compound layer 160 away from the second chip 140 is thinned, the thinned plurality of chip assemblies need to be cut, so as to form the plurality of independent chip assemblies shown in fig. 12. Then, as shown in fig. 13, the thinned first plastic package layer 160 and the surface of the first chip 110 away from the second chip 140 are fixed on the temporary carrier plate 161 by adhesive glue, that is, the back surface of the first chip 110 is used as a contact surface, and the temporary carrier plate 161 with the temporary adhesive glue is attached one by one according to the final package size, and then plastic package is performed to form a second plastic package layer 170 as shown in fig. 14, where the second plastic package layer 170 wraps the first chip 110, the second chip 140 and the first plastic package layer 160. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
And S160, forming a rewiring layer on the surfaces of the first chip and the first plastic packaging layer, which are away from the second chip, wherein the rewiring layer is electrically connected with the second chip through the plurality of conductive convex columns.
Illustratively, the forming a redistribution layer on the surfaces of the first chip and the first molding compound layer, which face away from the second chip, includes:
firstly, the first chip and the first plastic package layer are separated from the temporary carrier plate.
Specifically, as shown in fig. 15, the first chip 110 and the first molding layer 160 are separated from the temporary carrier board 161, that is, the temporary carrier board 161 is removed. The separation method can adopt methods such as thermal separation, laser separation, ultraviolet light separation, mechanical separation and the like, which are all common temporary bonding separation methods at present, the embodiment of the separation method is not particularly limited, and the separation method can be selected according to actual needs.
And secondly, forming a dielectric layer on the surfaces of the first chip and the first plastic packaging layer, which are far away from the second chip.
Specifically, as shown in fig. 16, a dielectric layer 180 is coated on the surfaces of the first chip 110 and the first molding compound 160 facing away from the second chip 150. The material of the dielectric layer 180 may be Polyimide (PI), Polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in this embodiment.
And patterning the dielectric layer, and forming a rewiring layer on the patterned dielectric layer.
Specifically, as shown in fig. 16, the dielectric layer 180 is patterned by a photolithography process, and a redistribution layer 190 is formed on the patterned dielectric layer 180. The redistribution layer 190 is electrically connected to the second chip 140 through the plurality of conductive pillars 150. The method for forming the redistribution layer 190 may be electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the like, and this embodiment is not particularly limited. The material of the redistribution layer 190 may be metal titanium and metal copper, and the material of the redistribution layer 190 is not limited in this embodiment.
And finally, patterning the redistribution layer, and forming solder balls on the patterned redistribution layer.
Specifically, the redistribution layer 190 is patterned by a photolithography process, and a plurality of solder balls (not shown) are formed by ball-mounting on the patterned redistribution layer 190 and electrically connected to the outside through the solder balls.
According to the packaging method and the packaging structure of the fan-out stacked chip, the first chip is fixed in the groove on the dummy chip, the first chip and the second chip with two different sizes are adjusted to be the same size through the dummy chip, then wafer-level hybrid bonding is carried out on the first chip and the second chip, and wafer-level hybrid bonding is carried out through a wafer expansion technology, so that high-density interconnection is realized, and meanwhile, the production efficiency is improved.
According to the invention, the dummy wafer is separated from the second chip, the surface of the second chip facing the first chip is provided with a plurality of conductive convex columns, the outer side of the first chip is provided with a plurality of conductive convex columns, partial signals of the second chip are led out through the plurality of conductive convex columns, the surfaces of the first chip and the first plastic packaging layer, which are deviated from the second chip, are provided with the rewiring layer, and the traditional substrate interconnection is replaced by the conductive convex columns and the fan-out rewiring layer, so that the packaging size is reduced.
According to the invention, as the first chip and the second chip are directly bonded by the wafer, the thickness after bonding is the same as that of the chip body, the packaging height is reduced to the greatest extent, and ultrathin multilayer high-density stacked packaging is realized.
As shown in fig. 16, another aspect of the present invention provides a fan-out stacked chip package structure, which includes a first chip 110, a second chip 140, a plurality of conductive pillars 150, a hybrid bonding structure (not shown), a first molding compound layer 160, a second molding compound layer 170, and a redistribution layer 190.
The second chip 140 is disposed on the first chip 110 by the hybrid key and structure stack.
The plurality of conductive pillars 150 are disposed on a side of the second chip 140 facing the first chip 110, and are disposed outside the first chip 110.
The first molding compound layer 160 wraps the first chip 110 and the plurality of conductive pillars 150, and the first molding compound layer 160 protects the first chip 110 and the plurality of conductive pillars 150.
The second plastic package layer 170 wraps the first chip 110, the second chip 140 and the first plastic package layer 160, and the second plastic package layer 170 protects the first chip 110, the second chip 140 and the first plastic package layer 160.
The redistribution layer 190 is disposed on the surfaces of the first chip 110 and the first molding compound layer 160 away from the second chip 140, and the redistribution layer 190 is electrically connected to the second chip 140 through the plurality of conductive pillars 150.
Illustratively, as shown in fig. 16, the hybrid bonding structure includes a first passivation layer 111 and a first metal pad 112 disposed on a surface of the first chip 110 facing the second chip 140, and a second passivation layer 141 and a second metal pad 142 disposed on a surface of the second chip 140 facing the first chip 110, wherein the first passivation layer 111 and the second passivation layer 141 are bonded and connected, and the first metal pad 112 and the second metal pad 142 are bonded and connected.
Illustratively, as shown in fig. 16, the package structure further includes a dielectric layer 180 and solder balls (not shown in the figure), the dielectric layer 180 is disposed on the second molding compound layer 170 and a surface of the first chip 110 facing away from the second chip 140, a redistribution layer 190 is disposed on the dielectric layer 180, and the solder balls are disposed on the redistribution layer 190. The packaging structure is electrically connected with the outside through the solder balls.
For example, as shown in fig. 16, the conductive pillars 150 correspond to the second metal pads 142, that is, a plurality of conductive pillars 150 are plated on the second metal pads 142, corresponding to the second metal pads 142, and the conductive pillars 150 can be plated according to actual requirements. And a part of signals of the second chip 140 can be led out by adopting the plurality of conductive convex columns 150, and the vertical electrical interconnection is realized by adopting the conductive convex columns 150 relative to the interconnection of the substrates, so that the packaging height is reduced.
In this embodiment, both the first passivation layer 111 and the second passivation layer 141 may be a silicon dioxide layer or a silicon nitride layer, or may be other materials capable of performing a passivation function. The material of the first metal pad 112 and the second metal pad 142 is copper, and may be other metal materials, which is not specifically limited in this embodiment. The material of the dielectric layer 180 may be Polyimide (PI), Polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in this embodiment. The redistribution layer 190 may be made of titanium and copper, or may be made of other metal materials, which is not specifically limited in this embodiment.
According to the packaging structure of the fan-out stacked chip, the second chip is in hybrid bonding connection with the first chip through the hybrid bonding structure, high-density interconnection is achieved, production efficiency is improved, and packaging height is reduced to the greatest extent. A plurality of electrically conductive posts are arranged on one side, facing the first chip, of the second chip and are arranged on the outer side of the first chip, partial signals of the second chip can be led out through the electrically conductive posts, the rewiring layer is arranged on the surface, deviating from the second chip, of the first chip and the first plastic packaging layer, and the electrically conductive posts and the rewiring layer are adopted for vertical electrical interconnection relative to substrate interconnection, so that the packaging height is reduced, and high-density and ultrathin packaging is realized.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A method of packaging fan-out stacked die, the method comprising:
fixing the first chip in the groove body on the dummy chip;
carrying out hybrid bonding on a second chip and the first chip, wherein the orthographic projection of the second chip on the dummy chip is superposed with the dummy chip;
separating the dummy chip from the second chip, and forming a plurality of conductive convex columns on the surface of the second chip facing the first chip and on the outer side of the first chip;
forming a first plastic packaging layer, wherein the first plastic packaging layer wraps the first chip and the plurality of conductive convex columns;
forming a second plastic packaging layer, wherein the second plastic packaging layer wraps the first chip, the second chip and the first plastic packaging layer;
and forming a rewiring layer on the surfaces of the first chip and the first plastic packaging layer, which are away from the second chip, wherein the rewiring layer is electrically connected with the second chip through the plurality of conductive convex columns.
2. The method according to claim 1, characterized in that the surface of the first chip facing the second chip is provided with a first passivation layer and a first metal pad, and the surface of the second chip facing the first chip is provided with a second passivation layer and a second metal pad;
the hybrid bonding of the second chip and the first chip includes:
bonding a first passivation layer of the first chip with the second passivation layer of the second chip; and the number of the first and second groups,
bonding a first metal pad of the first chip with the second metal pad of the second chip.
3. The method of claim 2, wherein prior to hybrid bonding the second chip with the first chip, the method further comprises:
forming an adhesive glue on the first surfaces of the dummy piece and the first chip, and filling part of the adhesive glue into a gap between the dummy piece and the first chip;
and completely removing the adhesive glue on the first surface of the first chip, and simultaneously keeping part of the adhesive glue on the surface of the dummy sheet to expose the first passivation layer and the first metal pad of the first chip.
4. The method of claim 1, wherein the forming the second molding layer comprises:
thinning one side of the first plastic packaging layer, which is far away from the second chip, to expose the plurality of conductive convex columns so that the first plastic packaging layer is flush with the second surface of the first chip;
and fixing the thinned first plastic packaging layer and the second surface of the first chip onto a temporary carrier plate, and then forming the second plastic packaging layer.
5. The method of claim 4, wherein the forming a redistribution layer on the first chip and the surface of the first molding compound layer facing away from the second chip comprises:
separating the first chip and the first plastic packaging layer from the temporary carrier plate;
forming a dielectric layer on the surfaces of the first chip and the first plastic packaging layer, which are far away from the second chip;
patterning the dielectric layer, and forming a rewiring layer on the patterned dielectric layer;
and patterning the redistribution layer, and forming solder balls on the patterned redistribution layer.
6. The method of any one of claims 1 to 5, wherein the first surface of the first chip protrudes above the surface of the dummy wafer.
7. The packaging structure of the fan-out stacked chip is characterized by comprising a first chip, a second chip, a plurality of conductive convex columns, a hybrid bonding structure, a first plastic packaging layer, a second plastic packaging layer and a rewiring layer;
the second chip is stacked and arranged on the first chip through the hybrid key and the structure;
the plurality of conductive convex columns are arranged on one side, facing the first chip, of the second chip and are arranged on the outer side of the first chip;
the first plastic packaging layer wraps the first chip and the plurality of conductive convex columns;
the second plastic packaging layer wraps the first chip, the second chip and the first plastic packaging layer;
the rewiring layer is arranged on the surfaces, away from the second chip, of the first chip and the first plastic packaging layer, and the rewiring layer is electrically connected with the second chip through the plurality of conductive convex columns.
8. The package structure of claim 7, wherein the hybrid bond structure comprises a first passivation layer and a first metal pad disposed on a surface of the first chip facing the second chip, and a second passivation layer and a second metal pad disposed on a surface of the second chip facing the first chip;
the first passivation layer is in bonding connection with the second passivation layer, and the first metal pad is in bonding connection with the second metal pad.
9. The package structure of claim 8, further comprising a dielectric layer and solder balls;
the dielectric layer is arranged on the surfaces, away from the second chip, of the second plastic packaging layer and the first chip, the redistribution layer is arranged on the dielectric layer, and the solder balls are arranged on the redistribution layer.
10. The package structure of claim 9, wherein the conductive post corresponds to the second metal pad.
CN202111493788.0A 2021-12-08 2021-12-08 Packaging method and packaging structure of fan-out type stacked chip Pending CN114188316A (en)

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CN202111493788.0A CN114188316A (en) 2021-12-08 2021-12-08 Packaging method and packaging structure of fan-out type stacked chip
PCT/CN2022/137246 WO2023104094A1 (en) 2021-12-08 2022-12-07 Fan-out packaging method and packaging structure of stacked chips thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115411032A (en) * 2022-11-02 2022-11-29 季华实验室 CMOS integrated circuit substrate, preparation method thereof and display panel
WO2023104094A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104094A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof
CN115411032A (en) * 2022-11-02 2022-11-29 季华实验室 CMOS integrated circuit substrate, preparation method thereof and display panel

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