TWI389220B - 半導體封裝件及其製法 - Google Patents
半導體封裝件及其製法 Download PDFInfo
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description
本發明係有關於一種半導體封裝件及其製法,尤指一種毋需晶片承載件之半導體封裝件及其製法。
傳統半導體晶片係以導線架(Lead Frame)作為晶片承載件以形成一半導體封裝件。該導線架係包含一晶片座及形成於該晶片座周圍之多數導腳,待半導體晶片黏接至晶片座上並以銲線電性連接該晶片與導腳後,經由一封裝樹脂包覆該晶片、晶片座、銲線以及導腳之內段而形成該具導線架之半導體封裝件。
以導線架作為晶片承載件之半導體封件之型態及種類繁多,就四邊扁平無導腳(Quad Flat Non-leaded,QFN)半導體封裝件而言,其特徵在於未設置有外導腳,即未形成有如習知四邊形平面(Quad Flat package,QFP)半導體封裝件中用以與外界電性連接之外導腳,如此,將得以縮小半導體封裝件之尺寸。
惟,伴隨著半導體產品輕薄短小之發展趨勢的日益重要,傳統導線架往往因其厚度之限制,而無法進一步縮小封裝件之整體高度,因此,業界便發展出一種無承載件之半導體封裝件,冀藉由減低習用之導線架厚度,以令其整體厚度得以較傳統導線架式封裝件更為輕薄。
請參閱第1A至1E圖,美國專利第6,884,652號揭示一種毋需晶片承載件之半導體封裝件之製法,首先係於一銅板10上敷設一如玻纖浸樹脂(Prepreg,PP)或ABF(Ajinomoto Build-up Film)之介電層11,並於該介電層11之預定部位開設多數開口110,以透過電鍍方式敷設一銲料12於各該介電層之開口110中(如第1A圖所示);接著以無電解電鍍(Electroless Plating)或濺鍍(Sputtering)方式形成一第一薄銅層13於該介電層11及銲料12上(如第1B圖所示);再以電鍍方式敷設一第二銅層14於該第一薄銅層13上,且圖案化(Patterning)該第一薄銅層及13第二銅層14以形成多數導電線路,而使各該導電線路具有一終端141,再以電鍍方式敷設一金屬層15於各該導電線路之終端141上(如第1C圖所示);復接置至少一晶片16於該導電線路之預定部位上,並藉多數銲線17電性連接該晶片16至該敷設有金屬層15之終端,且形成一封裝膠體18以包覆該晶片16及銲線17(如第1D圖所示);以及以蝕刻(Etching)方式移除該銅板10,而使該介電層11及銲料12外露(如第1E圖所示)。
然而於前述製法中,需利用介電層開口110定義出供晶片16與外界電性連接之終端(即銲料12)位置,該用以形成銲料12之介電層開口110尺寸必滿足預定之大尺寸(如400微米),且此使用之介電層如玻纖浸樹脂(Prepreg,PP)或ABF(Ajinomoto Build-up Film)並非感光材質(photosensitive material),因此不能以黃光製程形成,為此,傳統上多採用雷射燒製方式形成該開口110,惟如此不僅增加製程時間且提高製程成本。
再者,由於該導電線路厚僅5-10微米,且與封裝膠體之結合力差,因此於該導電線路外露之終端與封裝膠體間容易發生脫層問題。
因此,如何提供一種毋需晶片承載件之半導體封裝件及其製法,既可避免於介電層中形成大尺寸開口所導致製程不便及成本高等問題,同時亦可提供導電線路終端具鑲嵌能力而不易發生脫層問題,實為目前業界亟待解決之課題。
有鑑於前述習知技術問題,本發明之一目的在於提供一種毋需晶片承載件之半導體封裝件及其製法,同時避免於介電層中形成大尺寸開口所造成製程不便及成本增加問題。
本發明之另一目的在於提供一種導電線路具有鑲嵌能力之半導體封裝件及其製法。
本發明之又一目的在於提供一種半導體封裝件及其製法,避免導電線路終端與封裝膠體發生脫層問題。
為達上揭目的,本發明揭露一種半導體封裝件之製法,包括:敷設第一阻層於一金屬載具上,並於該第一阻層之預定部位開設多數貫穿之開口,以外露出該金屬載具;於該開口中形成導電金屬層;移除該第一阻層,並於該金屬載具上形成導電金屬層之一側覆蓋一介電層,並令該介電層形成有盲孔(blind via)以露出部分導電金屬層;於該介電層上形成導電線路及於該盲孔中形成導電柱,並使該導電線路透過該導電柱而電性連接至該導電金屬層;將至少一晶片電性連接至該導電線路;形成一封裝膠體以包覆該晶片及導電線路;以及移除該金屬載具,藉以外露出該介電層及導電金屬層。
該導電線路及導電柱之製法係包括:以無電解電鍍方式於該介電層及外露於盲孔之導電金屬層上形成一導電層;以一第二阻層覆蓋該導電層,並形成有多數圖案化之開口;透過電鍍製程,以於外露出該第二阻層開口之導電層上形成導電線路及於該盲孔中形成導電柱,並使該導電線路透過該導電柱而電性連接至該導電金屬層;以及移除該第二阻層及其所覆蓋之導電層部分。
透過前述製法,本發明復揭示一種半導體封裝件,係包括:導電金屬層;介電層,係覆蓋該導電金屬層之一側,其中該介電層形成有盲孔以外露出部分該導電金屬層;導電線路,係形成於該介電層上;導電柱,係形成於該盲孔中,並使該導電線路透過該導電柱而電性連接至該導電金屬層;晶片,係電性連接至該導電線路;以及封裝膠體,係包覆該晶片及導電線路。另外該導電線路與該介電層間及該導電柱與該盲孔間復包含有一導電層。
於本發明中,復可於外露之導電金屬層上接置如銲球之導電元件,以供晶片電性連接至外部裝置。
再者,於形成該導電金屬層前,係可先於第一阻層開口中形成與金屬載具相同材質之鍍層,以於移除該金屬載具時,同時移除該鍍層,進而使該導電金屬層相對內凹於該介電層中,以供導電元件有效接置於該導電金屬層上。
另外,於該導電線路上亦可覆蓋一例如拒銲層之絕緣層,並令該絕緣層形成有外露出部分導電線路之開孔,以供晶片以覆晶方式電性連接至該導電線路。
再者,該導電金屬層之材質係可與該金屬載具相同,以於蝕刻移除該金屬載具時,同時蝕刻部分之導電金屬層,並控制該導電金屬層之蝕刻量,進而使該導電金屬層相對內凹於該介電層中,藉以有效於該導電金屬層上接置導電元件。
因此本發明之半導體封裝件及其製法主要係先在金屬載具上敷設一第一阻層,並於該第一阻層中開設多數外露出該金屬載具之開口,以於該開口中形成導電金屬層,接著移除該第一阻層,並於該金屬載具上具導電金屬層之一側覆蓋一介電層,且於該介電層中形成盲孔(blind via)以外露出部分導電金屬層,再於該介電層上形成導電線路及於該盲孔中形成導電柱,並使該導電線路透過該導電柱而電性連接至該導電金屬層,如此即可使該導電線路及作為電性連接終端(terminal)之導電金屬層利用導電柱與該介電層有效嵌合,減少習知脫層問題發生,再者於本發明中,該介電層中僅需形成小尺寸之盲孔,故可避免習知技術因形成大尺寸開口所造成製程不便及成本增加問題。之後即可將至少一晶片電性連接至該導電線路,且形成一包覆該晶片及導電線路之封裝膠體,再移除該金屬載具,藉以外露出該介電層及作為電性連接終端之導電金屬層,進而形成毋需晶片承載件之半導體封裝件。
以下係藉由特定的具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
請參閱第2A至2H圖,係本發明之半導體封裝件及其製法第一實施之剖面示意圖。
如第2A圖所示,首先,製備如銅板(Cu Plate)之金屬載具(Carrier)20,並於該金屬載具20之一表面上敷設第一阻層21,該第一阻層21例如為光阻層(photo-resist)等,並透過曝光、顯影之方式使該第一阻層21形成有外露出部分該金屬載具20之貫穿開口210。
接著於該第一阻層開口210中形成導電金屬層22,其中該導電金屬層22係包括有對應晶片位置之晶片座(die pad)221及供晶片與外部裝置電性連接之電性連接終端(terminal)222。該導電金屬層22之材質例如為金/鎳/銅(Au/Ni/Cu)、鎳/金(Ni/Au)、金/鎳/金(Au/Ni/Au)、金/鎳/鈀/金(Au/Ni/Pd/Au)、金/鈀/鎳/鈀(Au/Pd/Ni/Pd)等。
如第2B及2C圖所示,移除該第一阻層21,並於該金屬載具20上形成有導電金屬層22之一側覆蓋一介電層23,該介電層23例如為玻纖浸樹脂(Prepreg,PP)或ABF(Ajinomoto Build-up Film),且利用如雷射開孔技術以於該介電層23中形成複數盲孔(blind via)230,其中該盲孔230之開孔孔徑約100微米,藉以外露出部分導電金屬層22,避免習知技術於介電層中形成大尺寸開口(400微米)時所造成製程不便及成本增加問題。
如第2D及2E圖所示,透過例如無電解電鍍方式於該介電層23及外露於盲孔230之導電金屬層22上形成一例如薄銅之導電層24,再以一第二阻層25(例如乾膜)覆蓋該導電層24,並經曝光、顯影製程而形成有多數圖案化之開口250。
接著,透過電鍍製程,以於該外露出該第二阻層開口250之導電層24上形成導電線路261及於該盲孔230中形成導電柱262,並使該導電線路261透過該導電柱262而電性連接至該導電金屬層22。
如此即可使該導電線路261及作為電性連接終端(terminal)222之導電金屬層22利用導電柱262與該介電層23有效嵌合,減少習知脫層問題發生。
如第2F圖所示,移除該第二阻層25及其所覆蓋之導電層24部分。另於該導電線路261之終端復形成有如鎳/金之銲接材料263。
如第2G及2H圖所示,對應該導電金屬層22中作為晶片座221部分之導電線路261上接置至少一晶片27,並使該晶片27透過銲線28電性連接至該導電線路261終端之銲接材料263。
接著形成一封裝膠體29以包覆該晶片27及導電線路261,以及移除該金屬載具20,藉以外露出該介電層23及導電金屬層22。後續即可利用該作為電性連接終端(terminal)之外露導電金屬層22,透過導電材料而供晶片27與外部裝置電性連接。
透過前述之製法,本發明復揭示一種半導體封裝件,包括:導電金屬層22;介電層23,係覆蓋該導電金屬層22之一側,其中該介電層23形成有盲孔230以外露出該部分該導電金屬層22;導電線路261,係形成於該介電層23上;導電柱262,係形成於該盲孔230中,並使該導電線路261透過該導電柱262而電性連接至該導電金屬層22;晶片27,係電性連接至該導電線路261;以及封裝膠體29,係包覆該晶片27及導電線路261。
該導電線路261與該介電層23間及該導電柱262與該盲孔230間復包含有一導電層24。
該導電金屬層22係包括有對應晶片27位置之晶片座(die pad)221及供該晶片27與外部裝置電性連接之電性連接終端(terminal)222。
因此本發明之半導體封裝件及其製法主要係先在金屬載具上敷設一第一阻層,並於該第一阻層中開設多數外露出該金屬載具之開口,以於該開口中形成導電金屬層,接著移除該第一阻層,並於該金屬載具上具導電金屬層之一側覆蓋一介電層,且於該介電層中形成盲孔(blind via)以外露出部分導電金屬層,再於該介電層上形成導電線路及於該盲孔中形成導電柱,並使該導電線路透過該導電柱而電性連接至該導電金屬層,如此即可使該導電線路及作為電性連接終端(terminal)之導電金屬層利用導電柱與該介電層有效嵌合,減少習知脫層問題發生,再者於本發明中,該介電層中僅需形成小尺寸之盲孔,故可避免習知技術因形成大尺寸開口所造成製程不便及成本增加問題。之後即可將至少一晶片電性連接至該導電線路,且形成一包覆該晶片及導電線路之封裝膠體,再移除該金屬載具,藉以外露出該介電層及作為電性連接終端之導電金屬層,進而形成毋需晶片承載件之半導體封裝件。
請參閱第3A至3C圖,係為本發明之半導體封裝件及其製法第二實施例之剖視圖。本實施例之半導體封裝件及其製法大致與前述實施例大致相同,主要差異在於形成導電金屬層前,係可先於第一阻層開口中形成與金屬載具相同材質之鍍層,以於移除該金屬載具時,同時移除該鍍層,藉以使該導電金屬層內凹於該介電層中,以供接置導電元件。
如第3A圖所示,敷設一第一阻層31於金屬載具30(例如為銅板)上,並於該第一阻層31之預定部位開設多數貫穿之開口310,以外露出該金屬載具30,接著於該第一阻層開口310中先電鍍形成有與該金屬載具30相同材質(銅)之鍍層300,再於該鍍層300上電鍍形成導電金屬層32。
如第3B圖所示,移除該第一阻層31,並於該金屬載具30上形成有導電金屬層32之一側覆蓋一介電層33,並令該介電層33形成有盲孔(blind via)330以露出部分導電金屬層32,且於該介電層33上形成導電線路361及於該盲孔330中形成導電柱362,並使該導電線路361透過該導電柱362而電性連接至該導電金屬層32,俾將至少一晶片37透過銲線38電性連接至該導電線路361,再形成一包覆該晶片37及導電線路361之封裝膠體39。
如第3C圖所示,透過蝕刻製程移除該相同材質之金屬載具30及鍍層300,藉以外露出該介電層33及導電金屬層32,並使該導電金屬層32內凹於該介電層33中,以供接置如銲球之導電元件380,並使該導電元件380有效接著於該導電金屬層32上。
請參閱第4A及4B圖,係為本發明之半導體封裝件及其製法第三實施例之剖視圖。
本實施例之半導體封裝件及其製法大致與前述實施例大致相同,主要差異係在選擇導電金屬層42之材質與金屬載具40之材質相同,以於蝕刻移除該金屬載具40時,同時蝕刻部分該導電金屬層42,並控制該導電金屬層42之蝕刻量(蝕刻約10微米之深度),藉以使該導電金屬層42內凹於介電層43中,以供導電元件480有效固著於該導電金屬層42上。
請參閱第5圖,係為本發明之半導體封裝件及其製法第四實施例之剖視圖。
本實施例之半導體封裝件及其製法大致與前述實施例大致相同,主要差異係在導電線路561上覆蓋一例如拒銲層之絕緣層511,並令該絕緣層511形成有外露出部分導電線路561之開孔5110,以供晶片57以覆晶方式電性連接至該導電線路561。
上述實施例僅例示性說明本發明之原理及其功效,而非用於限制本發明,任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。
10...銅板
11...介電層
110...開口
12...銲料
13...第一薄銅層
14...第二銅層
141...終端
15...金屬層
16...晶片
17...銲線
18...封裝膠體
20...金屬載具
21...第一阻層
210...開口
22...導電金屬層
221...晶片座
222...電性連接終端
23...介電層
230...盲孔
24...導電層
25...第二阻層
250...開口
261...導電線路
262...導電柱
263...銲接材料
27...晶片
28...銲線
29...封裝膠體
30...金屬載具
300...鍍層
31...第一阻層
310...開口
32...導電金屬層
33...介電層
330...盲孔
361...導電線路
362...導電柱
37...晶片
38...銲線
380...導電元件
39...封裝膠體
40...金屬載具
42...導電金屬層
43...介電層
480...導電元件
511...絕緣層
5110...開孔
561...導電線路
57...晶片
第1A至1E圖係顯示美國專利第6,884,652號之毋需晶片承載件之半導體封裝件之製法剖視圖;第2A至2H圖係顯示本發明之半導體封裝件及其製法第一實施例之示意圖;第3A至3C圖係顯示本發明之半導體封裝件及其製法第二實施例之剖視圖;第4A及4B圖係顯示本發明之半導體封裝件及其製法第三實施例之剖視圖;以及第5圖係顯示本發明之半導體封裝件及其製法第四實施例之剖視圖。
22...導電金屬層
221...晶片座
222...電性連接終端
23...介電層
261...導電線路
262...導電柱
263...銲接材料
27...晶片
28...銲線
29...封裝膠體
Claims (22)
- 一種半導體封裝件之製法,係包括:敷設第一阻層於一金屬載具上,並於該第一阻層之預定部位開設多數貫穿之開口,以外露出該金屬載具;於該開口中形成導電金屬層,該導電金屬層係包括有電性連接終端(terminal);移除該第一阻層,並於該金屬載具上形成有導電金屬層之一側覆蓋一介電層,且令該介電層形成有複數盲孔(blind via)以露出部分導電金屬層,且各該電性連接終端係對應有複數該盲孔;於該介電層上形成導電線路及於各該盲孔中形成導電柱,並使該導電線路透過該導電柱而電性連接至該導電金屬層;將至少一晶片電性連接至該導電線路;形成一封裝膠體以包覆該晶片及導電線路;以及移除該金屬載具,藉以外露出該介電層及導電金屬層。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該第一阻層為光阻層(photo-resist),並透過曝光、顯影之方式使該第一阻層形成有外露出部分該金屬載具之貫穿開口。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該導電金屬層係包括有對應晶片位置之晶片座 (die pad)。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該導電金屬層之材質為金/鎳/銅(Au/Ni/Cu)、鎳/金(Ni/Au)、金/鎳/金(Au/Ni/Au)、金/鎳/鈀/金(Au/Ni/Pd/Au)、金/鈀/鎳/鈀(Au/Pd/Ni/Pd)之其中一者。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該介電層為玻纖浸樹脂(Prepreg,PP)及ABF(Ajinomoto Build-up Film)之其中一者,且利用雷射開孔技術以於該介電層中形成複數盲孔(blind via)。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該導電線路及導電柱之製法係包括:以無電解電鍍方式於該介電層及外露於盲孔之導電金屬層上形成一導電層;以一第二阻層覆蓋該導電層,並形成有多數圖案化之開口;透過電鍍製程,以於外露出該第二阻層開口之導電層上形成導電線路及於該盲孔中形成導電柱,並使該導電線路透過該導電柱而電性連接至該導電金屬層;以及移除該第二阻層及其所覆蓋之導電層部分。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該導電線路之終端復形成有銲接材料。
- 如申請專利範圍第7項之半導體封裝件之製法,其中,該晶片透過銲線電性連接至該導電線路終端之銲接材料。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,於形成該導電金屬層前,先於第一阻層開口中形成與金屬載具相同材質之鍍層,以於移除該金屬載具時,同時移除該鍍層,藉以使該導電金屬層內凹於該介電層中。
- 如申請專利範圍第1項之半導體封裝件之製法,復包括於外露出介電層之導電金屬層上接置導電元件。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該導電金屬層之材質與金屬載具之材質相同,以於蝕刻移除該金屬載具時,同時蝕刻部分該導電金屬層,並控制該導電金屬層之蝕刻量,以使該導電金屬層內凹於介電層中。
- 如申請專利範圍第1項之半導體封裝件之製法,其中,該導電線路上覆蓋有一絕緣層,並令該絕緣層形成有外露出部分導電線路之開孔,以供晶片以覆晶方式電性連接至該導電線路。
- 一種半導體封裝件,係包括:導電金屬層,係包括有電性連接終端(terminal);介電層,係覆蓋該導電金屬層之一側,其中該介電層形成有複數盲孔以外露出部分該導電金屬層,且 各該電性連接終端係對應有複數該盲孔;導電線路,係形成於該介電層上;導電柱,係形成於各該盲孔中,並使該導電線路透過該導電柱而電性連接至該導電金屬層;晶片,係電性連接至該導電線路;以及封裝膠體,係包覆該晶片及導電線路。
- 如申請專利範圍第13項之半導體封裝件,其中,該導電金屬層係包括有對應晶片位置之晶片座(die pad)。
- 如申請專利範圍第13項之半導體封裝件,其中,該導電金屬層之材質為金/鎳/銅(Au/Ni/Cu)、鎳/金(Ni/Au)、金/鎳/金(Au/Ni/Au)、金/鎳/鈀/金(Au/Ni/Pd/Au)、金/鈀/鎳/鈀(Au/Pd/Ni/Pd)之其中一者。
- 如申請專利範圍第13項之半導體封裝件,其中,該介電層為玻纖浸樹脂(Prepreg,PP)及ABF(Ajinomoto Build-up Film)之其中一者,且利用雷射開孔技術以於該介電層中形成複數盲孔(blind via)。
- 如申請專利範圍第13項之半導體封裝件,其中,該導電線路之終端復形成有銲接材料。
- 如申請專利範圍第17項之半導體封裝件,其中,該晶片透過銲線電性連接至該導電線路終端之銲接材料。
- 如申請專利範圍第13項之半導體封裝件,其中,該 導電金屬層內凹於該介電層中。
- 如申請專利範圍第13項之半導體封裝件,復包括於外露出介電層之導電金屬層上接置有導電元件。
- 如申請專利範圍第13項之半導體封裝件,其中,該導電線路上覆蓋有一絕緣層,並令該絕緣層形成有外露出部分導電線路之開孔,以供晶片以覆晶方式電性連接至該導電線路。
- 如申請專利範圍第13項之半導體封裝件,其中,該導電線路與該介電層間及該導電柱與該盲孔間復包含有一導電層。
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US12/287,936 US20090102063A1 (en) | 2007-10-22 | 2008-10-14 | Semiconductor package and method for fabricating the same |
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