WO2008093414A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2008093414A1 WO2008093414A1 PCT/JP2007/051601 JP2007051601W WO2008093414A1 WO 2008093414 A1 WO2008093414 A1 WO 2008093414A1 JP 2007051601 W JP2007051601 W JP 2007051601W WO 2008093414 A1 WO2008093414 A1 WO 2008093414A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- manufacturing
- same
- sealing resin
- wiring board
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000011347 resin Substances 0.000 abstract 3
- 229920005989 resin Polymers 0.000 abstract 3
- 238000007789 sealing Methods 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020097012746A KR101057368B1 (ko) | 2007-01-31 | 2007-01-31 | 반도체 장치 및 그 제조 방법 |
JP2008555983A JP5120266B6 (ja) | 2007-01-31 | 2007-01-31 | 半導体装置及びその製造方法 |
PCT/JP2007/051601 WO2008093414A1 (ja) | 2007-01-31 | 2007-01-31 | 半導体装置及びその製造方法 |
CN200780049019A CN101617400A (zh) | 2007-01-31 | 2007-01-31 | 半导体器件及其制造方法 |
US12/479,915 US8018033B2 (en) | 2007-01-31 | 2009-06-08 | Semiconductor device and manufacturing method of the same |
US13/198,986 US8497156B2 (en) | 2007-01-31 | 2011-08-05 | Semiconductor device and manufacturing method of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/051601 WO2008093414A1 (ja) | 2007-01-31 | 2007-01-31 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/479,915 Continuation US8018033B2 (en) | 2007-01-31 | 2009-06-08 | Semiconductor device and manufacturing method of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008093414A1 true WO2008093414A1 (ja) | 2008-08-07 |
Family
ID=39673734
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/051601 WO2008093414A1 (ja) | 2007-01-31 | 2007-01-31 | 半導体装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8018033B2 (ja) |
JP (1) | JP5120266B6 (ja) |
KR (1) | KR101057368B1 (ja) |
CN (1) | CN101617400A (ja) |
WO (1) | WO2008093414A1 (ja) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010441A (ja) * | 2008-06-27 | 2010-01-14 | Murata Mfg Co Ltd | 回路モジュールの製造方法および回路モジュール |
JP2011003749A (ja) * | 2009-06-19 | 2011-01-06 | Shinko Electric Ind Co Ltd | 電子装置および電子装置の製造方法 |
JP2011035058A (ja) * | 2009-07-30 | 2011-02-17 | Sharp Corp | 高周波モジュールおよび高周波モジュールが実装されたプリント配線基板 |
WO2017200103A1 (ja) * | 2016-05-20 | 2017-11-23 | 日立化成株式会社 | 離型フィルム |
CN107535081A (zh) * | 2015-05-11 | 2018-01-02 | 株式会社村田制作所 | 高频模块 |
WO2018164158A1 (ja) * | 2017-03-08 | 2018-09-13 | 株式会社村田製作所 | 高周波モジュール |
WO2018164159A1 (ja) * | 2017-03-08 | 2018-09-13 | 株式会社村田製作所 | モジュール |
WO2019230705A1 (ja) * | 2018-06-01 | 2019-12-05 | 株式会社村田製作所 | 高周波モジュール |
WO2020110578A1 (ja) * | 2018-11-30 | 2020-06-04 | 株式会社村田製作所 | モジュール |
JP2020109844A (ja) * | 2019-01-01 | 2020-07-16 | 蔡 憲 聰 | パッケージ内コンパートメントシールドを備える半導体パッケージ及びその製造方法 |
JP2021002610A (ja) * | 2019-06-24 | 2021-01-07 | 富士電機株式会社 | 半導体モジュール、車両、および半導体モジュールの製造方法 |
US10896880B2 (en) | 2018-11-28 | 2021-01-19 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
US10923435B2 (en) | 2018-11-28 | 2021-02-16 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance |
US11211340B2 (en) | 2018-11-28 | 2021-12-28 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding |
US11239179B2 (en) | 2018-11-28 | 2022-02-01 | Shiann-Tsong Tsai | Semiconductor package and fabrication method thereof |
Families Citing this family (127)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101313391B1 (ko) | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | 적층형 패키징 |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8212339B2 (en) | 2008-02-05 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8022511B2 (en) * | 2008-02-05 | 2011-09-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8350367B2 (en) | 2008-02-05 | 2013-01-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US7989928B2 (en) | 2008-02-05 | 2011-08-02 | Advanced Semiconductor Engineering Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20110180933A1 (en) * | 2008-05-30 | 2011-07-28 | Yasunori Inoue | Semiconductor module and semiconductor module manufacturing method |
US8410584B2 (en) | 2008-08-08 | 2013-04-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20100110656A1 (en) * | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US20100207257A1 (en) * | 2009-02-17 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
US8110902B2 (en) | 2009-02-19 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
JP5106460B2 (ja) * | 2009-03-26 | 2012-12-26 | 新光電気工業株式会社 | 半導体装置及びその製造方法、並びに電子装置 |
US8212340B2 (en) | 2009-07-13 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
WO2011043058A1 (ja) * | 2009-10-09 | 2011-04-14 | 住友ベークライト株式会社 | 半導体装置 |
US8368185B2 (en) * | 2009-11-19 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8030750B2 (en) | 2009-11-19 | 2011-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
TWI540698B (zh) | 2010-08-02 | 2016-07-01 | 日月光半導體製造股份有限公司 | 半導體封裝件與其製造方法 |
US9007273B2 (en) | 2010-09-09 | 2015-04-14 | Advances Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
TWI523158B (zh) * | 2010-10-11 | 2016-02-21 | 日月光半導體製造股份有限公司 | 雙面封裝結構及應用其之無線通訊系統 |
US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US8654537B2 (en) * | 2010-12-01 | 2014-02-18 | Apple Inc. | Printed circuit board with integral radio-frequency shields |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US20120162930A1 (en) * | 2010-12-23 | 2012-06-28 | Azurewave Technologies, Inc. | Module ic package structure with electrical shield function and method for making the same |
TWI525782B (zh) * | 2011-01-05 | 2016-03-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
EP2666344B1 (en) * | 2011-01-20 | 2019-03-13 | Hewlett-Packard Enterprise Development LP | Chip carrier support systems |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
JP5668627B2 (ja) * | 2011-07-19 | 2015-02-12 | 株式会社村田製作所 | 回路モジュール |
US8404520B1 (en) | 2011-10-17 | 2013-03-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8541883B2 (en) | 2011-11-29 | 2013-09-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having shielded conductive vias |
TWI474462B (zh) * | 2011-12-16 | 2015-02-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9030841B2 (en) * | 2012-02-23 | 2015-05-12 | Apple Inc. | Low profile, space efficient circuit shields |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
JP2013197209A (ja) * | 2012-03-16 | 2013-09-30 | Toshiba Corp | 半導体装置及びその製造方法 |
US8937376B2 (en) | 2012-04-16 | 2015-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with heat dissipation structures and related methods |
US8786060B2 (en) | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US8704341B2 (en) | 2012-05-15 | 2014-04-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal dissipation structures and EMI shielding |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8653634B2 (en) | 2012-06-11 | 2014-02-18 | Advanced Semiconductor Engineering, Inc. | EMI-shielded semiconductor devices and methods of making |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9153542B2 (en) | 2012-08-01 | 2015-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having an antenna and manufacturing method thereof |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
TWI570864B (zh) * | 2013-02-01 | 2017-02-11 | 英帆薩斯公司 | 具有焊線通孔的微電子封裝、其之製造方法以及用於其之硬化層 |
US8940630B2 (en) | 2013-02-01 | 2015-01-27 | Invensas Corporation | Method of making wire bond vias and microelectronic package having wire bond vias |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
US9978688B2 (en) | 2013-02-28 | 2018-05-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a waveguide antenna and manufacturing method thereof |
US9837701B2 (en) | 2013-03-04 | 2017-12-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna substrate and manufacturing method thereof |
US9129954B2 (en) | 2013-03-07 | 2015-09-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna layer and manufacturing method thereof |
US9172131B2 (en) | 2013-03-15 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor structure having aperture antenna |
US9788466B2 (en) * | 2013-04-16 | 2017-10-10 | Skyworks Solutions, Inc. | Apparatus and methods related to ground paths implemented with surface mount devices |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
CN103400825B (zh) | 2013-07-31 | 2016-05-18 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
JP6199724B2 (ja) * | 2013-12-13 | 2017-09-20 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
JP6163421B2 (ja) | 2013-12-13 | 2017-07-12 | 株式会社東芝 | 半導体装置、および、半導体装置の製造方法 |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
JP2015170770A (ja) * | 2014-03-07 | 2015-09-28 | イビデン株式会社 | プリント配線板 |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US10026701B1 (en) * | 2014-07-28 | 2018-07-17 | National Technology & Engineering Solutions Of Sandia, Llc | Electromagnetic isolation structure |
KR101616625B1 (ko) * | 2014-07-30 | 2016-04-28 | 삼성전기주식회사 | 반도체 패키지 및 그 제조방법 |
CN105321933B (zh) * | 2014-08-01 | 2019-08-09 | 乾坤科技股份有限公司 | 具有顺形电磁屏蔽结构的半导体封装件及其制造方法 |
CN104409446A (zh) * | 2014-10-24 | 2015-03-11 | 苏州日月新半导体有限公司 | 采用引线键合的仿形屏蔽结构及其制作工艺 |
JP6444707B2 (ja) * | 2014-11-28 | 2018-12-26 | Towa株式会社 | 電子部品、その製造方法及び製造装置 |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
DE112014007248T5 (de) * | 2014-12-12 | 2017-08-31 | Meiko Electronics Co., Ltd. | Gekapseltes Schaltungsmodul und Herstellungsverfahren dafür |
US9673150B2 (en) * | 2014-12-16 | 2017-06-06 | Nxp Usa, Inc. | EMI/RFI shielding for semiconductor device packages |
CN105990317A (zh) * | 2015-02-25 | 2016-10-05 | 晟碟信息科技(上海)有限公司 | 具有电磁干扰屏蔽层和半导体装置和其制造方法 |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9530749B2 (en) | 2015-04-28 | 2016-12-27 | Invensas Corporation | Coupling of side surface contacts to a circuit platform |
KR102354370B1 (ko) | 2015-04-29 | 2022-01-21 | 삼성전자주식회사 | 쉴딩 구조물을 포함하는 자기 저항 칩 패키지 |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US20170141278A1 (en) * | 2015-11-17 | 2017-05-18 | Toshiba Corporation | Led assembly for led package with sidewall electrodes |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9824979B2 (en) * | 2015-12-29 | 2017-11-21 | Stmicroelectronics, Inc. | Electronic package having electromagnetic interference shielding and associated method |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9831155B2 (en) * | 2016-03-11 | 2017-11-28 | Nanya Technology Corporation | Chip package having tilted through silicon via |
JP6524003B2 (ja) | 2016-03-17 | 2019-06-05 | 東芝メモリ株式会社 | 半導体装置 |
US9953929B2 (en) | 2016-03-18 | 2018-04-24 | Intel Corporation | Systems and methods for electromagnetic interference shielding |
US9793222B1 (en) * | 2016-04-21 | 2017-10-17 | Apple Inc. | Substrate designed to provide EMI shielding |
US10373916B2 (en) * | 2016-07-28 | 2019-08-06 | Universal Scientific Industrial (Shanghai) Co., Ltd. | Semiconductor device packages |
US9935075B2 (en) * | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10546819B2 (en) | 2016-09-15 | 2020-01-28 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
KR20230132883A (ko) | 2016-10-04 | 2023-09-18 | 스카이워크스 솔루션즈, 인코포레이티드 | 오버몰드 구조체를 갖는 양면 라디오-주파수 패키지 |
JP7039224B2 (ja) * | 2016-10-13 | 2022-03-22 | 芝浦メカトロニクス株式会社 | 電子部品の製造装置及び電子部品の製造方法 |
US9953930B1 (en) | 2016-10-20 | 2018-04-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
EP3486944A1 (en) * | 2017-09-14 | 2019-05-22 | Shenzhen Goodix Technology Co., Ltd. | Chip packaging structure and method, and electronic device |
CN109509736A (zh) * | 2017-09-14 | 2019-03-22 | 晨星半导体股份有限公司 | 电路板及芯片封装体 |
US10157834B1 (en) * | 2017-09-18 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electronic apparatus |
JP6635605B2 (ja) * | 2017-10-11 | 2020-01-29 | 国立研究開発法人理化学研究所 | 電流導入端子並びにそれを備えた圧力保持装置及びx線撮像装置 |
JP2023130249A (ja) * | 2022-03-07 | 2023-09-20 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000200859A (ja) * | 1998-12-31 | 2000-07-18 | Anam Semiconductor Inc | チップサイズ半導体パッケ―ジ及びその集合体並びにその製造方法 |
JP2003174122A (ja) * | 2001-12-04 | 2003-06-20 | Toshiba Corp | 半導体装置 |
JP2003249607A (ja) * | 2002-02-26 | 2003-09-05 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03120740A (ja) | 1989-10-04 | 1991-05-22 | Hitachi Ltd | 半導体チップのためのパッケージ、パッケージの着脱方法および検査方法、並びに、治具 |
US6541872B1 (en) * | 1999-01-11 | 2003-04-01 | Micron Technology, Inc. | Multi-layered adhesive for attaching a semiconductor die to a substrate |
JP2001007252A (ja) | 1999-06-25 | 2001-01-12 | Matsushita Electronics Industry Corp | 半導体装置およびその製造方法 |
JP2001244688A (ja) | 2000-02-28 | 2001-09-07 | Kyocera Corp | 高周波モジュール部品及びその製造方法 |
JP2004111656A (ja) | 2002-09-18 | 2004-04-08 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US7187060B2 (en) * | 2003-03-13 | 2007-03-06 | Sanyo Electric Co., Ltd. | Semiconductor device with shield |
US7030469B2 (en) * | 2003-09-25 | 2006-04-18 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package and structure thereof |
JP4761524B2 (ja) * | 2004-09-28 | 2011-08-31 | キヤノン株式会社 | プリント配線板及びプリント回路板 |
JP4489575B2 (ja) * | 2004-12-17 | 2010-06-23 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US7671468B2 (en) * | 2005-09-30 | 2010-03-02 | Tdk Corporation | Light emitting apparatus |
US7928538B2 (en) * | 2006-10-04 | 2011-04-19 | Texas Instruments Incorporated | Package-level electromagnetic interference shielding |
-
2007
- 2007-01-31 WO PCT/JP2007/051601 patent/WO2008093414A1/ja active Application Filing
- 2007-01-31 CN CN200780049019A patent/CN101617400A/zh active Pending
- 2007-01-31 KR KR1020097012746A patent/KR101057368B1/ko active IP Right Grant
- 2007-01-31 JP JP2008555983A patent/JP5120266B6/ja not_active Expired - Fee Related
-
2009
- 2009-06-08 US US12/479,915 patent/US8018033B2/en not_active Expired - Fee Related
-
2011
- 2011-08-05 US US13/198,986 patent/US8497156B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000200859A (ja) * | 1998-12-31 | 2000-07-18 | Anam Semiconductor Inc | チップサイズ半導体パッケ―ジ及びその集合体並びにその製造方法 |
JP2003174122A (ja) * | 2001-12-04 | 2003-06-20 | Toshiba Corp | 半導体装置 |
JP2003249607A (ja) * | 2002-02-26 | 2003-09-05 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
Cited By (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010441A (ja) * | 2008-06-27 | 2010-01-14 | Murata Mfg Co Ltd | 回路モジュールの製造方法および回路モジュール |
JP2011003749A (ja) * | 2009-06-19 | 2011-01-06 | Shinko Electric Ind Co Ltd | 電子装置および電子装置の製造方法 |
JP2011035058A (ja) * | 2009-07-30 | 2011-02-17 | Sharp Corp | 高周波モジュールおよび高周波モジュールが実装されたプリント配線基板 |
US10772244B2 (en) | 2015-05-11 | 2020-09-08 | Murata Manufacturing Co., Ltd. | High-frequency module |
CN107535081A (zh) * | 2015-05-11 | 2018-01-02 | 株式会社村田制作所 | 高频模块 |
JPWO2016181954A1 (ja) * | 2015-05-11 | 2018-02-15 | 株式会社村田製作所 | 高周波モジュール |
JP7120295B2 (ja) | 2015-05-11 | 2022-08-17 | 株式会社村田製作所 | 高周波モジュール |
JP2021061412A (ja) * | 2015-05-11 | 2021-04-15 | 株式会社村田製作所 | 高周波モジュール |
WO2017200103A1 (ja) * | 2016-05-20 | 2017-11-23 | 日立化成株式会社 | 離型フィルム |
JPWO2017200103A1 (ja) * | 2016-05-20 | 2019-04-18 | 日立化成株式会社 | 離型フィルム |
WO2018164159A1 (ja) * | 2017-03-08 | 2018-09-13 | 株式会社村田製作所 | モジュール |
CN110392923A (zh) * | 2017-03-08 | 2019-10-29 | 株式会社村田制作所 | 高频模块 |
WO2018164158A1 (ja) * | 2017-03-08 | 2018-09-13 | 株式会社村田製作所 | 高周波モジュール |
JPWO2018164158A1 (ja) * | 2017-03-08 | 2019-12-19 | 株式会社村田製作所 | 高周波モジュール |
US11183465B2 (en) | 2017-03-08 | 2021-11-23 | Murata Manufacturing Co., Ltd. | Radio-frequency module |
US10999956B2 (en) | 2017-03-08 | 2021-05-04 | Murata Manufacturing Co., Ltd. | Module |
JP7010372B2 (ja) | 2018-06-01 | 2022-01-26 | 株式会社村田製作所 | 高周波モジュール |
JPWO2019230705A1 (ja) * | 2018-06-01 | 2021-04-08 | 株式会社村田製作所 | 高周波モジュール |
WO2019230705A1 (ja) * | 2018-06-01 | 2019-12-05 | 株式会社村田製作所 | 高周波モジュール |
US11348894B2 (en) | 2018-06-01 | 2022-05-31 | Murata Manufacturing Co., Ltd. | High-frequency module |
US10923435B2 (en) | 2018-11-28 | 2021-02-16 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance |
US10896880B2 (en) | 2018-11-28 | 2021-01-19 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
US11211340B2 (en) | 2018-11-28 | 2021-12-28 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding |
US11239179B2 (en) | 2018-11-28 | 2022-02-01 | Shiann-Tsong Tsai | Semiconductor package and fabrication method thereof |
WO2020110578A1 (ja) * | 2018-11-30 | 2020-06-04 | 株式会社村田製作所 | モジュール |
US11749589B2 (en) | 2018-11-30 | 2023-09-05 | Murata Manufacturing Co., Ltd. | Module |
JP2020109844A (ja) * | 2019-01-01 | 2020-07-16 | 蔡 憲 聰 | パッケージ内コンパートメントシールドを備える半導体パッケージ及びその製造方法 |
JP2021002610A (ja) * | 2019-06-24 | 2021-01-07 | 富士電機株式会社 | 半導体モジュール、車両、および半導体モジュールの製造方法 |
JP7367352B2 (ja) | 2019-06-24 | 2023-10-24 | 富士電機株式会社 | 半導体モジュール、車両、および半導体モジュールの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20090236700A1 (en) | 2009-09-24 |
KR101057368B1 (ko) | 2011-08-18 |
JP5120266B6 (ja) | 2018-06-27 |
US20110294261A1 (en) | 2011-12-01 |
CN101617400A (zh) | 2009-12-30 |
JP5120266B2 (ja) | 2013-01-16 |
US8497156B2 (en) | 2013-07-30 |
JPWO2008093414A1 (ja) | 2010-05-20 |
KR20090087076A (ko) | 2009-08-14 |
US8018033B2 (en) | 2011-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2008093414A1 (ja) | 半導体装置及びその製造方法 | |
WO2008146243A3 (en) | An electronic device comprising a convertible structure, and a method of manufacturing an electronic device | |
WO2008018959A3 (en) | Overmolded semiconductor package with a wirebond cage for emi shielding | |
TW200723457A (en) | Semiconductor device and method for manufacturing semiconductor device | |
TW200739972A (en) | Light-emitting device and method for manufacturing the same | |
TW200644297A (en) | Semiconductor apparatus and manufacturing method thereof | |
WO2009044863A1 (ja) | モジュール、配線板、及びモジュールの製造方法 | |
WO2008105496A1 (ja) | キャパシタ搭載インターポーザ及びその製造方法 | |
SG153729A1 (en) | Integrated circuit package system for shielding electromagnetic interference | |
WO2007050287A3 (en) | Semiconductor structure and method of assembly | |
WO2008118230A3 (en) | Large area circuiry using appliques | |
DE502008000072D1 (de) | Schaltungsanordnung mit Verbindungseinrichtung sowie Herstellungsverfahren hierzu | |
WO2008112101A3 (en) | Packaging methods for imager devices | |
WO2009002381A3 (en) | Mold compound circuit structure for enhanced electrical and thermal performance | |
WO2008146793A1 (ja) | 電気装置、接続方法及び接着フィルム | |
WO2006094025A3 (en) | Fabricated adhesive microstructures for making an electrical connection | |
WO2009037523A3 (en) | An antenna arrangement, a method for manufacturing an antenna arrangement and a printed wiring board for use in an antenna arrangement | |
TW200631059A (en) | Semiconducor device and manufacturing method thereof | |
WO2009054098A1 (ja) | 部品内蔵配線基板および部品内蔵配線基板の製造方法 | |
WO2009069551A1 (ja) | 光電変換素子用電極基板 | |
WO2009050891A1 (ja) | 実装構造体 | |
TW200802743A (en) | High frequency device module and method for manufacturing the same | |
WO2009048154A1 (ja) | 半導体装置及びその設計方法 | |
WO2009028807A3 (en) | Light emitting device package and method for fabricating the same | |
TW200741970A (en) | Method for manufacturing semiconductor device and semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200780049019.3 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07707787 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2008555983 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020097012746 Country of ref document: KR |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 07707787 Country of ref document: EP Kind code of ref document: A1 |