TWI474462B - 半導體封裝件及其製法 - Google Patents
半導體封裝件及其製法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
本發明係關於一種半導體封裝件,更詳言之,本發明係為一種防電磁干擾之半導體封裝件及其製法。
隨著電子產品輕薄短小及系統整合的趨勢,現今已發展出一種系統級封裝(System in package;SIP),將一個或多個晶片、被動元件等不同的電子元件整合在同一個封裝件中,當整合之元件含有射頻(Radio frequency,RF)元件或其他電磁元件,容易造成鄰近其他電子元件之電磁干擾(Electromagnetic Interference簡稱EMI),且封裝件中的電子元件積集度日益增加,使得各該電子元件之間的相對位置越來越靠近,故各該電子元件之間的EMI問題更顯重要。
第7701040號美國專利係揭露一種防電磁干擾之半導體封裝件,如第1圖所示,於一承載件10上形成具有屏蔽層11之複數基板12,且各該基板12上設有複數封裝體,如射屏(RF)單元16a與基頻(base band)單元16b,而各該基板12之側邊具有電性連接墊120以供結合銲錫凸塊,又於該基板12之邊緣、射屏單元16a及基頻單元16b上鍍覆另一屏蔽層13。最後,移除該承載件10,以獲取複數個半導體封裝件1。
惟,習知半導體封裝件1中,該屏蔽層13不能形成於該電性連接墊120上,否則會造成短路,故於該電性連接墊120上先形成光阻,待形成屏蔽層13之後,移除該光阻以外露電性連接墊120,致使製程繁雜且增加製程時間,導致製作成本提高。
然而,如何克服習知技術之種種問題,實為一重要課題。
為解決上述習知技術之種種問題,本發明遂揭露一種半導體封裝件,係包括:載板;複數封裝體,係設於該載板上;擋架,係設於該載板上,並位於該些封裝體之間;封裝膠體,係形成於該載板上,以包覆該些封裝體與該擋架,並令該擋架之部分表面外露於該封裝膠體;以及屏蔽元件,係電性連接該擋架。
本發明復提供一種半導體封裝件之製法,係包括:提供一載板;形成複數封裝體於該載板上;設置擋架於該些封裝體之間;形成封裝膠體於該載板上,以包覆該些封裝體與該擋架,並令該擋架之部分表面外露於該封裝膠體;以及將一屏蔽元件電性連接該擋架。
前述之半導體封裝件及其製法,該屏蔽元件係可為以濺鍍方式形成於該封裝體上之金屬層。亦或,該屏蔽元件可為金屬蓋,蓋設於該封裝體上。
前述之半導體封裝件及其製法,形成該擋架之材質可為導電材,且該擋架可具有擋板,以藉之立設於該載板上並位於各該封裝體之間。
另外,前述之半導體封裝件及其製法,該封裝體可為半導體晶片或具有半導體晶片之封裝結構。
由上可知,本發明半導體封裝件及其製法,係藉由屏蔽元件形成於該封裝膠體上,且藉由該擋架與該屏蔽元件作為屏蔽結構,故相較於習知技術,本發明之封裝體周圍均有屏蔽結構,因而可有效防止外界電磁波干擾該些封裝體之內部電路。
再者,藉由該擋架之設計及屏蔽元件形成於該封裝膠體上,因而無需考量該載板之線路佈設,故相較於習知技術,本發明之製程更簡易,且製程時間更短,因而可降低製作成本。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“側”、“二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
以下即配合第2A至2D圖詳細說明本發明之半導體封裝件2之製法。
如第2A圖所示,提供一載板20,且形成第一及第二封裝體22a,22b於該載板20上,該第一及第二封裝體22a,22b並以銲球202電性連接該載板20。應瞭解的是該載板20上可形成更多封裝體,在本實施例中僅藉第2A圖之封裝體作例示說明。
於本實施例中,該載板20係為線路板,而該些封裝體係為封裝結構,可具有電性連接該載板20之封裝基板220a,220b及設於該封裝基板220a,220b上之第一與第二晶片221a,221b,且該第一與第二晶片221a,221b可藉由銲線222a或銲錫凸塊222b電性連接該封裝基板220a,220b,並以封裝膠體223包覆該第一與第二晶片221,221b、銲線222a與銲錫凸塊222b。於其它實施例中,該封裝體可為半導體晶片。
再者,有關載板20與封裝基板220a,220b之種類繁多,且為業界所熟知,故不再贅述,特此述明。
又,有關該封裝體之內部結構因種類繁多,且為業界所熟知,故並不限於上述,亦可為其他態樣,特此述明。
另外,該第一及第二封裝體22a,22b之態樣可為射屏(RF)模組,例如:無線區域網路(Wireless LAN,WLAN)、全球定位系統(Global Positioning System,GPS)、藍芽(Bluetooth)或手持式視訊廣播(Digital Video Broadcasting-Handheld,DVB-H)、調頻(FM)等無線通訊模組。
如第2B圖所示,設置擋架26於該第一與第二封裝體22a,22b之間。
於本實施例中,形成該擋架26之材質為導電材,如銅、金、鎳或鋁等之金屬,且該擋架26具有擋板260,以立設於該載板20上並位於該第一與第二封裝體22a,22b之間,用以遮蔽該些封裝體的側壁,可避免該第一與第二封裝體22a,22b之電磁相互干擾,使該第一與第二晶片221a,221b可保持應有的功效。
如第2C圖所示,形成封裝膠體27於該載板20上,以包覆該擋架26與該第一與第二封裝體22a,22b,且令該擋架26之部分表面外露於該封裝膠體27。
於本實施例中,係以模壓製程(Injection Molding)形成該封裝膠體27,且藉由該封裝膠體27可保護該些封裝體避免遭受環境汙染、氧化或破壞。
再者,該封裝膠體27可藉由例如雷射鑽孔形成開口270以外露該擋架26,如第2C圖所示;亦可如第2C’圖所示,使該封裝膠體27’與該擋架26之頂面齊平,以令該擋架26外露於該封裝膠體27’。
如第2D圖所示,接續第2C圖之製程,將一屏蔽元件28電性連接該擋架26。
於本實施例中,該屏蔽元件28係為利用濺鍍(sputtering deposition)之方式形成於該封裝膠體27上之屏蔽層,且該部分屏蔽層係形成於該開口270中以連接該擋架26之外露部分。又形成該屏蔽元件28之材質為導電材,如金屬或導電膠,但不以此為限。
於另一實施例中,如第2D’圖所示,提供一金屬蓋作為屏蔽元件28’,以蓋設於該封裝膠體27’上(如圖中之箭頭方向),並電性連接該擋架26之頂面外露部分。
本發明之半導體封裝件2,2’之製法,係藉由該擋架26與該屏蔽元件28,28’相互連接以形成雙重屏蔽結構,使第一與第二封裝體22a,22b之周圍均有屏蔽結構,不僅有效防止該第一與第二封裝體22a,22b之間的電磁波相互干擾,且有效防止外界電磁波干擾該第一與第二封裝體22a,22b之內部電路。
再者,藉由形成屏蔽元件28,28’於該封裝膠體27,27’上,故無需考量該載板20之線路佈設,亦即該屏蔽元件28,28’不會造成短路,不僅使製程更簡易,且縮短製程時間,因而有效降低製作成本。
請參閱第3A至3B圖,係本發明半導體封裝件之製法之另一實施例。本實施例與上述實施例之差異在於封裝體之數量與該封裝膠體之頂面高度,其它相關製程均相同,故不再贅述相同製程,僅說明相異處。
如第3A圖所示,於該載板20上設置三組封裝體32a,32b,32c,且該擋架36之擋板360係依該些封裝體32a,32b,32c之位置作設計。
如第3B圖所示,形成封裝膠體37於該載板20上,以包覆該擋架36與該些封裝體32a,32b,32c,且該封裝膠體37之頂面低於該擋架36之頂面,以外露該擋架36之頂面。後續製程請參考第2D圖之製程。
綜上所述,本發明之半導體封裝件及其製法中,係藉由形成屏蔽元件於該封裝膠體上,且藉由該擋架與該屏蔽元件作為屏蔽結構,不僅防止該些封裝體之間的電磁波相互干擾,且有效防止外界電磁波干擾該些封裝體之內部電路。
再者,藉由該擋架取代鍍覆製程及屏蔽元件形成於該封裝膠體上,因而無須考量該載板之線路佈設,故使本發明之製程更簡易,且可縮短製程時間,因而有效達到降低製作成本之目的。
上述該些實施樣態僅例示性說明本發明之功效,而非用於限制本發明,任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述該些實施態樣進行修飾與改變。此外,在上述該些實施態樣中之元件的數量僅為例示性說明,亦非用於限制本發明。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
1,2,2’...半導體封裝件
10...承載件
11、13...屏蔽層
12...基板
120...電性連接墊
16a...射頻單元
16b...基頻單元
20...載板
202...銲球
22a...第一封裝體
22b...第二封裝體
220a,220b...封裝基板
221a...第一晶片
221b...第二晶片
222a...銲線
222b...銲錫凸塊
223,27,27’,37...封裝膠體
26,36...擋架
260,360...擋板
270...開口
28,28’...屏蔽元件
32a,32b,32c...封裝體
第1圖係顯示第7701040號美國專利之半導體封裝件之製法之剖面示意圖;
第2A至2D圖係為本發明半導體封裝件之剖面示意圖;其中,第2C’及2D’圖係為第2C及2D圖之其他實施例;以及
第3A至3B圖係為本發明半導體封裝件之另一實施例之立體示意圖。
2...半導體封裝件
20...載板
22a...第一封裝體
22b...第二封裝體
221a...第一晶片
221b...第二晶片
26...擋架
27...封裝膠體
28...屏蔽元件
Claims (8)
- 一種半導體封裝件,係包括:載板;複數封裝體,係設於該載板上;擋架,係設於該載板上,並位於該些封裝體之間,且形成該擋架之材質係為導電材;封裝膠體,係形成於該載板上,以包覆該些封裝體與該擋架,並令該擋架之部分表面外露於該封裝膠體;以及屏蔽元件,係為金屬蓋且電性連接該擋架,並蓋設於該封裝體上。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該屏蔽元件係為形成於該封裝體上之導電層。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該擋架係具有擋板,以立設於該載板上並位於各該封裝體之間。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該封裝體係為半導體晶片或具有半導體晶片之封裝結構。
- 一種半導體封裝件之製法,係包括:提供一載板;形成複數封裝體於該載板上;設置擋架於該些封裝體之間,且形成該擋架之材質係為導電材; 形成封裝膠體於該載板上,以包覆該些封裝體與該擋架,並令該擋架之部分表面外露於該封裝膠體;以及將為金屬蓋之屏蔽元件電性連接該擋架,並蓋設於該封裝體上。
- 如申請專利範圍第5項所述之半導體封裝件之製法,其中,該屏蔽元件係為以濺鍍方式形成於該封裝體上之導電層。
- 如申請專利範圍第5項所述之半導體封裝件之製法,其中,該擋架係具有擋板,以立設於該載板上並位於各該封裝體之間。
- 如申請專利範圍第5項所述之半導體封裝件之製法,其中,該封裝體係為半導體晶片或具有半導體晶片之封裝結構。
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CN105336629B (zh) * | 2014-08-08 | 2018-11-27 | 日月光半导体制造股份有限公司 | 电子封装模块的制造方法以及电子封装模块 |
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