CN106206547B - 一种集成电路封装结构及其制造方法 - Google Patents
一种集成电路封装结构及其制造方法 Download PDFInfo
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- CN106206547B CN106206547B CN201610558807.6A CN201610558807A CN106206547B CN 106206547 B CN106206547 B CN 106206547B CN 201610558807 A CN201610558807 A CN 201610558807A CN 106206547 B CN106206547 B CN 106206547B
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000003292 glue Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 238000007711 solidification Methods 0.000 claims description 6
- 230000008023 solidification Effects 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000004519 grease Substances 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 7
- 239000004020 conductor Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (7)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811005785.6A CN109524387A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构的制造方法 |
CN201811005780.3A CN109461719A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构 |
CN201610558807.6A CN106206547B (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610558807.6A CN106206547B (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构及其制造方法 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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CN201811005785.6A Division CN109524387A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构的制造方法 |
CN201811005780.3A Division CN109461719A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构 |
Publications (2)
Publication Number | Publication Date |
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CN106206547A CN106206547A (zh) | 2016-12-07 |
CN106206547B true CN106206547B (zh) | 2018-10-02 |
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Application Number | Title | Priority Date | Filing Date |
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CN201610558807.6A Active CN106206547B (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构及其制造方法 |
CN201811005780.3A Pending CN109461719A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构 |
CN201811005785.6A Pending CN109524387A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构的制造方法 |
Family Applications After (2)
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CN201811005780.3A Pending CN109461719A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构 |
CN201811005785.6A Pending CN109524387A (zh) | 2016-07-17 | 2016-07-17 | 一种集成电路封装结构的制造方法 |
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CN (3) | CN106206547B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110286367B (zh) * | 2019-07-03 | 2020-07-17 | 江西亿施客传感器有限公司 | 一种小型化微波传感器 |
CN111050534B (zh) * | 2019-12-19 | 2022-02-18 | Oppo广东移动通信有限公司 | 基板组件、网络设备 |
CN111490019B (zh) * | 2020-04-24 | 2022-01-07 | 天津恒立远大仪表股份有限公司 | 一种集成电路结构及其制造方法 |
CN114267664A (zh) * | 2020-09-16 | 2022-04-01 | 鹏鼎控股(深圳)股份有限公司 | 封装电路结构及其制作方法 |
CN114038836A (zh) * | 2021-11-24 | 2022-02-11 | 苏州科阳半导体有限公司 | 一种半导体芯片的封装结构及封装方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101118890A (zh) * | 2006-08-03 | 2008-02-06 | 国际商业机器公司 | 带有集成无源元件的硅基封装装置 |
CN103313175A (zh) * | 2012-03-16 | 2013-09-18 | 美律电子(深圳)有限公司 | 微机电麦克风封装模块 |
CN104701273A (zh) * | 2015-03-27 | 2015-06-10 | 江阴长电先进封装有限公司 | 一种具有电磁屏蔽功能的芯片封装结构 |
CN104882416A (zh) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | 具有堆叠式封装能力的半导体封装件及其制作方法 |
CN204720447U (zh) * | 2015-06-19 | 2015-10-21 | 江苏长电科技股份有限公司 | 一种凹槽基板的电磁屏蔽模组封装结构 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010263080A (ja) * | 2009-05-07 | 2010-11-18 | Denso Corp | 半導体装置 |
TWI474462B (zh) * | 2011-12-16 | 2015-02-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
CN103219324A (zh) * | 2012-01-18 | 2013-07-24 | 刘胜 | 堆叠式半导体芯片封装结构及工艺 |
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2016
- 2016-07-17 CN CN201610558807.6A patent/CN106206547B/zh active Active
- 2016-07-17 CN CN201811005780.3A patent/CN109461719A/zh active Pending
- 2016-07-17 CN CN201811005785.6A patent/CN109524387A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101118890A (zh) * | 2006-08-03 | 2008-02-06 | 国际商业机器公司 | 带有集成无源元件的硅基封装装置 |
CN103313175A (zh) * | 2012-03-16 | 2013-09-18 | 美律电子(深圳)有限公司 | 微机电麦克风封装模块 |
CN104882416A (zh) * | 2013-11-13 | 2015-09-02 | 钰桥半导体股份有限公司 | 具有堆叠式封装能力的半导体封装件及其制作方法 |
CN104701273A (zh) * | 2015-03-27 | 2015-06-10 | 江阴长电先进封装有限公司 | 一种具有电磁屏蔽功能的芯片封装结构 |
CN204720447U (zh) * | 2015-06-19 | 2015-10-21 | 江苏长电科技股份有限公司 | 一种凹槽基板的电磁屏蔽模组封装结构 |
Also Published As
Publication number | Publication date |
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CN109461719A (zh) | 2019-03-12 |
CN106206547A (zh) | 2016-12-07 |
CN109524387A (zh) | 2019-03-26 |
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Effective date of registration: 20180828 Address after: 325600 Yuhong Road, Hongqiao Town, Yueqing, Zhejiang Province, No. 14 Applicant after: Gao Yanni Address before: 226300 266 Century Avenue, Nantong hi tech Zone, Nantong, Jiangsu Applicant before: Wang Peipei |
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Effective date of registration: 20190618 Address after: 226000 West Group 8 of Sun Liqiao Village, Xingdong Town, Tongzhou District, Nantong City, Jiangsu Province Patentee after: Nantong Hualong microelectronics Limited by Share Ltd Address before: 325600 Yuhong Road, Hongqiao Town, Yueqing, Zhejiang Province, No. 14 Patentee before: Gao Yanni |