201214650 ' 六、發明說明： • · 【發明所屬之技術領域】 本發明係有關於經封裝之半導體裝置，特別係有關於 一種全罩式屏蔽至接地銲球之晶片封裝構造。 【先前技術】 隨著電子元件的運算速度越來越高'或是資訊傳遞的 訊號頻率越來越高，對於電磁干擾（electr〇magnetie interference，EMI)之防護的要求也必須不斷的提升。其 是由於積體電路容易與其他内部或外部電子元件 (electronic device)相互產生電磁干擾之現象，例如串擾 (cross talk)、傳輸損耗（transmission loss)與訊號反射等 等’使得積體電路的運作效能受到削減，故如何保護晶 片封裝構造中的積體電路晶片不受電磁干擾以達到品質 要求相對顯得重要。 習知係將電磁屏蔽層連接至接地之結構設置於基板 φ 内’例如我國專利證書號數1287433號所揭示者。在基 板内部係預先形成有接地層，並使接地線路延伸於至基 板上表面之側邊，透過導通孔（via)或可稱為鍍通孔（PTH) 使接地線路電性連接至基板下表面。在封裝之後，另以 一電磁干擾屏蔽層形成在封膠體表面並連接至該接地線 路’以將電磁波或靜電導引至接地迴路予以釋放、排散， 藉以保護晶片不受電磁干擾的影響。然此基板需要額外 增設對應之接地線路至該基板之側邊，而相對提高製作 成本。此外’利用電磁干擾屏蔽層去連接基板侧面之接 201214650 地線路，然基板側面之接地線路顯露端面是有限的、窄 小的（narrow)，故與電磁干擾屏蔽層之接觸面積為點狀 之接合，容易造成接地線路接觸不良而造成電磁屏蔽失 敗。 另有人在屏蔽接地之晶片封裝構造中提出一種基板 改善結構，例如我國專利公開公報編號2〇丨〇〇59丨丨所揭 不者。必須在封裂過程中，先在基板單義出一鄰近 φ於基板單元之周邊設置的切除部，在封裝之前，將接地 元件設置於原切除部的凹槽内且延伸於基板單元的上表 面與下表面之間。在封裳之後’於單體化切割時令接地 兀件露出側向之連接面’再將電磁干擾防護體電性連接 接地元件之連接面，藉由接地元件提供一電性路徑以將 電磁干擾防護體上的電磁放射放電至接地端。利用此方 法接地兀件與電磁干擾防護體之結合面積雖然增加 了但接地兀件之設計、製作與切割製成步驟複雜而繁 • 瑣，而增加了製造成本與時間。 【發明内容】 贫月之主要目的係在於提供一種全罩 屏蔽至接地鲜球之晶 來之曰曰片封裝構造，令在封膠體表面之 罩式屏蔽層跳過基板之接地線路而直接連接至接地 球，藉以改善封裝構造之電性效能。 本發明之次-目的係在於提供一種全罩式屏蔽至 地辉球之晶片封裝構 ^ 碩保全罩式屏蔽層的接地 接’又不需要改變基板之線路結構。 201214650 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種全罩式屏蔽至接地銲球之 晶片封裝構造’包含一基板、至少一晶片、一封膠體、 複數個銲球、一電磁干擾屏蔽層以及一底面導線。該基 板係具有一上表面、一下表面與複數個侧邊，該基板之 該下表面係設有複數個接球墊與一銲罩層，該些接球墊 係包含至少一接地墊 '該晶片係設置於該基板上且電性 Φ 連接至該基板。該封膠體係形成於該基板之該上表面， 以包覆該晶片。該些銲球係接合至該基板之該些接球 塾’該些銲球係包含至少一位於該接地墊之接地銲球。 該電磁干擾屏蔽層係包覆該封膠體之一頂面與四周侧 面’更延伸至該基板之該些側邊。該底面導線係形成於 該銲罩層上’該底面導線係由該基板鄰近該接地墊之其 中一側邊連接該電磁干擾屏蔽層至該接地銲球，以提供 電磁干擾屏蔽。 • 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的晶片封裝構造中，該電磁干擾屏蔽層係可為 表面塗佈之導電漆層。 在前述的晶片封裝構造中，該基板係可不具有延伸至 該些侧邊之接地線路。 在前述的晶片封裝構造中，該底面導線之一端係可局 部覆蓋該接地墊’以供該接地銲球之接合。 在前述的晶片封裝構造中，該晶片之—主 土動面係可貼 201214650 附至該基板之該上表面，該基板係可更具有一貫穿槽 孔’以顯露該晶片複數個位於該主動面之銲墊。 在前述的晶片封裝構造中，可另包含複數個穿過該貫 穿槽孔之電性連接元件，以電性連接該些銲墊至該基板。 在前述的晶片封裝構造中，該些電性連接元件係可為 打線形成之銲線》 由以上技術方案可以看出，本發明之全罩式屏蔽至接 筆地銲球之晶片封裝構造，具有以下優點與功效： -、可藉由電磁干擾屏蔽層與底面導線之特殊組合關係 作為其中之-技術手段，利用電磁干擾屏蔽層包覆 封膠體之頂面與四周側面，更延伸至基板之側邊， 再利用在料層表面之底面導線連接至接地銲球， 令在封膠體表面之全罩式屏蔽層跳過基板之接地線 路而直接連接至接地銲球’藉以改善封裝構造之電 性效能》 底面導線之特殊組合關係 能從晶片封裝構造外部形 可藉由電磁干擾屏蔽層與 作為其中之一技術手段， 成接地之底面導線，碟你各罢 崎保全罩式屏蔽層的接地連接 又不需要改變基板之線路結構。 【實施方式】 以下將配合所附圖示詳乡却日日士 孑細說明本發明之實施例，然應 注意的是’該些圖示均為筋外+ __土 馬簡化之不意圖，僅以示意方法 來說明本發明之基本架構咬實雜 诉次貫施方法，故僅顯示與本案 有關之元件與組合關係，圖φ _ 圖中所顯不之兀件並非以實際[s】 6 201214650 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為二種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種全罩式屏蔽至接 地銲球之晶片封裝構造舉例說明於第卜2圖之截面示意 圖與第3圖之局部底面示意圖。該晶片封裝構造⑽主 要包含一基板no、至少一晶片120、一封膠體13〇、複 數個銲球14〇、—電磁干擾屏蔽& 15()以及—底面導線 16〇。在本實施例第i圖中，雖以窗口型球柵陣列封裝型 態為例’但不受局限地，本發明亦可運用在其它已知的 球柵陣列封裝架構或是覆晶封裝架構。 請參閱第1圖所示，該基板11〇係用以提供電性連接 並作為該晶片封裝構造刚之晶片載體，通常是印刷電 路板，或可為Μ載板、電路薄膜或是―鑛切型態封裝 之無外接腳式導線架m 110係具有一上表面⑴、 一:表面112與複數個側邊113,該上表面ιη係為晶 片《又置面，並作為被該封膠冑130覆蓋之表面，而該下 表面112係為顯露於該封膠體13〇之外且相對於該上表 面Hi之外表面，作為該些銲球14G的安裝面。該基板 係可為複數個一體形成之一基板條（subsuate P)後續再予以單體化切割以製成複數個晶片封裝構 也1刀。丨i後之該基板i i 0係真有複數個經單體化切叼 為顯露之側邊⑴，通常為四面連接該上表面⑴之周 201214650 邊至該下表面112之周邊，而使該基板no為矩形或正 方形。在本實施例中，該基板110係可不具有延伸至該 些側邊113之接地線路’故該基板110内部為原有金屬 線路層之結構。較佳地，該基板110可選用一種僅具有 單面線路層之電路基板’可省去接地金屬層佈局之複雜 度與製程困擾’提高訊號處理高速化，並降低基板之製 作成本。 再如第1圖所示’該基板110之該下表面U2係設有 複數個接球墊114與一銲罩層115，該些接球塾114係 包含至少一接地墊116。該銲罩層115係可為一保護線 路之絕緣性表面塗層，可稱之為綠漆，或可為其它具防 銲特性之表面保護層。在本實施例中，該銲罩層丨丨5係 形成於該基板110之該下表面112並局部覆蓋該些接球 墊114(包含該接地塾116)’能防土線路及基板核心層外 露而被污染。該接地墊116係可為虛置墊（dummy pad) 而不具有訊號傳遞功能’或者是以接地線路連接至外部 印刷電路板之金屬墊。 再如第1圖所示，該晶片120係設置於該基板110上 且電性連接至該基板11 0。該晶片1 20係可為一基頻晶 片（base band chip)或一射頻晶片（RF chip)，可由一晶圓 (wafer)分割而出。在本實施例中，該晶片12〇之一主動 面121係可貼附至該基板11〇之該上表面m，該基板 110係可更具有一貫穿槽孔117，以顯露該晶片120複數 個位於該主動面121之銲墊122。該貫穿槽孔117係可201214650 ' VI. Description of the Invention: • Technical Field of the Invention The present invention relates to a packaged semiconductor device, and more particularly to a chip package structure for a full-mask shield to ground ball. [Prior Art] As the computing speed of electronic components is getting higher or higher, or the signal frequency of information transmission is getting higher and higher, the requirements for protection against electromagnetic interference (EMI) must be continuously improved. It is because the integrated circuit is easy to generate electromagnetic interference with other internal or external electronic devices, such as cross talk, transmission loss and signal reflection, etc. The performance is reduced, so how to protect the integrated circuit chip in the chip package structure from electromagnetic interference to achieve quality requirements is relatively important. Conventionally, a structure in which an electromagnetic shielding layer is connected to a ground is provided in a substrate φ, for example, as disclosed in Japanese Patent Laid-Open No. 1287433. A ground layer is pre-formed on the inside of the substrate, and the ground line is extended to the side of the upper surface of the substrate, and the ground line is electrically connected to the lower surface of the substrate through a via or a plated through hole (PTH). . After encapsulation, an electromagnetic interference shielding layer is formed on the surface of the encapsulant and connected to the grounding line to direct electromagnetic waves or static electricity to the ground loop for release and dissipation, thereby protecting the wafer from electromagnetic interference. However, the substrate needs to additionally add a corresponding ground line to the side of the substrate, and the manufacturing cost is relatively increased. In addition, the EMI shielding layer is used to connect the side of the substrate to the 201214650 ground line. However, the ground line on the side of the substrate has a limited end face, which is narrow and narrow. Therefore, the contact area with the electromagnetic interference shielding layer is a point-like joint. It is easy to cause poor contact of the grounding line and cause electromagnetic shielding failure. Another person proposes a substrate-improving structure in a shield-grounded chip package structure, such as disclosed in Japanese Patent Laid-Open Publication No. Hei. In the process of the cracking, a cut-off portion disposed adjacent to the periphery of the substrate unit is first formed on the substrate. Before the package, the grounding member is disposed in the groove of the original cut-out portion and extends on the upper surface of the substrate unit. Between the lower surface and the lower surface. After sealing the skirt, the grounding element is exposed to the lateral connection surface during the singulation, and then the electromagnetic interference protection body is electrically connected to the connection surface of the grounding element, and the grounding element provides an electrical path to electromagnetic interference. The electromagnetic radiation on the shield is discharged to the ground. Although the combined area of the grounding element and the electromagnetic interference shielding body is increased by this method, the design, fabrication and cutting steps of the grounding element are complicated and complicated, and the manufacturing cost and time are increased. SUMMARY OF THE INVENTION The main purpose of the poor moon is to provide a full-mask shield to the grounded fresh ball crystal package structure, so that the cover shield on the surface of the seal body is directly connected to the ground line of the substrate Grounding ball to improve the electrical performance of the package structure. The second objective of the present invention is to provide a full-mask shielded ground-to-ground wafer package structure that does not require changing the substrate structure of the substrate. 201214650 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a full-mask shield-to-ground solder ball wafer package structure </ RTI> comprising a substrate, at least one wafer, a gel, a plurality of solder balls, an electromagnetic interference shield, and a bottom conductor. The substrate has an upper surface, a lower surface and a plurality of sides. The lower surface of the substrate is provided with a plurality of ball pads and a solder mask layer, and the ball pads comprise at least one ground pad. The system is disposed on the substrate and electrically connected to the substrate. The encapsulation system is formed on the upper surface of the substrate to coat the wafer. The solder balls are bonded to the ball 塾 of the substrate. The solder balls comprise at least one ground solder ball on the ground pad. The electromagnetic interference shielding layer covers a top surface and a peripheral side surface of the encapsulant to extend to the side edges of the substrate. The bottom wire is formed on the solder mask layer. The bottom wire is connected to the ground ball by the side of the substrate adjacent to the ground pad to provide electromagnetic interference shielding. • The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the aforementioned wafer package construction, the electromagnetic interference shield layer may be a surface coated conductive paint layer. In the aforementioned wafer package construction, the substrate may not have a ground line extending to the sides. In the aforementioned chip package construction, one end of the bottom wire can partially cover the ground pad 'for bonding of the ground ball. In the foregoing chip package structure, the main earth moving surface of the wafer may be attached to the upper surface of the substrate by the 201214650, and the substrate may have a through hole 'to expose the plurality of the wafers on the active surface. Solder pad. In the foregoing chip package structure, a plurality of electrical connection elements passing through the through-holes may be further included to electrically connect the pads to the substrate. In the foregoing chip package structure, the electrical connection elements may be wire bonds formed by wire bonding. As can be seen from the above technical solution, the full package type shield-to-pen solder ball chip package structure of the present invention has The following advantages and effects: - The special combination of the electromagnetic interference shielding layer and the bottom wire can be used as a technical means. The electromagnetic interference shielding layer is used to cover the top surface and the surrounding side of the sealing body, and extends to the side of the substrate. Side, the bottom surface of the surface of the material layer is connected to the grounding ball, so that the full shield layer on the surface of the sealing body is directly connected to the grounding ball by the grounding line of the substrate to improve the electrical performance of the package structure. The special combination of the bottom wire can be externally shaped from the chip package structure. The electromagnetic interference shielding layer can be used as one of the technical means to form a grounded bottom wire. The ground connection of the various shielded shields is not It is necessary to change the wiring structure of the substrate. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, but it should be noted that 'these illustrations are not intended to be outside the ribs + __ simplification, Only the schematic method is used to explain the basic structure of the present invention. Therefore, only the components and combinations related to the case are shown. The components shown in the figure φ _ are not actual [s] 6 The number, shape, and size of the implementation of 201214650 are drawn in equal proportions, and some ratios of scales to other related sizes are either exaggerated or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation are two alternative designs, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a wafer package structure of a full-cover shield to a ground solder ball is illustrated in a cross-sectional schematic view of Fig. 2 and a partial bottom view of Fig. 3. The chip package structure (10) mainly comprises a substrate no, at least one wafer 120, a gel 13 〇, a plurality of solder balls 14 〇, an electromagnetic interference shield & 15 (), and a bottom conductor 16 〇. In the first embodiment of the present embodiment, the window type ball grid array package type is taken as an example 'but without limitation, the present invention can also be applied to other known ball grid array package structures or flip chip package structures. Referring to FIG. 1 , the substrate 11 is used to provide electrical connection and serves as the wafer carrier of the wafer package structure, usually a printed circuit board, or may be a carrier board, a circuit film or a “cutting”. The external packaged lead frame m 110 of the type package has an upper surface (1), a surface 112 and a plurality of side edges 113, and the upper surface is a wafer "against, and serves as the sealing tape 130" The surface to be covered is the mounting surface of the solder balls 14G which is exposed outside the sealing body 13 且 and opposite to the surface of the upper surface Hi. The substrate may be formed by a plurality of substrate strips (subsuate P) and then singulated to form a plurality of wafer packages. The substrate ii 0 after 丨i has a plurality of singulated singulations as the exposed side edges (1), and generally four sides are connected to the periphery of the upper surface (1) from the 201214650 side to the periphery of the lower surface 112, so that the substrate no It is a rectangle or a square. In this embodiment, the substrate 110 may not have a ground line extending to the side edges 113, so that the inside of the substrate 110 is a structure of an original metal wiring layer. Preferably, the substrate 110 can be selected from a circuit substrate having only a single-sided wiring layer, which can eliminate the complexity and process troubles of the ground metal layer layout, thereby improving the speed of signal processing and reducing the manufacturing cost of the substrate. Further, as shown in FIG. 1 , the lower surface U2 of the substrate 110 is provided with a plurality of ball pads 114 and a solder mask layer 115. The ball pads 114 include at least one ground pad 116. The solder mask layer 115 can be an insulating surface coating of a protective line, which can be called green lacquer, or can be other surface protective layer with solder resist properties. In this embodiment, the solder mask layer 5 is formed on the lower surface 112 of the substrate 110 and partially covers the ball pads 114 (including the grounding pad 116). The anti-soil circuit and the substrate core layer are exposed. And it is polluted. The ground pad 116 can be a dummy pad without a signal transfer function or a metal pad connected to an external printed circuit board by a ground line. As shown in FIG. 1, the wafer 120 is disposed on the substrate 110 and electrically connected to the substrate 110. The chip 120 can be a base band chip or an RF chip, which can be separated by a wafer. In this embodiment, one active surface 121 of the wafer 12 can be attached to the upper surface m of the substrate 11 , and the substrate 110 can have a through hole 117 to expose the plurality of wafers 120 . The pad 122 is located on the active surface 121. The through slot 117 is
S 201214650 位於該基板110之中央位置，而該些銲墊122係分佈排 列於該晶片120之該主動面121之中央，即中央型銲墊 (central pad)。該晶片120係可利用一非液態黏晶層，例 如勝帶、B階黏勝（B-stage adhesive)或是晶片貼附物質 (Die Attach Material, DAM)，以黏接該晶片120之該主 動面121至該基板110之該上表面π! ^該基板"ο在 該貫穿槽孔1 1 7之兩側可設置複數個接指，利用跡線電 鲁 性連接至該些接球塾114(包含該接地塾116)。此外，在 該晶片封裝構造100中可另包含複數個穿過該貫穿槽孔 117之電性連接元件170’以電性連接該些銲墊122至該 基板11 0。在本實施例中’該些電性連接元件1 7 〇係為 打線形成之銲線（bonding wires)，可為金線或鋼線，係 連接該晶片120之該些銲墊122與該基板11〇之接指。 在另一變化實施例中’該些電性連接元件丨7〇亦可為基 板内部延伸出之引線（lead)。 _ 該封膠體130係形成於該基板110之該上表面Ul， 以包覆該晶片1切。具體而言，該封膠體13〇係可為一 環氧模封化合物（Epoxy Molding Compound，EMC)，以轉 移成形方式（transfer m〇iding)覆蓋於該基板11〇之該上 表面111。在本實施例中，該封膠體13〇係可更形成在 該基板11〇之該貫穿槽孔117與部分之該下表面112 ’ 以密封該些電性連接元件i 7〇 ’提供適當的絕緣封裝保 護’以防止電性短路與塵埃污染。 如第1圖與第2圖之局部放大圖所示，該些銲球14〇 9 201214650 係接合至該基板110之該些接球墊114 ’該些銲球14〇 係包含至少一位於該接地墊116之接地銲球ι41。該些 銲球140與該接地銲球141係呈柵狀陣列排列於該下表 面112，其形成方式例如為：在該基板11〇之該下表面 112上的該些接球墊114(包含該接地墊116)上形成一錫 膏（solder paste)或助銲劑（flux)，再在上述錫膏或助銲劑 上分別放置具有一定固定球徑的錫球（solder ball)，再經 鲁 由一迴焊（reflow)製程將上述錫球熔化並焊接於該基板 110上’形成該些銲球140以及該接地銲球141。 請再參閱第1圖所示，該電磁干擾屏蔽層15〇係包覆 該封膠體130之一頂面131與四周側面132，更延伸至 該基板110之該些側邊113。該電磁干擾屏蔽層15〇係 作為該晶片封裝構造1〇〇之電磁防護層（RF shielding)， 可形成在該封膠體130表面上，更延伸至該基板11〇之 該些侧邊113。詳細而言，該電磁干擾屏蔽層15〇係可 為表面塗佈之導電漆詹（conductive coating).，例如銀膠 (epoxy paste) ’可利用印刷塗佈（c〇ating)、喷塗（听^) 等方式將該電磁干擾屏蔽層15〇形成在該封膠體13〇表 面上與該基板110之該些側邊113上，如此方可以在該 封膠體130與該基板110等不同材質表面以一次作業方 式形成該電磁干擾屏蔽層150。在其他之變化例中，該 電磁干擾屏蔽層1 50亦可利用浸潰、電鑛（piating)、真 空印刷（vacuum printing)、真空沉積（vacuum deposition)、插入成形（insert m〇iding)或其他可行方法形： 10 201214650 成。此外，在其他應用例中，該電磁干擾屏蔽層150亦 可為一金屬殼體，利用雙面膠層貼附於該封膠體130表 面與該基板110之該些側邊113。較佳地，如第1圖所 示，該封膠體130之該些四周側面132與該基板110之 該些侧邊113平齊而不具有凸出端，其係可在模封 (molding)之後經同一切割步驟中形成，以利該電磁干擾 屏蔽層150之形成。 • 該底面導線160係形成於該銲罩層115上，該底面導 線160係由該基板110鄰近該接地墊114之其中一側邊 113連接該電磁干擾屏蔽層15〇至該接地銲球14卜以完 成接地線路之連接與提供電磁干擾屏蔽、減少傳輸損耗 與串擾（cross talk)現象。具體而言，如第2與3圖所示， 該底面導線160係形成於該基板110底部之顯露表面 上’除了採用在植球之前（即該些銲球14〇形成之前）的 印刷方法形成該底面導線1 6 〇，亦可在植球之後利用一 籲金線筆wire pen,圖未繪出）升溫至可使金線成融 溶態的溫度，取由該接地銲球141至該電磁干擾屏蔽層 150之最短距離，以塗畫方式形成該底面導線16〇，使該 接地銲球141與該電磁干擾屏蔽層丨5〇為連結導通。詳 細而。，金線筆係可採尖端加熱或放電形式達成，以減 少能源消耗。在另—變化實施例中，可將金線筆内塗施 物可更換為其他任何金屬材質，例如：鋁、銅等價格較 為便且之材質，以降低製造成本。較佳地，該接地墊H6 係可設置在鄰近該基板UG之任—側邊ιΐ3，以降低該 201214650 底面導線1 60之長度與塗施難度。放本發明係從該晶片 封裝構造100之基板外部形成接地連接之底面導線 160,嫁保全罩式電磁干擾屏蔽層15〇的接地連接又不需 要改變該基板11 0之線路結構。此外，本發明利用該電 磁干擾屏蔽層150包覆該封膠體130之該頂面131與四 周侧面132,更延伸至該基板11〇之側邊η3，再利用該 底面導線160連接至該接地銲球14卜令在該封膠體13〇 φ 表面之全罩式電磁干擾屏蔽層150跳過該基板11〇之接 地線路而直接連接至接地銲球1 4丨，藉以改善該晶片封 裝構造1 00之電性效能，並且對於封裝結構之抗濕性亦 有改善之效果。 依據本發明之第一具體實施例，另一種全罩式屏蔽至 接地銲球之晶片封裝構造說明於第4與5圖之截面示意 圖。該晶片封裝構造200主要包含一基板11〇、至少一 晶片120、一封膠體13〇、複數個銲球14〇、一電磁干擾 籲屏蔽層15〇以及一底面導線1 60。其中與第一實施例相 同的主要元件將以相同符號標示，故可理解亦具有上述 之相同作用’在此不再予以贅述。 在本實施例中’如第4圖所示，該晶片丨2〇之該主動 面i21係可朝上設置，該些銲墊122係設置於該晶片12〇 之該主動面121之單—侧邊。該晶片12〇之上方可再往 上堆疊更多適當數量之晶片i 2〇，達到記憶體容量或是 力忐的擴充，而成為多晶片封裝構造。再利用該些電性 連接疋件170連接該些晶片12〇至該基板11〇之複數個 12 201214650 接指215。該些接指215係設置在該基板110之該上表 面111，可並以另一銲罩層216局部覆蓋該些接指215 以防止線路及基板核心層外露而被污染。在其他變化例 中，下方之晶片120亦可以覆晶方式接合至該基板11〇。 此外’如第5圖之局部放大圖所示，該底面導線ι6〇 之一端係可局部覆蓋該接地墊11 6，以供該接地銲球14 1 之接合。其形成方式係在植球之前先以金線筆塗畫連接 由該接地墊116至該電磁干擾屏蔽層15〇，之後再進行 該些銲球140之設置，經由一迴焊（refl〇w)製程後可將錫 球熔化並焊接於該些接球墊114與該接地墊116上而 達到全罩式屏蔽之接地連接，不需要利用習知延伸基板 侧邊之接地線路。S 201214650 is located at a central position of the substrate 110, and the pads 122 are distributed in the center of the active surface 121 of the wafer 120, that is, a central pad. The wafer 120 can utilize a non-liquid adhesive layer, such as a ribbon, a B-stage adhesive, or a Die Attach Material (DAM) to bond the active wafer 120. The surface 121 to the upper surface of the substrate 110 is π! ^ The substrate " ο a plurality of fingers may be disposed on both sides of the through slot 1 1 7 , and electrically connected to the ball 塾 114 by a trace (Include this grounding 塾 116). In addition, the chip package structure 100 may further include a plurality of electrical connection elements 170' passing through the through holes 117 to electrically connect the pads 122 to the substrate 110. In the present embodiment, the electrical connecting elements 1 7 are bonding wires formed by wire bonding, which may be gold wires or steel wires, and the pads 122 connecting the wafers 120 and the substrate 11 〇 接 。. In another variant embodiment, the electrical connection elements 丨7〇 may also be leads extending inside the substrate. The encapsulant 130 is formed on the upper surface U1 of the substrate 110 to cover the wafer 1 to be cut. Specifically, the encapsulant 13 can be an Epoxy Molding Compound (EMC) coated on the upper surface 111 of the substrate 11 by transfer molding. In this embodiment, the encapsulant 13 can be further formed on the through hole 117 of the substrate 11 and a portion of the lower surface 112 ′ to seal the electrical connection elements i 7 ′′ to provide proper insulation. Package protection 'to prevent electrical short circuits and dust pollution. As shown in the partial enlarged views of FIGS. 1 and 2, the solder balls 14〇9 201214650 are bonded to the ball pads 114 of the substrate 110. The solder balls 14 are at least one located at the ground. Grounding ball ι41 of pad 116. The solder balls 140 and the ground solder balls 141 are arranged in a grid array on the lower surface 112, and are formed by, for example, the ball pads 114 on the lower surface 112 of the substrate 11 (including the A solder paste or a flux is formed on the ground pad 116), and a solder ball having a certain fixed ball diameter is placed on the solder paste or the flux, and then the solder ball is returned. A reflow process melts and solders the solder balls onto the substrate 110 to form the solder balls 140 and the ground solder balls 141. Referring to FIG. 1 again, the EMI shielding layer 15 covers one of the top surface 131 and the surrounding side surface 132 of the encapsulant 130 and extends to the side edges 113 of the substrate 110. The EMI shielding layer 15 is formed as an electromagnetic shielding layer of the chip package structure, and is formed on the surface of the encapsulant 130 and extends to the side edges 113 of the substrate 11. In detail, the electromagnetic interference shielding layer 15 can be a surface-coated conductive coating. For example, an epoxy paste can be used for printing, coating, and printing. The EMI shielding layer 15 is formed on the surface of the encapsulant 13 and the side edges 113 of the substrate 110, so that the surface of the encapsulant 130 and the substrate 110 can be different. The electromagnetic interference shielding layer 150 is formed in a single operation mode. In other variations, the EMI shielding layer 150 can also utilize immersion, piating, vacuum printing, vacuum deposition, insert m〇iding, or other Possible method form: 10 201214650 into. In addition, in other applications, the EMI shielding layer 150 can also be a metal casing, and the double-sided adhesive layer is attached to the surface of the sealing body 130 and the side edges 113 of the substrate 110. Preferably, as shown in FIG. 1 , the peripheral sides 132 of the encapsulant 130 are flush with the side edges 113 of the substrate 110 without protruding ends, which may be after molding. Formed in the same cutting step to facilitate the formation of the electromagnetic interference shielding layer 150. The bottom wire 160 is formed on the solder mask layer 115. The bottom wire 160 is connected to the grounded solder ball 14 from the one side 113 of the ground pad 114. To complete the connection of the grounding line and provide electromagnetic interference shielding, reduce transmission loss and cross talk. Specifically, as shown in FIGS. 2 and 3, the bottom wire 160 is formed on the exposed surface of the bottom of the substrate 110 except that it is formed by a printing method before the ball is formed (that is, before the solder balls 14 are formed). The bottom wire 1 6 〇 can also be heated by a wire pen (not shown) after the ball is raised to a temperature at which the gold wire can be melted, and the ground ball 141 is taken to the electromagnetic The bottom wire 16 is formed by the shortest distance of the interference shielding layer 150, and the ground ball 141 is electrically connected to the electromagnetic interference shielding layer 丨5〇. Detailed. Gold line pens can be achieved by cutting-edge heating or discharge to reduce energy consumption. In another alternative embodiment, the gold pen inner coating can be replaced with any other metal material, such as aluminum, copper, etc., which is relatively inexpensive, to reduce manufacturing costs. Preferably, the ground pad H6 can be disposed adjacent to the side ι 3 of the substrate UG to reduce the length and application difficulty of the 201214650 bottom wire 1 60. The present invention forms a ground connection wire 160 from the outside of the substrate of the wafer package structure 100, and the ground connection of the full-cover EMI shielding layer 15〇 does not need to change the circuit structure of the substrate 110. In addition, the EMI shielding layer 150 covers the top surface 131 and the peripheral side surface 132 of the encapsulant 130, and extends to the side η3 of the substrate 11 , and is connected to the ground welding by the bottom wire 160. The ball 14 is disposed on the surface of the sealing body 13〇φ, and the full-shield electromagnetic interference shielding layer 150 is directly connected to the grounding ball 1 4丨, thereby improving the chip package structure 1 00. Electrical performance, and also has an improved effect on the moisture resistance of the package structure. In accordance with a first embodiment of the present invention, another wafer package construction of a full-mask shield to ground ball is illustrated in cross-sections in Figures 4 and 5. The chip package structure 200 mainly comprises a substrate 11 , at least one wafer 120 , a gel 13 〇 , a plurality of solder balls 14 , an electromagnetic interference shielding layer 15 , and a bottom wire 1 60 . The same elements as those in the first embodiment will be denoted by the same reference numerals, and it is understood that they have the same functions as described above' and will not be described again. In the present embodiment, as shown in FIG. 4, the active surface i21 of the wafer can be disposed upward, and the pads 122 are disposed on the single side of the active surface 121 of the wafer 12 side. A larger number of wafers i 2 堆叠 can be stacked on top of the wafer 12 to achieve a memory capacity or a power expansion to become a multi-chip package structure. The plurality of 12 201214650 fingers 215 are connected to the plurality of 12 through the plurality of electrical connections 170 170. The fingers 215 are disposed on the upper surface 111 of the substrate 110, and the contacts 215 may be partially covered by another solder mask layer 216 to prevent the line and the substrate core layer from being exposed and contaminated. In other variations, the underlying wafer 120 can also be flip-chip bonded to the substrate 11A. Further, as shown in a partially enlarged view of Fig. 5, one end of the bottom wire ι6 可 partially covers the ground pad 11 6 for the bonding of the ground ball 14 1 . The method of forming is to connect the grounding pad 116 to the electromagnetic interference shielding layer 15〇 with a gold pen before painting the ball, and then perform the setting of the solder balls 140 through a reflow (refl〇w). After the process, the solder balls can be melted and soldered to the ball pads 114 and the ground pad 116 to achieve a full-shield shield ground connection without using a grounding line on the side of the conventional extension substrate.
【圖式簡單說明】 一具體實施例的一種全罩式展[Simple Description of the Drawings] A full-cover exhibition of a specific embodiment
第1圖.依據本發明之第一 第2圖 201214650 第3圖 第4圖 ’依據本發明之第 接地銲球之晶片 ’依據本發明之第 屏蔽至接地銲球 圖〇 —具體實施例 封裴構造之局 二具體實施例 之晶片封裝^ 第5圖：依據本發明之第二具體實施例 接地銲球之晶片封裝構造之局 的全罩式屏蔽至 部底面示意圖。 的另一種全罩式 綠造之截面示意 的全罩式屏蔽至 部放大截面示意1 is a first shielded to grounded solder ball according to the present invention. FIG. 4 is a first embodiment of the present invention. FIG. 4 is a second embodiment of the present invention. 2 is a wafer package of a specific embodiment. FIG. 5 is a schematic view showing a full-face shield to a bottom surface of a wafer package structure of a ground solder ball according to a second embodiment of the present invention. Another full-cover green-shaped section of the full-face shield to the enlarged section
【主 要元件符號說明 ] 100 晶片封裝構造 110 基板 111 上表面 113 側邊 114 接球墊 116 接地墊 117 貫穿槽孔 120 晶片 121 主動面 130 封膠體 131 頂面 140 銲球 141 接地銲球 150 電磁干擾屏蔽層 160 底面導線 170 電性連接元件 200 晶片封裝構造 215 接指 216 銲罩層 112下表面 115銲罩層 122銲墊 1 3 2四周側面 14[Main component symbol description] 100 chip package structure 110 substrate 111 upper surface 113 side 114 ball pad 116 ground pad 117 through slot 120 wafer 121 active surface 130 encapsulant 131 top surface 140 solder ball 141 ground solder ball 150 electromagnetic interference Shielding layer 160 bottom wire 170 electrically connecting component 200 chip packaging construction 215 finger 216 solder mask layer 112 lower surface 115 solder mask layer 122 solder pad 1 3 2 peripheral side 14