CN109461719A - 一种集成电路封装结构 - Google Patents

一种集成电路封装结构 Download PDF

Info

Publication number
CN109461719A
CN109461719A CN201811005780.3A CN201811005780A CN109461719A CN 109461719 A CN109461719 A CN 109461719A CN 201811005780 A CN201811005780 A CN 201811005780A CN 109461719 A CN109461719 A CN 109461719A
Authority
CN
China
Prior art keywords
layer
groove
electromagnetic chip
electromagnetic
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811005780.3A
Other languages
English (en)
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201811005780.3A priority Critical patent/CN109461719A/zh
Publication of CN109461719A publication Critical patent/CN109461719A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提供了一种集成电路封装结构，其电磁芯片通过固定胶固定于凹槽的底部，凹槽的深度和宽度分别大于电磁芯片的高度和宽度，环形屏蔽层环绕电磁芯片并位于凹槽底部，封装层密封电磁芯片和环形屏蔽层，电磁芯片并通过导电通孔电连接至焊盘，其他多个集成芯片电连接至线路层和焊盘，所述线路层和焊盘均位于基板和封装层的上表面。本发明利用环形屏蔽层和金属基板的双层屏蔽，减小电磁干扰，减小了封装体积，增强了封装的灵活性。

Description

一种集成电路封装结构
技术领域
本发明涉及集成电路封装领域，具体涉及一种集成电路封装结构。
背景技术
在集成电路封装中，由于本身电子器件的电磁辐射或外界的电磁辐射，往往会导致集成电路的信号不稳定，电路失效，现有技术中，是将容易受电磁干扰或发出电磁波的半导体元件封装在特定的集成电路中，在将该封装体予以电子屏蔽，其屏蔽的构件往往是一个金属罩体，这样的封装体体积较大且封装极为不灵便。
发明内容
基于解决上述封装中的问题，本发明提供了一种集成电路封装结构的制造方法，其包括以下步骤：
（1）提供一带有凹槽的金属基板，将电磁芯片固定于凹槽底部，所述凹槽的深度和宽度分别大于所述电磁芯片的高度和宽度；
（2）形成环绕所述电磁芯片的环形屏蔽层；
（3）用封装胶填充满所述凹槽，完全覆盖电磁芯片和环形屏蔽层，固化后形成封装层；
（4）在对应电磁芯片的电极位置开槽形成通孔，所述通孔的孔径小于屏蔽凹槽的宽度；在所述通孔中填充导电物质形成连接电磁芯片的导电通孔，所述导电通孔的材质为非金属；
（5）形成在金属基板上的线路层和连接导电通孔的焊盘，并利用线路层和焊盘耦合其他集成芯片。
其中，形成环形屏蔽层的具体步骤为：在凹槽内沉积光刻胶，其中所述光刻胶的高度低于凹槽的深度并完全覆盖电磁芯片；利用干法光刻技术光刻光刻胶，在围绕电磁芯片的周圈形成环形的屏蔽凹槽，屏蔽凹槽的底部暴露固定胶；利用电磁屏蔽材料填充所述屏蔽凹槽形成环形屏蔽层，去除光刻胶。
其中，所述电磁屏蔽材料为金属。
本发明还提供了一种集成电路封装结构，其包括带有凹槽的金属基板、固定胶、电磁芯片、环形屏蔽层、封装层、导电通孔、线路层、焊盘和其他多个集成芯片，所述电磁芯片通过固定胶固定于凹槽的底部，所述凹槽的深度和宽度分别大于待封装电磁芯片的高度和宽度，环形屏蔽层环绕所述电磁芯片并位于凹槽底部，封装层密封所述电磁芯片和环形屏蔽层，电磁芯片并通过导电通孔电连接至焊盘，其他多个集成芯片电连接至线路层和焊盘，所述线路层和焊盘均位于基板和封装层的上表面。
其中，所述固定胶包括压敏固化胶、热固化胶、光固化胶、硅脂或环氧树脂。
其中，所述环形屏蔽层的宽度大于或等于1mm。
其中，所述其他多个集成芯片包括控制器、MOS晶体管或电阻。
本发明的优点如下：
（1）利用环形屏蔽层和金属基板的双层屏蔽，减小电磁干扰；
（2）利用基板的凹槽进行电磁导向；
（3）形成电子屏蔽较好的封装体，在后续集成电路封装中无需再增加电磁屏蔽罩等构件，减小了封装体积，增强了封装的灵活性。
附图说明
图1-10为本发明的集成电路封装结构的制造方法的过程示意图。
具体实施方式
参见图1-10，本发明首先提供了一种集成电路的封装方法，具体步骤将在如下进行描述，描述中所出现的上下、左右、侧面等位置名词均相对于示意图中的位置关系。
参见图1，提供一金属基板1，在金属基板1顶面挖槽形成安装凹槽2，所述凹槽2的深度和宽度分别大于待封装电磁芯片4的高度和宽度，所述金属基板接地以防止电磁波的干扰或通过。将电磁芯片4固定于凹槽2的底部，该电磁芯片是容易受电磁干扰或发出电磁波的半导体元件，例如RF元件、光电探测器、传感器、光电接收器等，其固定方式可通过固定胶3固定，该固定胶3包括压敏固化胶、热固化胶、光固化胶、硅脂、环氧树脂等。
参见图2，在凹槽2内沉积光刻胶5，其中所述光刻胶5的高度低于凹槽2的深度并完全覆盖电磁芯片4。
参见图3，利用干法光刻技术光刻光刻胶5，在围绕电磁芯片4的周圈形成环形的屏蔽凹槽6，屏蔽凹槽6的底部暴露固定胶3，该环形的屏蔽凹槽6的宽度为大于或等于1mm，以获得足够的厚度进行电磁屏蔽。
参见图4，利用电磁屏蔽材料填充所述屏蔽凹槽6形成环形屏蔽层7，其宽度同样的大于或等于1mm，高度略高于电磁芯片4单小于凹槽2的深度，其中电磁屏蔽材料优选为金属。
参见图5，去除光刻胶5。
参见图6，用封装胶填充满所述凹槽2，完全覆盖电磁芯片4和环形屏蔽层7，固化后形成封装层8。
参见图7，在对应电磁芯片4的电极位置开槽形成通孔9，所述通孔9的孔径小于屏蔽凹槽6的宽度。
参见图8，填充导电物质形成导电通孔10，所述导电物质为非金属，优选为多晶硅、ITO、AZO等，以防止正面电磁发射或接收的干扰。
参见图9，在基板2的上表面和封装层8上形成线路层11和电连接导电通孔10的焊盘12，所述线路层包括用于电隔离线路层11和金属基板1的绝缘层（未示出）。
参考图10，利用线路层11和焊盘12耦合其他多个电子元件13，所述其他多个电子元件13包括控制器、MOS晶体管、电阻等，所述其他多个电子元件13尺寸可以不同，但是都叠置在电磁芯片4上，并与电磁芯片4部分重叠，形成用于电磁发射或接收的开口。
本发明通过上述封装方法形成了一种集成电路封装结构，其包括带有凹槽2的金属基板1、固定胶3、电磁芯片4、环形屏蔽层7、封装层8、导电通孔10、线路层11、焊盘12和其他多个集成芯片13，所述电磁芯片4通过固定胶3固定于凹槽2的底部，所述凹槽2的深度和宽度分别大于待封装电磁芯片4的高度和宽度，环形屏蔽层7环绕所述电磁芯片4并位于凹槽底部，封装层密封所述电磁芯片4和环形屏蔽层7，电磁芯片4并通过导电通孔10电连接至焊盘12，其他多个集成芯片电连接至线路层11和焊盘12，所述线路层11和焊盘12均位于基板2和封装层8的上表面。
最后应说明的是：显然，上述实施例仅仅是为清楚地说明本发明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (2)

1.一种集成电路封装结构，其包括带有凹槽的金属基板、固定胶、电磁芯片、环形屏蔽层、封装层、导电通孔、线路层、焊盘和其他多个集成芯片，所述电磁芯片通过固定胶固定于凹槽的底部，所述凹槽的深度和宽度分别大于待封装电磁芯片的高度和宽度，环形屏蔽层环绕所述电磁芯片并位于凹槽底部，封装层密封所述电磁芯片和环形屏蔽层，电磁芯片并通过导电通孔电连接至焊盘，其他多个集成芯片电连接至线路层和焊盘，所述线路层和焊盘均位于基板和封装层的上表面；
所述固定胶包括压敏固化胶、热固化胶、光固化胶、硅脂或环氧树脂，所述环形屏蔽层的宽度大于或等于1mm。
2.根据权利要求1所述的集成电路封装结构，其特征在于：所述其他多个集成芯片包括控制器、MOS晶体管或电阻。
CN201811005780.3A 2016-07-17 2016-07-17 一种集成电路封装结构 Pending CN109461719A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811005780.3A CN109461719A (zh) 2016-07-17 2016-07-17 一种集成电路封装结构

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811005780.3A CN109461719A (zh) 2016-07-17 2016-07-17 一种集成电路封装结构
CN201610558807.6A CN106206547B (zh) 2016-07-17 2016-07-17 一种集成电路封装结构及其制造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201610558807.6A Division CN106206547B (zh) 2016-07-17 2016-07-17 一种集成电路封装结构及其制造方法

Publications (1)

Publication Number Publication Date
CN109461719A true CN109461719A (zh) 2019-03-12

Family

ID=57474974

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201811005785.6A Pending CN109524387A (zh) 2016-07-17 2016-07-17 一种集成电路封装结构的制造方法
CN201811005780.3A Pending CN109461719A (zh) 2016-07-17 2016-07-17 一种集成电路封装结构
CN201610558807.6A Active CN106206547B (zh) 2016-07-17 2016-07-17 一种集成电路封装结构及其制造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201811005785.6A Pending CN109524387A (zh) 2016-07-17 2016-07-17 一种集成电路封装结构的制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201610558807.6A Active CN106206547B (zh) 2016-07-17 2016-07-17 一种集成电路封装结构及其制造方法

Country Status (1)

Country Link
CN (3) CN109524387A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110286367A (zh) * 2019-07-03 2019-09-27 江西亿施客传感器有限公司 一种小型化微波传感器
CN111490019A (zh) * 2020-04-24 2020-08-04 济南南知信息科技有限公司 一种集成电路结构及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111050534B (zh) * 2019-12-19 2022-02-18 Oppo广东移动通信有限公司 基板组件、网络设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263080A (ja) * 2009-05-07 2010-11-18 Denso Corp 半導体装置
CN103165563A (zh) * 2011-12-16 2013-06-19 矽品精密工业股份有限公司 半导体封装件及其制法
CN103219324A (zh) * 2012-01-18 2013-07-24 刘胜 堆叠式半导体芯片封装结构及工艺

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518229B2 (en) * 2006-08-03 2009-04-14 International Business Machines Corporation Versatile Si-based packaging with integrated passive components for mmWave applications
CN103313175A (zh) * 2012-03-16 2013-09-18 美律电子(深圳)有限公司 微机电麦克风封装模块
US9318411B2 (en) * 2013-11-13 2016-04-19 Brodge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
CN104701273A (zh) * 2015-03-27 2015-06-10 江阴长电先进封装有限公司 一种具有电磁屏蔽功能的芯片封装结构
CN204720447U (zh) * 2015-06-19 2015-10-21 江苏长电科技股份有限公司 一种凹槽基板的电磁屏蔽模组封装结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263080A (ja) * 2009-05-07 2010-11-18 Denso Corp 半導体装置
CN103165563A (zh) * 2011-12-16 2013-06-19 矽品精密工业股份有限公司 半导体封装件及其制法
CN103219324A (zh) * 2012-01-18 2013-07-24 刘胜 堆叠式半导体芯片封装结构及工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110286367A (zh) * 2019-07-03 2019-09-27 江西亿施客传感器有限公司 一种小型化微波传感器
CN111490019A (zh) * 2020-04-24 2020-08-04 济南南知信息科技有限公司 一种集成电路结构及其制造方法

Also Published As

Publication number Publication date
CN106206547B (zh) 2018-10-02
CN109524387A (zh) 2019-03-26
CN106206547A (zh) 2016-12-07

Similar Documents

Publication Publication Date Title
US8829667B2 (en) Electronic devices including EMI shield structures for semiconductor packages and methods of fabricating the same
US20070176281A1 (en) Semiconductor package
US20140291821A1 (en) Semiconductor package having grounding member and method of manufacturing the same
US8766416B2 (en) Semiconductor package and fabrication method thereof
US20190035706A1 (en) Shielded fan-out packaged semiconductor device and method of manufacturing
TWI453836B (zh) 半導體封裝件及其製法
CN106206332B (zh) 一种集成电路封装结构的制造方法
CN106206547B (zh) 一种集成电路封装结构及其制造方法
CN104701273A (zh) 一种具有电磁屏蔽功能的芯片封装结构
US9209101B2 (en) Semiconductor package with a conductive shielding member
US20130093067A1 (en) Wafer level applied rf shields
US9245854B2 (en) Organic module EMI shielding structures and methods
CN107452696B (zh) 电磁屏蔽封装体以及制造方法
CN102446870A (zh) 具有静电放电及防电磁波干扰的封装件
KR20110020548A (ko) 반도체 패키지 및 그의 제조방법
CN103617991A (zh) 半导体封装电磁屏蔽结构及制作方法
TW200805615A (en) Semiconductor package having electromagnetic interference shielding and fabricating method thereof
CN111599799B (zh) 集成电路
US9502377B2 (en) Semiconductor package and fabrication method thereof
US9048199B2 (en) Semiconductor package and method of manufacturing the semiconductor package
US20070077686A1 (en) Packaging method for preventing chips from being interfered and package structure thereof
TW201428926A (zh) 半導體封裝件及其製法
US9320183B1 (en) Ground lid opening on a substrate
CN213905353U (zh) 封装结构
CN104051432A (zh) 电子元件封装体

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20190312