TWI612638B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI612638B
TWI612638B TW106102894A TW106102894A TWI612638B TW I612638 B TWI612638 B TW I612638B TW 106102894 A TW106102894 A TW 106102894A TW 106102894 A TW106102894 A TW 106102894A TW I612638 B TWI612638 B TW I612638B
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Taiwan
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electronic package
wall
item
substrate
scope
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TW106102894A
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TW201828446A (zh
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蔡芳霖
張翊峰
王隆源
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矽品精密工業股份有限公司
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Priority to TW106102894A priority Critical patent/TWI612638B/zh
Priority to CN201710078185.1A priority patent/CN108346648B/zh
Priority to US15/492,394 priority patent/US10236261B2/en
Application granted granted Critical
Publication of TWI612638B publication Critical patent/TWI612638B/zh
Publication of TW201828446A publication Critical patent/TW201828446A/zh

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Abstract

一種電子封裝件係包括：基板、設於該基板上之電子元件與屏蔽隔板、形成於該基板上以包覆該電子元件與該屏蔽隔板之包覆層、以及形成於該包覆層上並電性連接該屏蔽隔板之金屬層，其中，該屏蔽隔板之部分表面係外露於該包覆層之側面，使該金屬層延伸至該包覆層之壁面，以減少該屏蔽隔板的寬度，故能減少該屏蔽隔板用以結合該基板之錫膏使用量，因而能避免發生銲料擴散不良之問題。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係有關一種封裝技術，尤指一種具有屏蔽結構之半導體封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，簡稱EMI)產生。
第1A圖係為習知具有屏蔽功能之半導體封裝件1之剖面示意圖，係於一基板10上置放複數半導體元件11與複數金屬屏蔽板12，其中，該些半導體元件11係電性連接該基板10，且該金屬屏蔽板12具有相對之第一端部12a及第二端部12b，並使該金屬屏蔽板12以其第二端部12b藉由錫膏9黏合於該基板10上(如第1B圖所示)，以令該金屬屏蔽板12遮擋於兩相鄰之半導體元件11之間，避免該些半導體元件11之間相互電磁干擾。
惟，習知半導體封裝件1中，因該金屬屏蔽板12之第二端部12b的寬度w等於該金屬屏蔽板12之第一端部12a 之寬度w，因而該第二端部12b與基板10的接著面積(如寬度w)遠大於一般元件與基板10的接著面積，致使錫膏9的沾附量相當大，故容易在後續的高溫製程(如回銲)中產生銲料擴散(solder extension)不良(如橋接半導體元件11之銲料致使短路)，而導致產品良率下降問題。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：基板；電子元件，係設於該基板上；屏蔽隔板，係設於該基板上；包覆層，係形成於該基板上以包覆該電子元件與該屏蔽隔板，並令該屏蔽隔板之部分表面外露於該包覆層之側面；以及金屬層，係形成於該包覆層上並接觸外露於該包覆層之該屏蔽隔板之部分表面。
本發明復提供一種電子封裝件之製法，係包括：設置電子元件與屏蔽隔板於一基板上；形成包覆層於該基板上，以令該包覆層包覆該電子元件與屏蔽隔板，其中，該包覆層形成有凹部，以令該屏蔽隔板之部分表面外露於該凹部之壁面；以及形成金屬層於該包覆層上並延伸至該凹部中，以令該金屬層接觸外露於該凹部之該屏蔽隔板之部分表面。
前述之製法中，該凹部之縱剖面之寬度不一致。
前述之製法中，復包括於形成該金屬層之後，沿該凹部進行切單製程。
前述之電子封裝件及其製法中，該屏蔽隔板係包含一頂部及結合該基板並支撐該頂部之牆部，其中，該頂部之部分表面接觸該金屬層，且該頂部之寬度係大於該牆部之寬度，又該包覆層係包覆該牆部。例如，該牆部係包含有複數內牆與圍繞該內牆之複數外牆，且各該內牆之間的間隙係小於各該外牆之間的間隙，例如，該基板上設有至少二該電子元件，且該內牆設於兩該電子元件之間，部分該內牆之頂部與該金屬層之間具有該包覆層；或者，該屏蔽隔板復包含支撐該頂部之柱部，例如，該牆部與柱部係交錯排列；亦或，該牆部之縱剖面之寬度係不一致。
前述之電子封裝件及其製法中，該包覆層之側面(該凹部之壁面)係為相對該基板之傾斜面。
另外，前述之電子封裝件及其製法中，該金屬層復形成於該包覆層之側面(該凹部之壁面)上。
由上可知，本發明之電子封裝件及其製法，主要藉由該金屬層延伸至該凹部之壁面上的設計，以減少該屏蔽隔板(牆部)的寬度，故相較於習知技術，本發明之電子封裝件能減少該屏蔽隔板用以結合該基板之導電材料(錫膏)使用量，因而能避免發生銲料擴散不良之問題。
1‧‧‧半導體封裝件
10、20‧‧‧基板
11‧‧‧半導體元件
12‧‧‧金屬屏蔽板
12a‧‧‧第一端部
12b‧‧‧第二端部
2‧‧‧電子封裝件
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧絕緣層
201‧‧‧線路層
21‧‧‧電子元件
210‧‧‧導電凸塊
210’‧‧‧銲線
22‧‧‧屏蔽隔板
22a‧‧‧頂部
22b、32b‧‧‧牆部
220‧‧‧內牆
221‧‧‧外牆
22c‧‧‧柱部
23‧‧‧凹部
23a‧‧‧壁面
24‧‧‧包覆層
24a‧‧‧第一表面
24b‧‧‧第二表面
24c‧‧‧側面
25‧‧‧金屬層
26‧‧‧導電元件
9‧‧‧錫膏
a、b、r、w‧‧‧寬度
h‧‧‧高度
d,t‧‧‧間隙
S‧‧‧切割線
U‧‧‧弧面狀
第1A圖係為習知半導體封裝件之剖面示意圖；第1B圖係為第1A圖之局部放大圖；第2A至2D圖係為本發明之電子封裝件之製法的剖面示意圖； 第3A圖係為第2A圖之局部放大圖；第3B圖係為本發明之電子封裝件之屏蔽隔板之其中一實施例的下視平面示意圖；以及第4A至4D圖係為本發明之電子封裝件之屏蔽隔板之不同實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「下」、「第一」、「第二」、「頂」、「側面」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一基板20，其具有相對之第一側20a(如上側)與第二側20b(如下側)，且於該基板20之第 一側20a上設有複數個相互分隔之電子元件21與複數屏蔽隔板22。
於本實施例中，該基板20係為具有核心層之線路結構或無核心層(coreless)之線路結構，其具有絕緣層200與設於該絕緣層200上之線路層201，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。例如，形成該線路層201之材質係為銅，而形成該絕緣層201之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。
再者，該電子元件21係為封裝件、主動元件、被動元件或其組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。具體地，該電子元件21係為射頻晶片(例如：藍芽晶片或Wi-Fi晶片)，但亦可為其它不受電磁波干擾之電子元件。例如，該電子元件21係藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該基板20上並電性連接該線路層201；或者，該電子元件21可藉由複數銲線210’以打線方式電性連接該線路層201。然而，有關該電子元件電性連接該基板之方式不限於上述。
又，該屏蔽隔板22係為金屬結構，其藉由如錫膏9之導電材料(銲錫材料)固定及立設於該基板20上(如第3A圖所示)，且該屏蔽隔板22係位於各該電子元件21周圍並電性連接該線路層201，以藉由該些屏蔽隔板22作為電磁 波屏障，防止各該電子元件21之間相互電磁波(或訊號)干擾。具體地，該屏蔽隔板22係包含一頂部22a及一用以結合該基板20並支撐該頂部22a之牆部22b，且該頂部22a之寬度a係大於該牆部22b之寬度b。
舉例而言，如第3B圖所示，係為該屏蔽隔板22之其中一種實施例，其頂部22a係呈格柵狀立設於基板20上，其牆部22b係設於該頂部22a下方並包含有複數相互分隔之內牆220與複數相互分隔之外牆221，該外牆221係位於該格柵狀之頂部22a之外圍位置，該內牆220係位於該格柵狀之頂部22a之內部格柵位置，且各該內牆220之間的間隙t係小於各該外牆221之間的間隙d，並使該內牆220設於兩該電子元件21(如第3B圖所示之虛線位置)之間，又該屏蔽隔板22復包含複數用以結合該基板20並支撐該頂部22a之柱部22c，如圓柱或角柱，其係與該於內牆220相鄰，以當該頂部22a之面積過大時，可藉由該些柱部22c增強支撐該頂部22a之作用。具體地，該牆部22b(如該內牆220)與該柱部22c亦可交錯排列(即牆與柱交錯排列)，以得到更好的結構支撐性。
另外，於製作該屏蔽隔板22時，將一等寬的格柵狀框架以例如蝕刻方式移除該框架於高度方向上之部分之材質，以得到一體的頂部22a、牆部22b與柱部22c。如第3B圖所示，係蝕刻該框架於高度方向上之一半材質，亦即該頂部22a之高度與該牆部22b(及該柱部22c)之高度相同(如第4C及4D圖所示之高度h)。
如第2B圖所示，形成一包覆層24於該基板20之第一側20a上，以令該包覆層24包覆該些電子元件21與該些屏蔽隔板22。接著，形成複數如銲球之導電元件26於該基板20之第二側20b上並電性連接線路層201，俾供後續接置如封裝結構或其它結構(如電路板)之電子裝置(圖略)。
於本實施例中，該包覆層24係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該基板20之第一側20a上。具體地，該包覆層24係具有相對之第一表面24a與第二表面24b，使該包覆層24之第一表面24a結合至該基板20之第一側20a上。
再者，該包覆層24之第二表面24b係形成有凹部23，以令該屏蔽隔板22之頂部22a凸出該凹部23之壁面23a而外露於該凹部23之壁面23a，但該包覆層24仍包覆該牆部22b。具體地，該凹部23之縱剖面之寬度不一致，例如，其剖面係呈現上寬下窄之形狀，如倒三角形，使該凹部23之壁面23a係為相對該基板20第一側20a之傾斜面。
又，可藉由移除該包覆層24之第二表面24b之部分材質之方式形成該凹部23，例如，雷射切割、楔形刀割、磨除或其它方法等；或者，可於形成該包覆層24時，以模壓(molding)之方式直接壓出具有該凹部23之包覆層24。因此，有關具有該凹部23之包覆層24之形成方式繁多， 可依需求選擇，並不限於上述。
另外，相較於該些牆部22b之整面擋牆設計，該柱部22c更有利於該包覆層24之膠材的流動。較佳地，當該牆部22b與柱部22c交錯排列時，可提升該包覆層24之膠材的流動性。
如第2C圖所示，形成一金屬層25於該包覆層24之第二表面24b上，且該金屬層25延伸至該凹部23之壁面23a上而未填滿該凹部23，並使該金屬層25接觸外露出該凹部23之該屏蔽隔板22之頂部22a，以令該金屬層25電性連接該屏蔽隔板22，俾供作為電磁屏蔽隔間(EMI partition)。
於本實施例中，形成該金屬層25之材質如金、銀、銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等，且可藉由電鍍、塗佈(coating)、濺鍍(sputtering)、化鍍、無電鍍或蒸鍍等方式形成該金屬層25；或者，該金屬層25為框架體，以直接置放於該包覆層24之第二表面24b上。
再者，部分該內牆220之頂部22a與該金屬層25之間具有該包覆層24。
又，該金屬層25於對應該頂部22a之處會微凸，故可依需求保持原狀或磨平。
如第2D圖所示，將該凹部23作為切割路徑(如第2C圖所示之切割線S)，而沿其進行切單製程，以得到本發明之電子封裝件2，且該包覆層24具有傾斜之側面24c。
因此，本發明之電子封裝件2之製法係藉由該金屬層 25延伸至該凹部23之壁面23a上的設計，以減少該屏蔽隔板22的牆部22b(外牆221)的寬度b(其小於如第1A及1B圖之習知金屬屏蔽板12之第二端部12b之寬度w)，故本發明之電子封裝件2之製法能減少錫膏9之使用量，因而能避免發生銲料擴散不良之問題。
再者，該屏蔽隔板22之牆部22b的構造並不限於直立寬度不變的牆面。若該屏蔽隔板22以蝕刻方式形成，則如第4A及4B圖所示，其單一側面或複數側面會呈現弧面狀U，使該牆部32b之縱剖面呈現由上至下寬度b,r不一致的牆面(即頂部寬度a>牆部最大寬度r>牆部最小寬度b)；或者，如第4C及4D圖所示，該牆部32b之最大寬度r等於該頂部22a之寬度a(即頂部寬度a=牆部最大寬度r>牆部最小寬度b)。
又，藉由該屏蔽隔板22與該金屬層25之設計，故於該電子封裝件2運作時，該些電子元件21不會遭受外界之電磁干擾(EMI)，且該些電子元件21之間亦不會相互電磁干擾，因而該電子封裝件2的電性運作功能得以正常，進而不會影響整體該電子封裝件2的電性效能。
本發明亦提供一種電子封裝件2，其包括：一基板20、複數電子元件21、一屏蔽隔板22、一包覆層24、以及一金屬層25。
所述之電子元件21係設於該基板20上並電性連接該基板20。
所述之屏蔽隔板22係藉由導電材料(如錫膏9)結合於 該基板20上並電性連接該基板20且圍繞於該電子元件21周圍。
所述之包覆層24係形成於該基板20上，以令該包覆層24包覆該電子元件21與該屏蔽隔板22，且令該屏蔽隔板22之部分表面外露於該包覆層24之側面24c。
所述之金屬層25係形成於該包覆層24之第二表面24b與側面24c上並接觸及電性連接該屏蔽隔板22。
於一實施例中，該屏蔽隔板22係包含一頂部22a及一結合該基板20並支撐該頂部22a之牆部22b,32b，其中，該頂部22a之部分表面係接觸該金屬層25，且該頂部22a之寬度a係大於該牆部22b,32b之寬度b。例如，該包覆層24係包覆該牆部22b,32b。
於一實施例中，該牆部22b,32b係包含有複數內牆220與圍繞該複數內牆之複數外牆221，且各該內牆220之間的間隙t係小於各該外牆221之間的間隙d。例如，該基板20上設有至少二該電子元件21，且該內牆220設於兩該電子元件21之間，部分該內牆220之頂部22a與該金屬層25之間具有該包覆層24。
於一實施例中，該牆部32b之縱剖面之寬度b,r係不一致。
於一實施例中，該屏蔽隔板22復包含至少一支撐該頂部22a之柱部22c。例如，該牆部22b與該柱部22c係交錯排列。
於一實施例中，該包覆層24之側面24c係為相對該 基板20之傾斜面。
綜上所述，本發明之電子封裝件及其製法，係藉由該金屬層的設計，以減少該屏蔽隔板的牆部的寬度，故本發明之電子封裝件能減少錫膏之使用量，因而能避免發生銲料擴散之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧基板
21‧‧‧電子元件
22‧‧‧屏蔽隔板
22a‧‧‧頂部
24‧‧‧包覆層
24c‧‧‧側面
25‧‧‧金屬層

Claims (22)

  1. 一種電子封裝件，係包括：基板，係具有相對之第一側與第二側；電子元件，係設於該基板之第一側上；屏蔽隔板，係設於該基板之第一側上；包覆層，係具有相對之第一表面、第二表面與鄰近之側面，且以該第一表面結合至該基板之第一側上並包覆該電子元件與該屏蔽隔板，並令該屏蔽隔板之部分表面外露於該包覆層之側面，而未外露於該包覆層之第二表面；以及金屬層，係形成於該包覆層上並接觸外露於該包覆層之該屏蔽隔板之部分表面。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽隔板係包含一頂部及結合該基板並支撐該頂部之牆部，其中，該頂部之部分表面係接觸該金屬層，且該頂部之寬度係大於該牆部之寬度。
  3. 如申請專利範圍第2項所述之電子封裝件，其中，該包覆層係包覆該牆部。
  4. 如申請專利範圍第2項所述之電子封裝件，其中，該牆部係包含有複數內牆與圍繞該內牆之複數外牆，且各該內牆之間的間隙係小於各該外牆之間的間隙。
  5. 如申請專利範圍第4項所述之電子封裝件，其中，該基板上設有至少二該電子元件，且該內牆設於兩該電子元件之間，部分該內牆之頂部與該金屬層之間具有 該包覆層。
  6. 如申請專利範圍第2項所述之電子封裝件，其中，該屏蔽隔板復包含支撐該頂部之柱部。
  7. 如申請專利範圍第6項所述之電子封裝件，其中，該牆部與柱部係交錯排列。
  8. 如申請專利範圍第2項所述之電子封裝件，其中，該牆部之縱剖面之寬度係不一致。
  9. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層之側面係為相對該基板之傾斜面。
  10. 如申請專利範圍第1項所述之電子封裝件，其中，該金屬層復形成於該包覆層之側面上。
  11. 一種電子封裝件之製法，係包括：設置電子元件與屏蔽隔板於一基板上；形成包覆層於該基板上，以令該包覆層包覆該電子元件與屏蔽隔板，其中，該包覆層形成有凹部，以令該屏蔽隔板之部分表面外露於該凹部之壁面；以及形成金屬層於該包覆層上並延伸至該凹部中，以令該金屬層接觸外露於該凹部之該屏蔽隔板之部分表面。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該屏蔽隔板係包含一頂部及結合該基板並支撐該頂部之牆部，其中，該頂部之部分表面係接觸該金屬層，且該頂部之寬度係大於該牆部之寬度。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其 中，該包覆層係包覆該牆部。
  14. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該牆部係包含有複數內牆與圍繞該內牆之複數外牆，且各該內牆之間的間隙係小於各該外牆之間的間隙。
  15. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該基板上設有至少二該電子元件，且該內牆設於兩該電子元件之間，部分該內牆之頂部與該金屬層之間具有該包覆層。
  16. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該屏蔽隔板復包含支撐該頂部之柱部。
  17. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該牆部與柱部係交錯排列。
  18. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該牆部之縱剖面之寬度係不一致。
  19. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該凹部之縱剖面之寬度不一致。
  20. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該凹部之壁面係為相對該基板之傾斜面。
  21. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該金屬層復形成於該凹部之壁面上。
  22. 如申請專利範圍第11項所述之電子封裝件之製法，復包括於形成該金屬層之後，沿該凹部進行切單製程。
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