KR20150047168A - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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KR20150047168A
KR20150047168A KR1020130126885A KR20130126885A KR20150047168A KR 20150047168 A KR20150047168 A KR 20150047168A KR 1020130126885 A KR1020130126885 A KR 1020130126885A KR 20130126885 A KR20130126885 A KR 20130126885A KR 20150047168 A KR20150047168 A KR 20150047168A
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South Korea
Prior art keywords
lead
solder
conductive bump
semiconductor package
semiconductor chip
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KR1020130126885A
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English (en)
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KR101563911B1 (ko
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전형일
박인배
김병진
박노선
배재민
정지영
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020130126885A priority Critical patent/KR101563911B1/ko
Priority to TW103135955A priority patent/TWI556370B/zh
Priority to US14/521,417 priority patent/US9184148B2/en
Publication of KR20150047168A publication Critical patent/KR20150047168A/ko
Priority to US14/875,672 priority patent/US9543235B2/en
Application granted granted Critical
Publication of KR101563911B1 publication Critical patent/KR101563911B1/ko

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Abstract

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 마이크로 리드프레임과 반도체 칩 간을 연결하는 솔더 조인트 부분을 결합력을 향상시킬 수 있는 구조로 새롭게 개선시킨 반도체 패키지에 관한 것이다.
이를 위해, 본 발명은 반도체 칩과, 반도체 칩이 실장되는 다수의 리드와, 반도체 칩의 본딩패드와 각 리드 간을 전기적으로 연결하는 전도성 범프와, 반도체 칩을 비롯하여 리드 및 전도성 범프를 봉지시키며 몰딩된 몰딩 컴파운드 수지를 포함하는 반도체 패키지에 있어서, 상기 전도성 범프의 구리필러 사이즈를 리드에 비하여 더 큰 것으로 채택하여, 구리필러의 끝단에 형성된 솔더가 리드의 본드핑거 상면에 솔더링될 때, 솔더가 본드핑거의 일부 또는 전체 표면적를 감싸주며 솔더링된 것을 특징으로 하는 반도체 패키지를 제공한다.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}
본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 마이크로 리드프레임과 반도체 칩 간을 연결하는 솔더 조인트 부분을 결합력을 향상시킬 수 있는 구조로 새롭게 개선시킨 반도체 패키지에 관한 것이다.
일반적으로, 반도체 패키지를 제조하기 위한 기판의 한 종류인 금속 재질의 리드프레임은 전체 골격을 이루는 사이드프레임과, 반도체 칩이 실장되는 칩탑재판과, 상기 사이드프레임과 칩탑재판을 일체로 연결하는 타이바와, 사이드프레임으로부터 칩탑재판의 사방 모서리에 인접되게 연장된 다수의 리드를 포함하여 구성된다.
최근에는 반도체 패키지를 칩의 크기에 가깝게 제조하기 위하여 리드프레임을 매우 얇고 작게 제작하고 있고, 또한 단위 생산성을 향상시키기 위하여 다수의 반도체 패키지 영역이 한꺼번에 매트릭스 배열을 이루도록 제작되고 있으며, 이렇게 제작된 리드프레임중 하나를 소위 "마이크로 리드프레임(MLF: Micro Lead Frame)"이라 칭한다.
여기서, 마이크로 리드프레임을 이용한 반도체 패키지 구조를 첨부한 도 1 및 도 2를 참조로 살펴보면 다음과 같다.
도 1에 도시된 반도체 패키지는 소잉 공정에 의하여 낱개 단위로 분리된 상태를 나타낸 단면도로서, 반도체 칩(10)과 각 리드(20) 간을 도전성 와이어가 아닌 전도성 범프 또는 솔더볼 등과 같은 플립칩을 이용하여 전기적 신호 교환 가능하게 연결시킨 점에 특징이 있다.
기존과 같이, 반도체 칩의 본딩패드와 각 리드 간을 도전성 와이어로 연결하게 되면, 도전성 와이어의 루프 형성을 위한 높이를 확보해야 하기 때문에 반도체 패키지의 전체적인 두께가 증가하는 단점이 있다.
이와 달리, 도 1에 도시된 반도체 패키지는 반도체 칩(10)의 본딩패드와 각 리드(20) 간을 플립칩을 이용하여 전기적 신호 교환 가능하게 연결함에 따라, 반도체 패키지의 전체적인 두께를 감소시켜 경박단소화를 실현시킬 수 있는 장점을 제공한다.
도 1 및 도 2를 참조하면, 상기 마이크로 리드프레임의 각 리드(20)는 반도체 칩(10)을 실장하기 위한 칩탑재판 역할도 겸비하는 구조로 구비되고, 각 리드의 끝단과 인접한 중앙부에는 그라운드 패드(26)가 배열된다.
또한, 상기 각 리드(20)는 플립칩이 부착되는 자리인 본드핑거(22, bond finger)와 각종 전자기기의 마더보드에 대한 전기적 연결을 위한 랜드부(24, land)로 구분되며, 본드핑거(22)의 저면에는 에칭 처리에 의하여 두께가 감소된 에칭부(28, etching))가 형성된다.
따라서, 상기 반도체 칩(10)을 각 리드(20)의 본드핑거(22)에 부착하되, 반도체 칩(10)의 본딩패드(12)와 각 리드(20)의 본드핑거(22)를 플립칩을 매개로 전기적 신호 교환 가능하게 연결한 다음, 반도체 칩(10)과 플립칩 등을 몰딩 컴파운드 수지(40)로 봉지시키는 몰딩 공정이 진행됨으로써, 첨부한 도 1에 도시된 바와 같은 종래의 반도체 패키지가 완성된다.
이때, 상기 플립칩은 그 일례로서, 반도체 칩(10)의 본딩패드(12)에 도금 등의 공정에 의하여 성정시킨 구리필러와, 구리필러의 끝단에 도금에 의하여 일체로 형성되는 솔더로 구성되는 전도성 범프(30)로 채택된다.
또한, 상기 각 리드(20)의 랜드부(24)의 외측면 및 저면은 외부로 노출되고, 또한 각 리드(20)의 에칭부(28)에는 몰딩 컴파운드 수지(40)가 채워져 각 리드(20)와 몰딩 컴파운드 수지(40) 간의 결합력이 증대된다.
한편, 상기한 반도체 패키지의 커스토머들은 리드(20)들의 파인피치(fine pitch)를 요구하고 있기 때문에 각 리드의 폭(width)을 감소시킬 수 밖에 없고, 또한 플립칩으로 채택된 전도성 범프는 전기적 성능 향상을 위하여 보다 큰 사이즈를 요구하고 있는 실정에 있다.
이에, 각 리드의 폭은 감소하고, 반면에 전도성 범프의 사이즈는 커짐에 따라, 각 리드에 대한 전도성 범프의 솔더 조인트 부분이 약화되는 단점이 있다.
즉, 현재 전도성 범프(30)의 구리필러의 사이즈(직경)는 50㎛이고, 리드(20)의 본드핑거(22) 폭은 70㎛로 채택되어 구리필러의 끝단에 형성된 솔더가 각 리드(20)의 본드핑거(22)에 용이하게 안착되면서 전기적으로 융착될 수 있으나, 각 리드의 파인피치 요구 및 전도성 범프의 구리필러 사이즈 증가 요구에 부응하여 각 리드의 폭을 감소시키는 동시에 전도성 범프의 사이즈를 증가하는 경우, 각 리드에 대한 전도성 범프의 솔더 조인트 부분이 약화될 수 밖에 없는 단점이 있다.
본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 마이크로 리드프레임을 이용한 반도체 패키지 제조시, 각 리드의 폭을 감소시키는 동시에 전도성 범프의 구리필러 사이즈를 증가시키더라도, 각 리드와 전도성 범프의 솔더 간의 조인트 부분에 대한 접합력을 보다 견고한 수준으로 향상시킬 수 있도록 한 반도체 패키지를 제공하는데 그 목적이 있다.
상기한 목적을 달성하기 위한 본 발명은: 반도체 칩과, 반도체 칩이 실장되는 다수의 리드와, 반도체 칩의 본딩패드와 각 리드 간을 전기적으로 연결하는 전도성 범프와, 반도체 칩을 비롯하여 리드 및 전도성 범프를 봉지시키며 몰딩된 몰딩 컴파운드 수지를 포함하는 반도체 패키지에 있어서, 상기 전도성 범프의 구리필러 사이즈를 리드에 비하여 더 큰 것으로 채택하여, 구리필러의 끝단에 형성된 솔더가 리드의 본드핑거 상면에 솔더링될 때, 솔더가 본드핑거의 일부 또는 전체 표면적를 감싸주며 솔더링된 것을 특징으로 하는 반도체 패키지를 제공한다.
바람직하게는, 상기 본드핑거의 양측면에는 에칭 공정에 의하여 오목부가 형성된 것을 특징으로 한다.
특히, 상기 본드핑거의 솔더가 융착되는 부분의 폭은 에칭 공정에 의하여 본드핑거의 본래 폭에 비하여 보다 작은 네로우 넥부로 형성된 것을 특징으로 한다.
또한, 상기 본드핑거의 솔더가 융착되는 부분의 상면에는 딤플이 형성된 것을 특징으로 한다.
상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.
본 발명에 따르면, 마이크로 리드프레임을 이용한 반도체 패키지 제조시, 각 리드의 폭을 감소시키는 동시에 전도성 범프의 구리필러 사이즈를 증가시켜서, 각 리드와 전도성 범프의 솔더 간의 조인트 부분에 대한 접합력을 보다 견고한 수준으로 향상시킬 수 있다.
즉, 각 리드의 파인피치 요구 및 전도성 범프의 구리필러 사이즈 증가 요구에 부응하여 각 리드의 폭을 감소시키는 동시에 전도성 범프의 사이즈를 증가시키더라도, 솔더가 리드를 감싸는 구조로 솔더링이 이루어지도록 함으로써, 각 리드에 대한 전도성 범프의 솔더 조인트 부분에 대한 견고한 접합력을 제공할 수 있다.
도 1 및 도 2는 종래의 반도체 패키지 및 마이크로 리드프레임을 나타낸 단면도,
도 3 및 도 4는 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도,
도 5는 본 발명의 다른 실시예에 따른 반도체 패키지를 나타낸 단면도,
도 6은 본 발명의 또 다른 실시예에 따른 반도체 패키지를 나타낸 단면도,
도 7은 본 발명에 따른 반도체 패키지의 각 리드 폭과 범프 사이즈를 대비한 개략도.
이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.
본 발명은 마이크로 리드프레임을 이용한 반도체 패키지 제조시, 커스토머의 요구에 따라 각 리드의 파인피치 배열에 따른 리드 폭을 감소시키는 동시에 전도성 범프의 구리필러 사이즈를 증가시키더라도, 각 리드와 전도성 범프의 솔더 간의 조인트 부분에 대한 접합력을 견고한 수준으로 향상시킬 수 있도록 한 점에 주안점이 있다.
첨부한 도 3 및 도 4를 참조하면, 본 발명에 따른 반도체 패키지는 칩탑재판 역할을 하는 다수의 리드(20)와, 각 리드(20)에 실장되는 반도체 칩(10)과, 반도체 칩(10)의 본딩패드(12)와 각 리드(20)의 본드핑거(22) 간을 전기적으로 연결하는 전도성 범프(30)와, 반도체 칩(10)을 비롯하여 리드(20) 및 전도성 범프(30)를 봉지시키며 몰딩된 몰딩 컴파운드 수지(40) 등을 포함하여 구성된다.
상기 각 리드(20)는 그 길이방향을 따라 안쪽 영역은 플립칩이 부착되는 자리인 본드핑거(22, bond finger)로 형성되고, 바깥쪽 영역은 각종 전자기기의 마더보드에 대한 전기적 연결을 위한 랜드부(24, land)로 형성되며, 본드핑거(22)의 저면에는 에칭 처리에 의하여 두께가 감소된 에칭부(28, etching))가 형성된다.
바람직하게는, 도 7에 도시된 바와 같이 본 발명의 각 리드(20)들은 커스토머의 파인피치 요구에 따라 그 폭이 약 60㎛로 감소시킨 것으로 채택되고, 반면 리드에 도전 가능하게 융착되는 전도성 범프(30)의 구리필러(32) 사이즈는 전기적 성능 향상을 위하여 약 120㎛로 증가시킨 것으로 채택된다.
이렇게 리드(20)의 폭을 감소시키는 동시에 구리필러(32) 사이즈를 증가시키더라도, 각 리드(20)와 전도성 범프의 솔더(34) 간의 조인트 부분에 대한 접합력을 견고한 수준으로 향상시킬 수 있다.
즉, 상기 전도성 범프(30)의 구리필러(32)의 끝단에 형성된 솔더(34)가 리드(20)의 본드핑거(22) 상면에 솔더링될 때, 솔더(34)가 본드핑거(22)의 일부 또는 전체 표면적를 감싸주도록 함으로써, 각 리드(20)와 전도성 범프의 솔더(34) 간의 조인트 부분에 대한 접합력을 견고한 수준으로 향상시킬 수 있다.
바람직하게는, 상기 본드핑거(22)의 양측면에는 에칭 공정에 의하여 오목부(23)가 형성되는 바, 솔더(34)가 오목부(23)에 채워지도록 함으로써, 각 리드(20)의 본드핑거(22)와 전도성 범프(30)의 솔더(34) 간의 조인트 부분에 대한 접합력을 견고하게 유지시킬 수 있다.
본 발명의 다른 실시예로서, 첨부한 도 5에서 보듯이 상기 각 리드(20)의 본드핑거(22)와 전도성 범프(34)의 솔더(34) 간의 조인트 부분에 대한 접합력을 보다 견고한 수준으로 향상시킬 수 있도록 상기 본드핑거(22)의 솔더(34)가 융착되는 부분의 폭은 에칭 공정에 의하여 본드핑거(22)의 본래 폭에 비하여 보다 작은 네로우 넥부(27, narrow neck)로 형성된다.
따라서, 상기 전도성 범프(30)의 구리필러(32)의 끝단에 형성된 솔더(34)가 리드(20)의 본드핑거(22) 상면에 솔더링될 때, 솔더(34)가 본드핑거(22)의 일부 또는 전체 표면적를 감싸주되, 각 리드(20)의 본드핑거(22)에 네로우 넥부(27)가 형성됨에 따라, 솔더(34)가 보다 용이하게 본드핑거(22)의 표면적을 감싸줄 수 있게 되고, 결국 각 리드(20)의 본드핑거(22)와 전도성 범프(30)의 솔더(34) 간의 조인트 부분에 대한 접합력을 보다 견고한 수준으로 향상시킬 수 있다.
본 발명의 또 다른 실시예로서, 첨부한 도 6에서 보듯이 상기 각 리드(20)의 본드핑거(22)와 전도성 범프(34)의 솔더(34) 간의 조인트 부분에 대한 접합력을 보다 견고한 수준으로 향상시킬 수 있도록 상기 본드핑거(22)의 솔더(34)가 융착되는 부분의 상면에는 딤플(29)이 형성된다.
따라서, 상기 전도성 범프(30)의 구리필러(32)의 끝단에 형성된 솔더(34)가 리드(20)의 본드핑거(22) 상면에 솔더링될 때, 솔더(34)가 본드핑거(22)의 일부 또는 전체 표면적를 감싸주되, 각 리드(20)의 본드핑거(22)에 딤플(29)이 형성됨에 따라, 솔더(34)가 딤플(29)내에 채워지면서 보다 용이하게 본드핑거(22)의 표면적을 감싸줄 수 있게 되고, 마찬가지로 각 리드(20)의 본드핑거(22)와 전도성 범프(30)의 솔더(34) 간의 조인트 부분에 대한 접합력을 보다 견고한 수준으로 향상시킬 수 있다.
10 : 반도체 칩
12 : 본딩패드
20 : 리드
22 : 본드핑거
23 : 오목부
24 : 랜드부
26 : 그라운드 패드
27 : 네로우 넥부
28 : 에칭부
29 : 딤플
30 : 전도성 범프
32 : 구리필러
34 : 솔더
40 : 몰딩 컴파운드 수지

Claims (4)

  1. 반도체 칩(10)과, 반도체 칩(10)이 실장되는 다수의 리드(20)와, 반도체 칩(10)의 본딩패드(12)와 각 리드(20)의 본드핑거(22) 간을 전기적으로 연결하는 전도성 범프(30)와, 반도체 칩(10)을 비롯하여 리드(20) 및 전도성 범프(30)를 봉지시키며 몰딩된 몰딩 컴파운드 수지(40)를 포함하는 반도체 패키지에 있어서,
    상기 전도성 범프(30)의 구리필러(32) 사이즈를 리드(20)의 폭에 비하여 더 큰 것으로 채택하여, 구리필러(32)의 끝단에 형성된 솔더(34)가 리드(20)의 본드핑거(22) 상면에 솔더링될 때, 솔더(34)가 본드핑거(22)의 일부 또는 전체 표면적를 감싸주며 솔더링되도록 한 것을 특징으로 하는 반도체 패키지.
  2. 청구항 1에 있어서,
    상기 본드핑거(22)의 양측면에는 에칭 공정에 의하여 오목부(23)가 형성된 것을 특징으로 하는 반도체 패키지.
  3. 청구항 1에 있어서,
    상기 본드핑거(22)의 솔더(34)가 융착되는 부분의 폭은 에칭 공정에 의하여 본드핑거(22)의 본래 폭에 비하여 보다 작은 네로우 넥부(27)로 형성된 것을 특징으로 하는 반도체 패키지.
  4. 청구항 1에 있어서,
    상기 본드핑거(22)의 솔더(34)가 융착되는 부분의 상면에는 딤플(29)이 형성된 것을 특징으로 하는 반도체 패키지.
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US20150115422A1 (en) 2015-04-30
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US20160118319A1 (en) 2016-04-28
KR101563911B1 (ko) 2015-10-28
US9543235B2 (en) 2017-01-10
US9184148B2 (en) 2015-11-10

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