TWI619224B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI619224B
TWI619224B TW106110778A TW106110778A TWI619224B TW I619224 B TWI619224 B TW I619224B TW 106110778 A TW106110778 A TW 106110778A TW 106110778 A TW106110778 A TW 106110778A TW I619224 B TWI619224 B TW I619224B
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substrate
layer
cladding layer
electronic package
item
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TW106110778A
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TW201838134A (zh
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張書齊
王維賓
蕭憲隆
鄭坤一
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矽品精密工業股份有限公司
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Priority to TW106110778A priority Critical patent/TWI619224B/zh
Priority to CN201710227780.7A priority patent/CN108666279B/zh
Priority to US15/628,416 priority patent/US10903088B2/en
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Publication of TWI619224B publication Critical patent/TWI619224B/zh
Publication of TW201838134A publication Critical patent/TW201838134A/zh
Priority to US17/123,630 priority patent/US11728178B2/en
Priority to US18/343,544 priority patent/US20230343603A1/en

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Abstract

一種電子封裝件及其製法，係於設有電子元件之基板上形成包覆該電子元件之包覆層，且於該包覆層之上表面形成金屬材質之遮蔽層，並使該遮蔽層之延伸部沿該包覆層之角落延伸至該基板之側面而未延伸至該基板下側，以避免該遮蔽層接觸該基板下側之植球墊而造成短路之問題。

Description

電子封裝件及其製法
本發明係有關一種封裝技術，尤指一種能防止電磁干擾之半導體封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品要求具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，簡稱EMI)產生。
如第1圖所示，習知具有EMI屏蔽(shielding)之射頻(Radio frequency，簡稱RF)模組1，其將複數如射頻及非射頻式晶片之電子元件11電性連接在一基板10上，再以係如環氧樹脂之封裝層13包覆各該電子元件11，之後於該封裝層13之頂面13a與側面13c及該基板10之側面10c上以如濺鍍(sputtering)等方式形成一金屬層15，以藉由該金屬層15電性連接該基板10之側面10c之接地結構100，再與系統大地電性連接，藉以保護該些電子元件11免受外界EMI影響而受損。
惟，習知射頻模組1中，位於該基板10之底側外圍之 植球墊101因距離該基板10之邊緣太近，故於濺鍍該金屬層15時，該金屬層15容易溢鍍至該基板10之底側，致使該溢鍍的金屬層15a接觸該植球墊101而發生短路問題。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：基板，係具有相對之第一側與第二側及鄰接該第一側與第二側之側面；電子元件，係設於該基板之第一側上並電性連接該基板；包覆層，係形成於該基板之第一側上以包覆該電子元件，其中，該包覆層係具有結合該基板第一側之第一表面、相對該第一表面之第二表面、及鄰接該第一與第二表面之側面；以及遮蔽層，係形成於該包覆層之第二表面上且具有延伸部，該延伸部係自該包覆層之第二表面之部分邊緣沿該包覆層之側面延伸至該基板之側面而未延伸至該基板之第二側，以令該包覆層之部分側面與該基板之部分側面外露於該遮蔽層。
本發明復提供一種電子封裝件之製法，係包括：設置至少一電子元件於一基板上，其中，該基板係具有相對之第一側與第二側及鄰接該第一側與第二側之側面，且該電子元件係設於該基板之第一側上並電性連接該基板；形成包覆層於該基板上，以令該包覆層包覆該電子元件，其中，該包覆層係具有結合該基板第一側之第一表面、相對該第一表面之第二表面、及鄰接該第一與第二表面之側面；以 及形成遮蔽層於該包覆層之第二表面上，其中，該遮蔽層係具有延伸部，該延伸部係自該包覆層之第二表面之部分邊緣沿該包覆層之側面延伸至該基板之側面而未延伸至該基板之第二側，以令該包覆層之部分側面與該基板之部分側面外露於該遮蔽層。
前述之製法中，該遮蔽層之製程係包括：提供一承載結構，其包含複數基板及連結於各該基板之間的隔離部；設置該電子元件於該基板上，且以該包覆層包覆該電子元件；於該包覆層中形成複數穿孔，其中，該穿孔係延伸至該基板之側面，且該穿孔之位置係對應該基板之角落之隔離部位置；形成該遮蔽層於該包覆層之第二表面上，且該遮蔽層延伸至該穿孔中以形成該延伸部；以及沿該隔離部進行切割以分離各該基板。
前述之電子封裝件及其製法中，該基板係具有複數電性接觸墊，且該些電性接觸墊係外露於該基板之第二側。
前述之電子封裝件及其製法中，該基板係具有接觸該遮蔽層之接地部。例如，該接地部係連通該基板之側面以接觸該延伸部。
前述之電子封裝件及其製法中，該包覆層係為絕緣材。
前述之電子封裝件及其製法中，該遮蔽層係為導電材。
前述之電子封裝件及其製法中，該延伸部係自該包覆層之第二表面之角落朝該基板之第二側之角落延伸。
由上可知，本發明之電子封裝件及其製法，主要藉由遮蔽層之延伸部自包覆層之第二表面之部分邊緣沿包覆層之側面延伸至基板之側面而未延伸至基板之第二側，以令包覆層之部分側面與基板之部分側面外露於遮蔽層，使該延伸部不會接觸基板之電性接觸墊，故相較於習知技術，本發明能有效避免短路之發生。
1‧‧‧射頻模組
10,20’‧‧‧基板
10c,13c,20c,22c‧‧‧側面
100‧‧‧接地結構
101‧‧‧植球墊
11,21‧‧‧電子元件
13‧‧‧封裝層
13a‧‧‧頂面
15,15a‧‧‧金屬層
2‧‧‧電子封裝件
20‧‧‧承載結構
20”‧‧‧隔離部
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧線路層
201‧‧‧電性接觸墊
202‧‧‧接地部
210‧‧‧銲線
210’‧‧‧導電凸塊
22‧‧‧包覆層
22a‧‧‧第一表面
22b‧‧‧第二表面
23‧‧‧遮蔽層
23a‧‧‧延伸部
230‧‧‧穿孔
230a‧‧‧端面
A‧‧‧交界處
S‧‧‧切割路徑
第1圖係為習知射頻模組之剖面示意圖；第2A至2D圖係為本發明之電子封裝件之製法的剖面示意圖；第2A’及2B’圖係為第2A及2B圖之上視示意圖；以及第2D’圖係為第2D圖之立體放大示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如 「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一承載結構20，其具有相對之第一側20a與第二側20b，且於該承載結構20之第一側20a上設有複數電子元件21。接著，形成一包覆層22於該承載結構20之第一側20a上，以令該包覆層22包覆該些電子元件21。
於本實施例中，該承載結構20係為整版面型式，其包含複數陣列排設之基板20’，如第2A’圖所示，且各該基板20’之間連結有隔離部20”。例如，該基板20’係為具有核心層之線路構造或無核心層(coreless)之線路構造，其具有複數線路層200，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且形成該基板20’之主要材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該基板20’亦可為其它承載晶片之承載件，如有機板材、晶圓(wafer)、或其他具有金屬佈線(routing)之載板，並不限於上述。
再者，該線路層200係定義有複數接地部202，且該線路層200於該第二側20b上具有複數電性接觸墊201。
又，該些電子元件21係依所需之數量佈設於各該基板20’上，其可為主動元件、被動元件或其組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。具體地，該電子元件21係為射頻晶片(例如：藍芽晶片或Wi-Fi晶片)，但亦可為其它不受電磁波干擾之電子元件。例如，該電子元件21具有複數電極墊(圖略)，其可藉由複數銲線210以打線方式電性連接該線路層200；或者，該電子元件21之電極墊藉由複數如銲錫材料之導電凸塊210’以覆晶方式設於該承載結構20上並電性連接該線路層200；亦或，該電子元件21直接結合及電性連接該線路層200。然而，有關該電子元件21電性連接該承載結構20之方式不限於上述。
另外，該包覆層22係具有相對之第一表面22a與第二表面22b，使該包覆層22之第一表面22a結合至該承載結構20之第一側20a上。具體地，該包覆層22係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20之第一側20a上。然而，有關該包覆層22之材質及製作方式並不限於上述。
如第2B圖所示，於該包覆層22中形成複數穿孔230，並令該穿孔230延伸至該承載結構20之第二側20b。
於本實施例中，於對應該些隔離部20”之交界處A(如第2A圖所示)形成該些穿孔230，使該些穿孔230位於各 該基板20’之角落處，且該穿孔230之端面230a呈十字形狀，如第2B’圖所示。
如第2C圖所示，透過如電鍍金屬之方式形成一遮蔽層23於該包覆層22之第二表面22b上，且該遮蔽層23延伸至該些穿孔230中以作為延伸部23a，使該遮蔽層23之延伸部23a接觸並電性連接該承載結構20之接地部202，俾供作為電磁波屏障。
於本實施例中，形成該遮蔽層23之材質如金、銀、銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等。
再者，亦可藉由塗佈(coating)、濺鍍(sputtering)、化鍍、無電鍍或蒸鍍等方式形成該遮蔽層23。
又，該遮蔽層23只需電性連接該接地部202即可，故該接地部202之位置並不限於上述。
如第2D及2D’圖所示，沿如第2C圖所示之切割路徑S(如隔離部20”)進行切單製程，以得到本發明之電子封裝件2，其中，該切割路徑S係對應該隔離部20”位置且通過該穿孔230，且該延伸部23a係自該包覆層22之第二表面22b之部分邊緣(如角落處)沿該包覆層22之側面22c延伸至該基板20’之側面20c而未延伸至該基板20’之第二側20b，以令該包覆層22之部分側面22c與該基板20’之部分側面20c外露於該遮蔽層23。
於本實施例中，該基板20’之側面20c係鄰接該第一側20a與第二側20b，且該包覆層22之側面22c係鄰接該第一表面22a與第二表面22b。
再者，該接地部202係連通該基板20’之側面20c以接觸該延伸部23a，且該些電性接觸墊201係外露於該基板20’之第二側20b。
又，該延伸部23a係自該包覆層22之第二表面22b之角落朝該基板20’之第二側20b之角落延伸，且僅延伸至該基板20’之側面20c與第二側20b之交界處而不會延伸至該第二側20b上。
另外，於後續製程中，形成複數如銲球之導電元件(圖略)於該些電性接觸墊201上，俾供後續接置如封裝結構或電路板等外部裝置(圖略)。
因此，本發明之製法係藉由該穿孔230之設計，以於形成該遮蔽層23時，該延伸部23a會自該包覆層22之第二表面22b之角落朝該基板20’之第二側20b之角落延伸，且僅延伸至該基板20’之側面20c與第二側20b之交界處而不會延伸至該第二側20b上，故相較於習知技術，本發明之延伸部23a不會溢鍍至該基板20’之第二側20b，因而該延伸部23a不會接觸該電性接觸墊201，進而有效避免該電子封裝件2發生短路。
再者，藉由該電子元件21外圍覆蓋有該遮蔽層23，使該電子封裝件2於運作時，該電子元件21不會遭受外界之電磁干擾(EMI)，故該電子封裝件2的電性運作功能得以正常，因而不會影響整體該電子封裝件2的電性效能。
本發明亦提供一種電子封裝件2，其包括：一基板20’、至少一電子元件21、一包覆層22以及一遮蔽層23。
所述之基板20’係具有相對之第一側20a與第二側20b及鄰接該第一側20a與第二側20b之側面20c。
所述之電子元件21係設於該基板20’之第一側20a上並電性連接該基板20’。
所述之包覆層22係形成於該基板20’之第一側20a上以包覆該電子元件21，其中，該包覆層22係具有結合該基板20’第一側20a之第一表面22a、相對該第一表面22a之第二表面22b、及鄰接該第一與第二表面22a,22b之側面22c。
所述之遮蔽層23係形成於該包覆層22之第二表面22b上，其中，該遮蔽層23係具有延伸部23a，係自該包覆層22之第二表面22b之部分邊緣沿該包覆層22之側面22c延伸至該基板20’之側面20c而未延伸至該基板20’之第二側20b上，以令該包覆層22之部分側面22c與該基板20’之部分側面20c外露於該遮蔽層23。
於一實施例中，該基板20’係具有複數電性接觸墊201，且該些電性接觸墊201係外露於該基板20’之第二側20b。
於一實施例中，該基板20’係具有接觸該遮蔽層23之接地部202。例如，該接地部202係連通該基板20’之側面20c以接觸該延伸部23a。
於一實施例中，該包覆層22係為絕緣材。
於一實施例中，該遮蔽層23係為導電材。
於一實施例中，該延伸部23a係自該包覆層22之第二 表面22b之角落朝該基板20’之第二側20b之角落延伸。
綜上所述，本發明之電子封裝件及其製法，係藉由該遮蔽層之延伸部自該包覆層之第二表面之部分邊緣沿該包覆層之側面延伸至該基板之側面而未延伸至該基板之第二側，以令該包覆層之部分側面與該基板之部分側面外露於該遮蔽層，使該延伸部不會接觸該電性接觸墊，故本發明能有效避免該電子封裝件發生短路。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20’‧‧‧基板
20c,22c‧‧‧側面
22‧‧‧包覆層
23‧‧‧遮蔽層
23a‧‧‧延伸部

Claims (15)

  1. 一種電子封裝件，係包括：基板，係具有相對之第一側與第二側及鄰接該第一側與第二側之側面；電子元件，係設於該基板之第一側上並電性連接該基板；包覆層，係形成於該基板之第一側上以包覆該電子元件，其中，該包覆層係具有結合該基板第一側之第一表面、相對該第一表面之第二表面、及鄰接該第一與第二表面之側面；以及遮蔽層，係形成於該包覆層之第二表面上且具有延伸部，該延伸部係自該包覆層之第二表面之部分邊緣沿該包覆層之側面延伸至該基板之側面而未延伸至該基板之第二側，以令該包覆層之部分側面與該基板之部分側面外露於該遮蔽層。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該基板係具有複數電性接觸墊，且該些電性接觸墊係外露於該基板之第二側。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該基板係具有接觸該遮蔽層之接地部。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該接地部係連通該基板之側面以接觸該延伸部。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層係為絕緣材。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該遮蔽層係為導電材。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該延伸部係自該包覆層之第二表面之角落朝該基板之第二側之角落延伸。
  8. 一種電子封裝件之製法，係包括：設置至少一電子元件於一基板上，其中，該基板係具有相對之第一側與第二側及鄰接該第一側與第二側之側面，且該電子元件係設於該基板之第一側上並電性連接該基板；形成包覆層於該基板上，以令該包覆層包覆該電子元件，其中，該包覆層係具有結合該基板第一側之第一表面、相對該第一表面之第二表面、及鄰接該第一與第二表面之側面；以及形成遮蔽層於該包覆層之第二表面上，其中，該遮蔽層係具有延伸部，該延伸部係自該包覆層之第二表面之部分邊緣沿該包覆層之側面延伸至該基板之側面而未延伸至該基板之第二側，以令該包覆層之部分側面與該基板之部分側面外露於該遮蔽層。
  9. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該遮蔽層之製程係包括：提供一承載結構，其包含複數基板及連結於各該基板之間的隔離部；設置電子元件於該基板上，且以該包覆層包覆該電 子元件；於該包覆層中形成複數穿孔，其中，該穿孔係延伸至該基板之側面，且該穿孔之位置係對應該基板之角落之隔離部位置；形成該遮蔽層於該包覆層之第二表面上，且令該遮蔽層延伸至該穿孔中而形成該延伸部；以及沿該隔離部進行切割以分離各該基板。
  10. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該基板係具有複數電性接觸墊，且該些電性接觸墊係外露於該基板之第二側。
  11. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該基板係具有接觸該遮蔽層之接地部。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該接地部係連通該基板之側面以接觸該延伸部。
  13. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該包覆層係為絕緣材。
  14. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該遮蔽層係為導電材。
  15. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該延伸部係自該包覆層之第二表面之角落朝該基板之第二側之角落延伸。
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