TWI404187B - 能避免電磁干擾之四方形扁平無引腳封裝結構及其製法 - Google Patents

能避免電磁干擾之四方形扁平無引腳封裝結構及其製法 Download PDF

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TWI404187B
TWI404187B TW099104606A TW99104606A TWI404187B TW I404187 B TWI404187 B TW I404187B TW 099104606 A TW099104606 A TW 099104606A TW 99104606 A TW99104606 A TW 99104606A TW I404187 B TWI404187 B TW I404187B
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package structure
electromagnetic interference
lead
quad flat
encapsulant
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TW099104606A
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TW201128758A (en
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姚進財
黃建屏
柯俊吉
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矽品精密工業股份有限公司
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Priority to TW099104606A priority Critical patent/TWI404187B/zh
Priority to US12/769,024 priority patent/US8736030B2/en
Publication of TW201128758A publication Critical patent/TW201128758A/zh
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Priority to US14/253,324 priority patent/US9190387B2/en

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Description

能避免電磁干擾之四方形扁平無引腳封裝結構及其製法
本發明係有關於一種封裝結構及其製法，尤指一種能避免電磁干擾之四方形扁平無引腳封裝結構(Quad Flat Non Leaded Package,QFN)及其製法。
半導體封裝件係以導線架(Lead Frame)作為晶片承載件，而該導線架包括一晶片座及形成於該晶片座周圍之複數導腳，該晶片座上黏接晶片，並以銲線電性連接該晶片與導腳後，再以封裝膠體包覆該晶片、晶片座、銲線以及導腳之內段而形成該具導線架之半導體封裝件。
除傳統導線架類型之半導體封裝件外，亦發展出縮小整體半導體封裝件尺寸之四方形扁平無引腳封裝結構，其特徵在於不具有凸伸出封裝膠體之外導腳，而能縮小整體尺寸。另一方面，半導體封裝件於運作時，多少會受外界之電磁(EMI)等雜訊干擾，導致該半導體封裝件之電性運作功能不正常，因此影響整體之電性功能。
有鑑於習知半導體封裝件易受電磁干擾之問題，而有如美國專利第5,166,772號揭露於封裝膠體中嵌埋金屬罩之結構。
請參閱第1圖，其為美國專利第5,166,772號之封裝結構立體剖視示意圖；如圖所示，係於基板(substrate)10上接置晶片11，且該晶片11以複數銲線12電性連接至該基板10，並於該晶片11外罩設一網狀之金屬罩(metal shield)13，且該基板10上具有至少一接地端14，令該金屬罩13電性連接至該接地端14，此外，於該金屬罩13、晶片11、銲線12、及部份基板10上形成封裝膠體15，以將該金屬罩13嵌埋於該封裝膠體15中，並且藉由該網狀之金屬罩13遮蔽外界電磁干擾該晶片11之運作，俾能避免電性運作功能不正常，而影響整體之電性功能。其他類似避免電磁干擾設計之封裝結構包括美國專利第4,218,578、4,838,475、4,953,002及5,030,935號所揭露者。
惟，上述之習知構造，必須先另行製作網狀之金屬罩13，因而增加製程之複雜度；之後，再將該金屬罩13罩設於該晶片11上，並且將該金屬罩13固定於該基板10上，如此則增加組裝之困難度。此外，該網狀之金屬罩13罩設於該基板10上後，於該金屬罩13、晶片11、銲線12及部份基板10上形成封裝膠體15時，該封裝膠體15必須通過網狀的金屬罩13方能覆蓋於該晶片11上，由於該金屬罩13係為網狀，當該封裝膠體15通過該金屬罩13之細密的網目時容易產生紊流，導致氣泡產生，因此易於該封裝膠體15中產生氣泡，而於後續熱製程中產生爆米花效應。
另請參閱第2圖，其為美國專利第5,557,142號之封裝結構立體剖視示意圖，係於基板20上接置晶片21，且該晶片21以複數銲線22電性連接至該基板20，又於該晶片21、銲線22及部份基板20上形成封裝膠體23，以藉由該封裝膠體23保護該晶片21、銲線22及基板20，且於該封裝膠體23之外露表面以濺鍍形成金屬層24，俾以藉由該金屬層24遮蔽外界電磁干擾。其他類似避免電磁干擾設計之封裝結構包括美國專利第5,220,489、5,311,059及7,342,303號所揭露者。
惟，上述之習知構造，雖能免除複雜之製程，但必須在該基板20上完成接置晶片21及封裝膠體23，且進行切單(singular)成為單一封裝結構後，方能於該封裝膠體23之外露表面塗佈或濺鍍形成金屬層24，而該單一封裝結構於製程中不易排放取件，因而不利於大量生產。再者，濺鍍之方式亦無法應用於封裝膠體與基板側邊齊平之封裝結構。
另外，如美國專利第7,030,469號所揭露之一種封裝結構，其係於封裝膠體上形成外露出銲線之溝槽，且該溝槽及封裝膠體上形成有與該銲線連接之導線層，以達成電磁遮蔽之效果，惟，該導線層須為非鐵金屬材料，而僅能以沉積或濺鍍方式覆蓋於溝槽及封裝膠體上，無法應用於封裝膠體與基板側邊齊平之封裝結構。再者，該導線層與該銲線為點接觸，易有接觸不良的問題。
因此，鑒於上述之問題，如何得到能避免電磁干擾之四方形扁平無引腳封裝件，實已成為目前亟欲解決之課題。
鑑於上述習知技術之種種缺失，本發明提供一種能避免電磁干擾之四方形扁平無引腳封裝結構，係包括：導線架，係具有晶片座、複數連接該晶片座之支撐部及複數環設於該晶片座周圍且不連接該晶片座之導腳；晶片，係接置於該晶片座上；銲線，係電性連接該晶片及各該導腳；封裝膠體，係包覆該晶片、銲線及導線架，並外露出該導腳側邊和底面及晶片座底面；以及遮蔽膜，係設於該封裝膠體之頂面及側面並電性連接該支撐部。
本發明復揭露一種能避免電磁干擾之四方形扁平無引腳封裝結構之製法，係包括：準備一金屬架體，係包括複數導線架及複數縱橫分布之連接條，各該導線架具有晶片座、複數連接該晶片座之支撐部及複數環設於該晶片座周圍且不連接該晶片座之導腳，其中，各該導線架藉由該些支撐部及導腳連接該連接條；於各該導線架之晶片座上接置晶片，並以銲線對應電性連接各該導腳；形成封裝膠體以包覆該連接條、晶片、銲線、晶片座、導腳及支撐部，並外露出該連接條、晶片座及導腳之底面；沿著各該連接條進行第一次裁切，以切割該封裝膠體，以於該封裝膠體中形成複數露出各該連接條及部分支撐部之溝槽；於該封裝膠體表面及溝槽中形成遮蔽膜，以令該遮蔽膜電性連接該些支撐部；以及沿著各該溝槽及各該連接條進行第二次裁切，以切割該遮蔽膜及金屬架體，俾令該遮蔽膜包覆該封裝膠體側面，並與該導腳及支撐部之側邊齊平。
所述之遮蔽膜係可以網版印刷形成於該封裝膠體之外露表面及該些溝槽中，並固化該遮蔽膜，或者，該遮蔽膜形成之方法，係包括：於該些溝槽中滴入碳質材料或含金屬粉體材料，以形成第一遮蔽膜；於該封裝膠體之外露表面及該些溝槽中之第一遮蔽膜上形成第二遮蔽膜；以及固化該第一遮蔽膜及第二遮蔽膜。
由上可知，本發明能避免電磁干擾之四方形扁平無引腳封裝結構及其製法，係於該金屬架體之各個導線架之晶片座上接置晶片，並以銲線電性連接該晶片與該些導腳，接著於該金屬架體、晶片及銲線上形成封裝膠體，然後沿著該金屬架體之該些連接條進行第一次裁切，以切割該封裝膠體，以於該封裝膠體中形成複數縱橫分割之溝槽，再於已分割之封裝膠體表面及溝槽中形成遮蔽膜，之後再沿著各該溝槽進行第二次裁切，以切割該溝槽中之遮蔽膜及連接條，以令該遮蔽膜形成於該封裝膠體之側面，本發明之方法可於切單前巧妙地透過溝槽的形成，而於其中填入電磁遮蔽材料俾與連接條接觸，而達成電磁屏蔽之效果，且利於大量生產。
此外，透過溝槽形成具電磁屏蔽性能之遮蔽膜，可避免金屬罩細密的網目容易令封裝膠體產生紊流，而有因氣泡產生而致的爆米花效應，再者，遮蔽膜與支撐部之間為面接觸，大幅改善習知技術運用銲線做點接觸之接觸不良問題。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
請參閱第3A至3E圖，係為本發明所揭露之一種能避免電磁干擾之四方形扁平無引腳封裝結構之製法。
如第3A及3A’圖所示，該第3A圖係為3A’圖之上視圖。如圖所示，首先，準備一係為銅之金屬架體30，該金屬架體30係包括複數導線架31及由複數橫向連接條301a及複數縱向連接條301b組成之連接條301，且各該導線架31具有晶片座311、複數連接該晶片座311之支撐部312及複數環設於該晶片座311周圍且不連接該晶片座311之導腳313，又該些支撐部312及導腳313連接該連接條301。
上述之導腳313具有相對應之頂面313a及底面313b，且該導腳313復具有一延伸部3130，且該延伸部3130之厚度小於各該導腳313者，俾令該延伸部3130之頂面3131與該導腳313頂面313a形成段差結構，通常，該延伸部3130之頂面3131或段差結構係可經蝕刻移除部份金屬，以令該延伸部3130之厚度小於各該導腳313。
此外，復就前述實施態樣詳細說明，如第3A圖所示，各該導線架31之支撐部312係可自晶片座311連接至橫向連接條301a與縱向連接條301b之交點，而該導腳313係藉由延伸部3130連接連接條301而未連接晶片座311。又，上述之支撐部312之厚度小於該晶片座311者。具體而言，該支撐部312之底面312b與該晶片座311底面311b及連接條301底面301d形成段差結構。當然，亦可令支撐部312之頂面312a不與該晶片座311頂面311a及連接條301頂面301c齊平或者形成段差結構，以使支撐部312之厚度小於該晶片座311，而不限於前述態樣。而該段差結構係可經蝕刻形成。
如第3B圖所示，於各該導線架31之晶片座311的頂面311a上接置晶片32，並以銲線33對應電性連接至各該導腳313之頂面313a及晶片座311之頂面311a，其中，晶片座311之電性為接地。接著，復形成封裝膠體34以包覆該連接條301、晶片32、銲線33、晶片座311、導腳313及支撐部312，並外露出該連接條301、晶片座311及導腳313之底面(301d、311b、313b)。
如第3C圖所示，沿著各該連接條301之中心線進行第一次裁切，以切割該封裝膠體34，以於該封裝膠體34中形成複數露出各該連接條301及部分支撐部312之溝槽340，且該第一次裁切之深度d係大於或等於該封裝膠體34之厚度t。具體而言，形成於該連接條301及支撐部312交接處之溝槽340係露出各該連接條301及部分支撐部312，亦即該段之裁切深度d大於該封裝膠體34之厚度t以利於後續形成之遮蔽膜電性連接該些支撐部312，而其他處之溝槽340裁切深度d則小於該封裝膠體34之厚度t，僅露出各該連接條301。另外，所形成溝槽340之寬度係大於該連接條301者。
如第3D圖所示，於該封裝膠體34之表面及溝槽340中以如網版印刷之方式形成遮蔽膜35，該遮蔽膜35之材料係碳質材料或含金屬粉體材料，且令該遮蔽膜35電性連接該些支撐部312，並於網版印刷後進行固化，如此即能藉由該遮蔽膜35之遮蔽防止該晶片32受外界電磁干擾，俾以提供正常之運作。
另請參閱第3D-1及3D-2圖，其係為形成該遮蔽膜35之另一實施例，與前述實施例之不同處在於該些溝槽340中先滴入液態之碳質材料或含金屬粉體材料，以形成第一遮蔽膜351，如第3D-1圖所示；接著，於該封裝膠體34之外露表面及該些溝槽340中之第一遮蔽膜351上形成第二遮蔽膜352，如第3D-2圖所示；最後固化該第一遮蔽膜351及第二遮蔽膜352，而形成該遮蔽膜35。
如第3E圖所示，沿著各該溝槽340中之連接條301的中心線進行第二次裁切，以切割該遮蔽膜35及金屬架體30，且該第二次裁切之寬度w2小於該第一次裁切之寬度w1，令該遮蔽膜35包覆該封裝膠體34之側面341，並與該導腳313及支撐部312之側邊齊平。
依上述之製法，本發明復提供一種能避免電磁干擾之四方形扁平無引腳封裝結構3，係包括：導線架31、晶片32、銲線33、封裝膠體34、及遮蔽膜35。
所述之導線架31具有晶片座311、複數連接該晶片座311之支撐部312及複數環設於該晶片座311周圍且不連接該晶片座311之導腳313。
該晶片32係接置於該晶片座311上，並以銲線33電性連接該晶片32與各該導腳313之頂面313a及晶片座311之頂面311a。
所述之封裝膠體34，係包覆該晶片32、銲線33及導線架31，並外露出該導腳313側邊和底面313b及晶片座311底面311b。
所述之遮蔽膜35係設於該封裝膠體34之頂面及側面並電性連接該支撐部312。該遮蔽膜係可為碳質材料或含金屬粉體材料。
在本發明之四方形扁平無引腳封裝結構中，該導腳313與遮蔽膜35係為封裝膠體34隔開，且該封裝結構3係具有齊平之側表面。詳而言之，各該導腳313係可具有一延伸至該封裝結構3側邊之延伸部3130，且該延伸部3130之厚度小於各該導腳313者，俾令該延伸部3130之頂面3131與該導腳313頂面313a形成段差結構而嵌卡於該封裝膠體34中，因此，該導腳313與遮蔽膜35係為封裝膠體34隔開。
另一方面，該支撐部312之厚度小於該晶片座311者，舉例而言，該支撐部312底面312b與該晶片座311底面311b形成段差結構，俾令該支撐部嵌卡於該封裝膠體34中。再者，因該封裝結構3係具有齊平之側表面，且該遮蔽膜35係電性連接該支撐部312，因此，該遮蔽膜35可覆蓋該支撐部312末端；或者，如第3E圖所示，該支撐部312末端可部份外露出該封裝結構3之側表面。
本發明能避免電磁干擾之四方形扁平無引腳封裝結構及其製法，係於該金屬架體之各個導線架之晶片座上接置晶片，並以銲線電性連接該晶片與該些導腳及晶片座，接著於該金屬架體、晶片及該些銲線上形成封裝膠體，然後沿著該金屬架體之該些連接條進行第一次裁切，以切割該封裝膠體，但未切割該金屬架體，以於該封裝膠體中形成複數縱橫分割之溝槽，並露出各該導線架之支撐部的部份表面，再於該封裝膠體之外露表面及該些溝槽中形成遮蔽膜，令該遮蔽膜電性連接該支撐部，之後再沿著各該溝槽進行第二次裁切，以切割該遮蔽膜及金屬架體，且令該遮蔽膜包覆該封裝膠體之側面，並分割成複數封裝單元。由於先分割該封裝膠體，但未分割該金屬架體，再於已分割之封裝膠體表面及溝槽中形成遮蔽膜，之後再完全分割該遮蔽膜及金屬架體，因此能於封裝膠體之外露表面形成遮蔽膜，以避免電磁干擾，且該製法係有利於大量生產。
此外，透過溝槽形成具電磁屏蔽性能之遮蔽膜，可避免金屬罩細密的網目容易令封裝膠體產生紊流，而有因氣泡產生而致的爆米花效應，再者，遮蔽膜與支撐部之間為面接觸，大幅改善習知技術運用銲線做點接觸之接觸不良問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10、20．．．基板
11、21．．．晶片
12、22．．．銲線
13．．．金屬罩
14．．．接地端
15、23．．．封裝膠體
24．．．金屬層
3．．．封裝結構
30．．．金屬架體
301a．．．橫向連接條
301b．．．縱向連接條
301．．．連接條
31．．．導線架
311．．．晶片座
312．．．支撐部
313．．．導腳
301c、311a、312a、313a、3131．．．頂面
301d、311b、312b、313b．．．底面
3130．．．延伸部
32．．．晶片
33．．．銲線
34．．．封裝膠體
340．．．溝槽
341．．．側面
35．．．遮蔽膜
351．．．第一遮蔽膜
352．．．第二遮蔽膜
d．．．深度
t．．．厚度
w1．．．第一次裁切之寬度
w2．．．第二次裁切之寬度
第1圖係為美國專利第5,166,772號之封裝結構立體剖視圖；
第2圖係為美國專利第5,557,142號之封裝結構立體剖視圖；；以及
第3A至3E圖係為本發明能避免電磁干擾之四方形扁平無引腳封裝結構之製法的剖視示意圖，其中，該第3A’圖為第3A圖之A-A虛線剖視圖；第3D-1及3D-2圖係為第3D圖之另一實施態樣。
3．．．封裝結構
311．．．晶片座
312．．．支撐部
313．．．導腳
3131．．．頂面
3130．．．延伸部
32．．．晶片
33．．．銲線
34．．．封裝膠體
341．．．側面
35．．．遮蔽膜
w1．．．第一次裁切之寬度
w2．．．第二次裁切之寬度

Claims (20)

  1. 一種能避免電磁干擾之四方形扁平無引腳封裝結構，係包括：導線架，係具有晶片座、複數連接該晶片座之支撐部、及複數環設於該晶片座周圍且不連接該晶片座之導腳，該支撐部之末端形成有溝槽；晶片，係接置於該晶片座上；銲線，係電性連接該晶片及各該導腳；封裝膠體，係包覆該晶片、銲線及導線架，並外露出該導腳側邊和底面、晶片座底面及該支撐部之溝槽；以及遮蔽膜，係設於該封裝膠體之頂面及側面，並電性連接該支撐部之溝槽。
  2. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，該導腳與遮蔽膜係為封裝膠體隔開。
  3. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，該封裝結構係具有齊平之側表面。
  4. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，各該導腳係具有一延伸至該封裝結構側邊之延伸部，該延伸部之厚度小於各該導腳者，且該延伸部之頂面與該導腳頂面形成段差結構而嵌卡於該封裝膠體中。
  5. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，該支撐部之厚度小於該晶片座。
  6. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，該支撐部底面與該晶片座底面形成段差結構，且該支撐部嵌卡於該封裝膠體中。
  7. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，該支撐部之末端係外露出該封裝結構之側表面。
  8. 如申請專利範圍第1項所述之能避免電磁干擾之四方形扁平無引腳封裝結構，其中，該遮蔽膜係碳質材料或含金屬粉體材料。
  9. 一種能避免電磁干擾之四方形扁平無引腳封裝結構之製法，係包括：準備一金屬架體，係包括複數導線架及複數縱橫分布之連接條，各該導線架具有晶片座、複數連接該晶片座之支撐部及複數環設於該晶片座周圍且不連接該晶片座之導腳，其中，各該導線架藉由該些支撐部及導腳連接該連接條；於各該導線架之晶片座上接置晶片，並以銲線對應電性連接各該導腳；形成封裝膠體以包覆該連接條、晶片、銲線、晶片座、導腳及支撐部，並外露出該連接條、晶片座及導腳之底面； 沿著各該連接條進行第一次裁切以切割該封裝膠體，以於該封裝膠體中形成複數露出各該連接條及部分支撐部之溝槽；於該封裝膠體表面及溝槽中形成遮蔽膜，以令該遮蔽膜電性連接該些支撐部；以及沿著各該溝槽及各該連接條進行第二次裁切，以切割該遮蔽膜及金屬架體，俾令該遮蔽膜包覆該封裝膠體側面，並與該導腳及支撐部之側邊齊平。
  10. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該金屬架體之材料係為銅。
  11. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該支撐部之厚度小於該晶片座。
  12. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該支撐部底面與該晶片座底面及連接條底面形成段差結構。
  13. 如申請專利範圍第12項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該段差結構係經蝕刻形成。
  14. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，各該導腳係具有一延伸部，且該延伸部之厚度小於各該導腳者，俾令該延伸部之頂面與該導腳頂面形成段差結構。
  15. 如申請專利範圍第14項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該段差結構係經蝕刻形成。
  16. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該溝槽之寬度係大於該連接條者。
  17. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該第二次裁切之寬度小於該第一次裁切之寬度。
  18. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，形成該遮蔽膜之材料係碳質材料或含金屬粉體材料。
  19. 如申請專利範圍第9項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，該遮蔽膜係以網版印刷形成於該封裝膠體之外露表面及該些溝槽中，並固化該遮蔽膜。
  20. 如申請專利範圍第18項所述之能避免電磁干擾之四方形扁平無引腳封裝結構之製法，其中，形成該遮蔽膜之方法，係包括：於該些溝槽中滴入液態之碳質材料或含金屬粉體材料，以形成第一遮蔽膜；於該封裝膠體之外露表面及該些溝槽中之第一遮蔽膜上形成第二遮蔽膜；以及固化該第一遮蔽膜及第二遮蔽膜。
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