TW201727847A - 引線架及其製造方法、半導體裝置 - Google Patents
引線架及其製造方法、半導體裝置 Download PDFInfo
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- TW201727847A TW201727847A TW105134397A TW105134397A TW201727847A TW 201727847 A TW201727847 A TW 201727847A TW 105134397 A TW105134397 A TW 105134397A TW 105134397 A TW105134397 A TW 105134397A TW 201727847 A TW201727847 A TW 201727847A
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- Prior art keywords
- lead frame
- single region
- semiconductor device
- wafer
- terminal
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Classifications
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Abstract
提供一種半導體裝置,包括:引線架,包括第一表面和第二表面,該第二表面背對該第一表面,該第二表面具有凹向該第一表面以形成臺階面的一部分;半導體晶片,安裝在該引線架的該第一表面上;及密封樹脂,對該引線架和該半導體晶片進行密封。其中,該臺階面包括形成有複數個凹部的非平坦表面部,並被該密封樹脂覆蓋。
Description
本發明有關一種引線架及其製造方法、半導體裝置。
已存在一種在引線架上安裝半導體晶片並藉由樹脂進行密封的半導體裝置。在這樣的半導體裝置中,工作時的發熱會導致反覆發生膨脹或收縮,故存在著引線架和樹脂的界面會產生剝離的可能性。因此,藉由在晶片墊或引線的下表面側設置段差部(高低部或臺階部),以使樹脂流入該段差部,可提高晶片墊或引線與樹脂的密著性。
【先行技術文獻】
[先前技術文獻]
[專利文獻]
[專利文獻1](日本)特開2014-044980號公報
然,在上述方法中,由於晶片墊或引線上所設置的段差部和樹脂相接觸的部分的表面積不夠大,故難以獲得預期的密著性。
本發明是鑒於上述問題而提出的,其課題在於提
供一種藉由使引線架上所設置的段差部和樹脂相接觸的部分的表面積大於先前,可提高與樹脂之間的密著性的半導體裝置。
一種半導體裝置,包括:引線架,包括第一表面和第二表面,該第二表面背對該第一表面,該第二表面具有凹向該第一表面以形成臺階面的部分;半導體晶片,安裝在該引線架的該第一表面上;及密封樹脂,對該引線架和該半導體晶片進行密封。其中,該臺階面包括形成有複數個凹部的非平坦表面部,並被該密封樹脂所覆蓋。
根據所公開的技術,能夠提供一種藉由使引線架上所設置的段差部和樹脂相接觸的部分的表面積大於先前,可提高與樹脂之間的密著性的半導體裝置。
1‧‧‧半導體裝置
10、10S、10T‧‧‧引線架(lead frame)
11‧‧‧晶片墊(die pad)
11d、12d‧‧‧段差面(臺階面)
11x、12x‧‧‧段差部(臺階部)
12‧‧‧引線
13‧‧‧凹凸部(非平坦表面部)
15‧‧‧連接部
17‧‧‧黏結材
18‧‧‧鍍膜
20‧‧‧半導體晶片
30‧‧‧金屬線
40‧‧‧樹脂部
151‧‧‧外框部
152‧‧‧阻隔條(dam bar)
153‧‧‧支撐條(support bar)
[圖1]第1實施方式的半導體裝置的示例圖。
[圖2]S比(S ratio)的說明圖。
[圖3]對在段差部的段差面上設置凹凸部的效果進行說明的圖。
[圖4]第1實施方式的半導體裝置的製造步驟的示例圖(其1)。
[圖5]第1實施方式的半導體裝置的製造步驟的示例圖(其2)。
[圖6]第1實施方式的半導體裝置的製造步驟的示例圖(其3)。
[圖7]第1實施方式的半導體裝置的製造步驟的示例圖(其4)。
[圖8]第1實施方式的半導體裝置的製造步驟的示例圖(其5)。
[圖9]第1實施方式的半導體裝置的製造步驟的示例圖(其6)。
[圖10]第2實施方式的半導體裝置的示例圖。
[圖11]第2實施方式的半導體裝置的製造步驟的示例圖(其1)。
[圖12]第2實施方式的半導體裝置的製造步驟的示例圖(其2)。
[圖13]第2實施方式的半導體裝置的製造步驟的示例圖(其3)。
[圖14]第2實施方式的半導體裝置的製造步驟的示例圖(其4)。
[圖15]第2實施方式的變形例1的半導體裝置的製造步驟的示例圖(其1)。
[圖16]第2實施方式的變形例1的半導體裝置的製造步驟的示例圖(其2)。
[圖17]第2實施方式的變形例2的半導體裝置的製造步驟的示例圖(其1)。
[圖18]第2實施方式的變形例2的半導體裝置的製造步
驟的示例圖(其2)。
[圖19]對杯剪切試驗的試驗樣品等進行說明的圖。
[圖20]實施例1的杯剪切試驗結果的示例圖。
[圖21]實施例2的杯剪切試驗結果的示例圖。
[圖22]實施例3的杯剪切試驗結果的示例圖。
[圖23]第1實施方式的另一半導體裝置的截面圖。
下面參照圖示對本發明的實施方式進行說明。需要說明的是,各圖中存在著對相同的構成部分賦予了相同的符號並對其重覆說明進行了省略的情況。
〈第1實施方式〉
〔第1實施方式的半導體裝置的結構〕
首先對第1實施方式的半導體裝置的結構進行說明。圖1是第1實施方式的半導體裝置的示例圖,圖1的(a)是仰視圖,圖1的(b)沿圖1的(a)的A-A線的截面圖,圖1的(c)是圖1的(b)的B的局部放大截面圖,圖1的(d)是圖1的(b)的B的局部放大仰視圖。然,在圖1的(a)中,為了方便,除了樹脂部40之外還實施了與圖1的(b)的截面圖相對應的陰影處理。又,在圖1的(d)中,為了方便,對樹脂部40的圖示進行了省略。
參照圖1,半導體裝置1大致具有引線架10、半導體晶片20、金屬線30(bonding wire)及樹脂部40(密封樹脂)。半導體裝置1是所謂的QFN(Quad Flat Non-leaded package)型半導體裝置。
需要說明的是,在本實施方式中,為了方便,將半導體裝置1的半導體晶片20側稱為上側或一側,將引線架10側稱為下側或另一側。又,將各部位的半導體晶片20側的面稱為一個面或上表面,將引線架10側的面稱為另一面或下表面。然,半導體裝置1也能以上下倒置的狀態進行使用或者也能以任意角度進行配置。又,平面觀察是指從引線架10的一個面的法線方向觀察對象物,平面形狀是指從引線架10的一個面的法線方向觀察對象物時的形狀。
在半導體裝置1中,引線架10具有用於安裝半導體晶片20的晶片墊11(晶片安裝部)、複數個(plural)引線12(端子部)及支撐條153。作為引線架10的材料例如可使用銅(Cu)或銅合金、42合金(Fe和Ni的合金)等。
引線12與晶片墊11電氣分離,平面觀察時,在晶片墊11的周圍按預定間距設置有複數個引線。然,引線12也不必設置在晶片墊11的周圍的4個方向,例如也可僅設置在晶片墊11的兩側。引線12的寬度例如可為0.2mm左右。引線12的間距例如可為0.4mm左右。
引線12的上表面的與金屬線30的連接的區域形成有鍍膜18。作為鍍膜18例如可使用Ag膜、Au膜、Ni/Au膜(對Ni膜和Au膜依次進行了層疊(層構)的金屬膜)及Ni/Pd/Au膜(對Ni膜、Pd膜及Au膜依次進行了層疊的金屬膜)等。藉由形成鍍膜18,可提高與金屬線30的連接性(wire bonding性)。然,鍍膜18只要根據需要形成即可。
引線架10上設置有引線架10的下表面側被進行
了薄型化的段差部。具體而言,在晶片墊11的下表面的外周設置有段差部11x。換言之,晶片墊11的下表面被形成為小於上表面的面積,段差部11x的段差面11d(下表面)在平面觀察時設置在從晶片墊11的樹脂部40的底面露出的露出面(晶片墊11的下表面)的周圍。
又,在除了從樹脂部40的側面露出的那一側之外的引線12的下表面的外周設置有段差部12x。換言之,引線12的下表面被形成為小於上表面的面積,段差部12x的段差面12d(下表面)在平面觀察時設置在除了從樹脂部40的側面露出的那一側的從樹脂部40的底面露出的露出面(引線12的下表面)的周圍。段差部11x的段差面11d和段差部12x的段差面12d被樹脂部40覆蓋。藉由設置段差部11x和12x,由於段差部11x和12x內會流入構成樹脂部40的樹脂,故可防止晶片墊11和引線12從樹脂部40脫落。
支撐條153是在對引線架10進行單片化(單個化)之前用於支撐晶片墊11的部件。需要說明的是,支撐條153的裡面進行了半蝕刻,支撐條153的厚度與段差部11x和12x大致相同。因此,支撐條153的裡面可被樹脂部40完全覆蓋,不會從樹脂部40露出。
半導體晶片20以面朝上狀態安裝在晶片墊11上。半導體晶片20例如可藉由晶片黏結薄膜(die attach film)等黏結材17安裝(die bonding)在晶片墊11上。作為黏結材17除了可使用晶片黏結薄膜等薄膜狀的黏結材之外,還可使用糊狀的黏結材。半導體晶片20的上表面側所形成的各電極端
子藉由金線或銅線等金屬線30可與引線12的上表面所形成的鍍膜18電氣連接(wire bonding)。
樹脂部40對引線架10、半導體晶片20及金屬線30進行密封。然,晶片墊11的下表面、引線12的下表面及引線12的半導體裝置1的外周緣部側的側面從樹脂部40露出。即,樹脂部40能以使晶片墊11和引線12的一部分露出的方式對半導體晶片20等進行密封。引線12的從樹脂部40露出的部分成為外部連接端子。
晶片墊11的下表面及引線12的下表面可與樹脂部40的下表面大致同面。又,引線12的半導體裝置1的外周緣部側的側面可與樹脂部40的側面大致同面。作為樹脂部40例如可採用使環氧樹脂含有填料的所謂的模壓樹脂等。
段差部11x的段差面11d和段差部12x的段差面12d上設置有高密度的凹凸部13。又,盡管沒有圖示,支撐條153的下表面也可設置有高密度的凹凸部13。需要說明的是,設置了高密度的凹凸部13的區域在圖1的(a)中以類似梨皮的模樣被進行了表示,在圖1的(b)中則以波浪線的方式被進行了表示。
又,高密度的凹凸部13並沒有形成在晶片墊11的上表面和引線12的上表面。又,高密度的凹凸部13也沒有形成在晶片墊11和引線12的從樹脂部40露出的部分。沒有形成高密度的凹凸部13的面與形成了高密度的凹凸部13的面相比為平坦面(平面)。
然,這也不是必須的,例如,也在從樹脂部40露
出的晶片墊11的下表面或引線12的下表面可形成高密度的凹凸部13。此時,由於晶片墊11的下表面或引線12的下表面上設置有焊料等結合材,故具有可提高晶片墊11或引線12與結合材的密著性的效果。
高密度的凹凸部13例如是平面形狀為大致圓形的微小的凹部(dimple)高密度縱橫排列的部分。高密度的凹凸部13例如可排列為面心格子等格子狀。又,也可對各凹部進行規則的排列。需要說明的是,在圖1的(c)中,盡管高密度的凹凸部13的各凹部的截面被示為矩形形狀,然,實際上也可形成為凹部的上表面朝上方彎曲的曲面狀的截面。
凹部的直徑優選為0.020~0.060mm,較佳為0.020~0.040mm。凹部的間距優選為0.040~0.080mm。凹部的深度優選為引線架10的板厚的35~70%左右,例如可為0.010~0.050mm左右。
然,在高密度的凹凸部13中,凹部的平面形狀也可不為大致圓形,例如還可為六邊形等多邊形。此時,多邊形的外接圓的直徑優選為0.020~0.060mm,較佳為0.020~0.040mm。多邊形的外接圓的間距優選為0.040~0.08mm。
需要說明的是,本申請中的高密度的凹凸部是指凹凸部的凹部的平面形狀為直徑0.02mm以上且0.060mm以下的圓形或者各頂點與直徑為0.02mm以上且0.060mm以下的外接圓相交的多邊形,且凹凸部的S比為1.7以上的凹凸部。這裡,S比是指如圖2所示在表面積為S0的平坦面上形成凹凸部且凹凸部的表面積為S的情況下的S0與S的比率。即,S
比=S/S0。又,在凹凸部的表面被進行了鍍銀等被覆處理的情況下,該鍍面的面積為凹凸部的表面積。
在凹部的直徑或多邊形的外接圓的直徑小於0.020mm或大於0.06mm的情況下,難以增加S比,不會提高與樹脂部的密著性。
這樣,藉由在段差部11x的段差面11d、段差部12x的段差面12d及支撐條153的下表面設置高密度的凹凸部13,可增加引線架10與樹脂部40相接觸的部分的表面積。由此可產生固著(anchor)效果,進而可提高引線架10和樹脂部40的密著性。其結果為,可防止引線架10和樹脂部40的界面剝離。需要說明的是,由於現有技術的凹凸部的S比為1~1.2左右,故難以確保具有充分的密著性。
又,藉由在段差部11x的段差面11d和段差部12x的段差面12d上設置高密度的凹凸部13,可獲得防止樹脂部40從引線架10開始的剝離的傳播的效果或防止水分進入半導體裝置1內的效果。對此參照圖3進行說明。
需要說明的是,水分一旦進入半導體裝置的樹脂部內(樹脂部和引線架的界面),則在將半導體裝置實裝至實裝基板時的回流(reflow)步驟等中,樹脂部內的水分會急劇膨脹和氣化,導致樹脂部產生裂紋(crack)等問題(所謂的爆米花(popcorn)現象)。一旦發生爆米花現象,半導體裝置就會被破壞。而在半導體裝置1中,藉由在段差部11x的段差面11d和段差部12x的段差面12d上設置高密度的凹凸部13,可防止出現爆米花現象。其結果為,可防止半導體裝置1被破壞。
圖3的(a)是比較例的半導體裝置的示例圖,其示出了段差部11x的段差面11d上沒有設置高密度的凹凸部13的半導體裝置。需要說明的是,盡管沒有圖示,然,段差部12x的段差面12d上也沒有設置高密度的凹凸部13。在圖3的(a)所示的半導體裝置200中,a所示的晶片墊11和樹脂部40的界面發生剝離後,剝離會按b、c、d、e的順序傳播並擴大。又,在水分從a所示的晶片墊11和樹脂部40的界面進入後,水分會按b、c、d、e的順序進入內部。
相對於此,在圖3的(b)所示的半導體裝置1中,段差部11x的段差面11d上設置了高密度的凹凸部13。為此,即使a所示的晶片墊11和樹脂部40的界面發生了剝離,也僅會傳播至b,由於設置了高密度的凹凸部13的部分的晶片墊11和樹脂部40的密著力較大,故可防止剝離沿c、d、e傳播並擴大。同樣,即使水分從a所示的晶片墊11和樹脂部40的界面進入,也僅會進入至b,由於設置了高密度的凹凸部13的部分的晶片墊11和樹脂部40的密著力較大,故可防止水分沿c、d、e進入內部。
以上對段差部11x進行了說明,然,就段差部12x而言也具有同樣的效果。又,在段差部11x或12x以外的部分也設置了高密度的凹凸部13的情況下,由於該部分的與樹脂部40的密著力較大,故也可與段差部11x或12x的情況同樣地獲得防止剝離的傳播的效果或防止水分的進入的效果。
〔第1實施方式的半導體裝置的製造方法〕
接下來,對第1實施方式的半導體裝置的製造方法進行說
明。圖4~圖9是第1實施方式的半導體裝置的製造步驟的示例圖。
首先,在圖4所示的步驟中準備具有預定形狀的金屬製的板材10B。板材10B是最終可沿虛線所示的切割線被切割以被單片化為每個單片化區域(單個區域)C進而成為複數個引線架10(參照圖1)的部件。作為板材10B的材料例如可使用銅(Cu)或銅合金、42合金等。板材10B的厚度例如可為100~200μm左右。需要說明的是,圖4的(a)是平面圖,圖4的(b)是沿圖4的(a)的A-A線的截面圖。在圖4的(a)的平面圖中,為了方便,還實施了與圖4的(b)的截面圖相對應的陰影處理。
接下來,在圖5所示的步驟中,在板材10B的上表面形成感光性光阻300,並在板材10B的下表面也形成感光性光阻310。然後,對光阻300和310進行曝光和顯影,以在預定位置形成開口部300x及開口部310x和310y。
開口部300x和310x是用於在板材10B上形成晶片墊11、引線12及支撐條153的開口部,平面觀察時,設置在互相重疊的位置。又,開口部310y是用於形成高密度的凹凸部13並對板材10B的下表面側進行薄型化的開口部,其設置在形成段差部11x和12x的部分和形成支撐條153的部分。開口部310y例如是複數個圓形開口縱橫排列的開口部。圓形開口的直徑優選為0.020~0.060mm,較佳為0.020~0.040mm。圓形開口的間距優選為0.040~0.080mm。
需要說明的是,圖5示出了圖4中的一個單片化區域C,圖5的(a)是仰視圖,圖5的(b)是沿圖5的(a)
的A-A線的截面圖,圖5的(c)是圖5的(b)的B的局部放大截面圖,圖5的(d)是圖5的(b)的B的局部放大仰視圖。又,在圖5的(a)和圖5的(d)中,為了方便,也實施了與圖5的(b)的截面圖相對應的陰影處理。又,設置了用於形成高密度的凹凸部13的開口部310y的區域在圖5的(a)中以類似梨皮的模樣被進行了表示,而在圖5的(b)中則以波浪線的形式被進行了表示。又,後述的圖6和圖7也同樣。
接下來,在圖6所示的步驟中以光阻300和310為蝕刻掩膜對板材10B進行蝕刻(例如,濕蝕刻)。藉由蝕刻,可在平面觀察時開口部300x和310x重疊形成的部分對板材10B進行貫通。
又,在形成了開口部310y的部分,由於蝕刻初期蝕刻液被限制進入各圓形開口的周圍(形成了光阻310的部分),故板材10B不會被進行部分蝕刻。之後,從蝕刻中期開始至蝕刻末期蝕刻液會從周圍進入,並對開口部310y的整個面進行腐食。其結果為,各圓形開口的周圍與各圓形開口的內部相比蝕刻深度較淺,故各圓形開口的內部與各圓形開口的周圍相比較窪,成為平面形狀為圓形的凹部,這樣,不僅可形成高密度的凹凸部13,還可使整體厚度變薄。
即,形成了開口部310y的段差部11x、段差部12x及支撐條153的各部分的下表面與沒有形成開口部的部分的下表面相比較窪,這樣,不僅可形成段差部11x和12x,還可對支撐條153的部分進行薄型化。又,段差部11x、段差部12x及支撐條153的各下表面都形成了高密度的凹凸部13。需要說
明的是,段差部11x的段差面11d(下表面)、段差部12x的段差面12d(下表面)及支撐條153的下表面為由樹脂部40覆蓋的區域。
又,藉由對開口部310y的開口的平面形狀或大小、間距進行改變,可形成具有各種各樣形狀或深度的凹部的高密度的凹凸部13。又,藉由對開口部310y的開口的平面形狀或大小、間距進行改變,由於蝕刻量也會發生變化,故可將段差部11x、段差部12x及支撐條153薄型化為任意厚度。
接下來,在圖7所示的步驟中對圖6所示的光阻300和310進行除去。據此,成為圖8所示的平面形狀的引線架10S。需要說明的是,圖8的(a)是仰視圖,圖8的(b)是沿圖8的(a)的A-A線的截面圖。圖8所示的引線架10S是成為引線架10的複數個單片化區域C經由連接部15被連接了的結構。連接部15具有在引線架10S的外緣部形成為框架狀的外框部151、在外框部151的內側於各單片化區域C之間被配置為格子狀的阻隔條152、及在各單片化區域C內被斜著配置的支撐條153。支撐條153的一端與外框部151或阻隔條152連接,另一端與晶片墊11的四角連接,以對晶片墊11進行支撐。又,在外框部151或阻隔條152的各單片化區域C側,以包圍晶片墊11的方式設置了複數個引線12。又,由QFN型半導體裝置可知,阻隔條152也被稱為“連接條”(connecting bar或sawing bar)。
圖7和圖8的步驟之後,也可在引線架10S的所要部分藉由電鍍等被覆手段形成Ag膜、Au膜、Ni/Au膜(對Ni膜和Au膜依次進行了層疊的金屬膜)、Ni/Pd/Au膜(對
Ni膜、Pd膜及Au膜依次進行了層疊的金屬膜)等。這裡,作為一例,為了提高引線鍵合(wire bonding)性,可在引線12的上表面上藉由鍍銀等形成鍍膜18。
繼續對半導體裝置1的製作步驟進行說明。首先,在圖9的(a)所示的步驟中,以面朝上的狀態將半導體晶片20安裝在各單片化區域C的晶片墊11上。半導體晶片20例如可藉由晶片黏結薄膜等黏結材17被安裝在晶片墊11上。在此情況下,可加熱至預定溫度以使晶片黏結薄膜硬化。作為黏結材17除了可使用晶片黏結薄膜等薄膜狀的黏結材之外,還可使用糊狀的黏結材。
接下來,在圖9的(b)所示的步驟中,將半導體晶片20的上表面側所形成的電極端子經由金屬線30與引線12的上表面所形成的鍍膜18電氣連接。金屬線30例如可採用引線鍵合的方式與半導體晶片20的電極端子和鍍膜18連接。
接下來,在圖9的(c)所示的步驟中形成對引線架10S、半導體晶片20及金屬線30進行密封的樹脂部40。作為樹脂部40例如可使用使環氧樹脂含有填料的所謂的模壓樹脂等。樹脂部40例如可通過傳遞模壓(transfer mold)法或直接模壓(compression mold)法等形成。
需要說明的是,在形成樹脂部40時,為了不使樹脂流入引線架10S的下表面,可在引線架10S的下表面貼上保護膠帶等。由於引線架10S的下表面沒有形成高密度的凹凸部13,故可在引線架10S的下面無間隙地貼上保護膠帶等,進而可確實地防止樹脂流入。
然,由於只要可確實地貼上保護膠帶等即可,例如也可僅使晶片墊11的下表面的外周部為平坦面,而在其內側形成高密度的凹凸部13。在此情況下,在完成了半導體裝置1的製作後進行實裝時,具有可提高晶片墊11的下表面和晶片墊11的下表面所設置的焊料等結合材之間的密著性的效果。
之後,沿切割線對圖9的(c)所示的結構體進行切割,使其單片化為各單片化區域C,據此可完成複數個半導體裝置(參照圖1)的製作。切割例如可通過切割機(slicer)等來進行。
需要說明的是,半導體裝置1可作為一個製品出貨,又,圖8所示的單片化前的引線架10S也可作為一個製品出貨。在此情況下,作為製品獲得了單片化前的引線架10S時,可藉由執行圖9所示的各步驟製作複數個半導體裝置1。
這樣,在引線架10S的製造步驟中就可在藉由蝕刻板材形成晶片墊11或引線12、支撐條153時所使用的蝕刻掩膜上製作用於形成高密度的凹凸部13的預定圖案。據此,藉由在與形成晶片墊11或引線12、支撐條153的步驟相同的步驟中不僅形成段差部11x和12x還對支撐條153進行薄型化,可在段差部11x、段差部12x及支撐條153的下表面形成高密度的凹凸部13。為此,可提高製造步驟的效率,還可降低製造成本。
又,由於可採用一個蝕刻掩膜同時形成晶片墊11、引線12、支撐條153、段差部11x、段差部12x及高密度的凹凸部13,故它們的位置理論上不會發生偏差。因此,可在段差部11x、段差部12x及支撐條153的預期位置形成高密度
的凹凸部13。
需要說明的是,在現有技術的方法中,由於形成晶片墊11或引線12、支撐條153的蝕刻與對表面進行粗化的處理(氧化處理、粗化電鍍處理、粗化蝕刻處理等)為不同的步驟,故製造步驟複雜,成本也高。又,在進行部分粗化的情況下,盡管採用掩膜(masking)等可對粗化區域進行限定,然,由於難以避免蝕刻所形成的引線架和粗化處理用的掩膜的位置偏差,故位置精度較差。
第一實施方式的另一半導體裝置的示例如下。圖23是該另一半導體裝置的截面圖。圖23中的半導體裝置1a包括引線12但不包括晶片墊或支撐條。半導體晶片20以面朝下的方式(flip chip bonding)安裝在引線架10上,以使半導體晶片20的電極端子藉由連接端子50(連接部件)與引線12的上表面12a連接,該連接端子50例如可為焊料隆起(solder bump)、金隆起(gold bump)、或銅隆起(copper bump)等金屬隆起。鍍膜18設置在引線12的上表面12a,其中設置了連接端子50。此時,半導體晶片20的背面(圖23中的上表面)可暴露於樹脂40的上表面,據此,可降低半導體裝置1a的厚度,並可提高半導體晶片20的散熱性。然,半導體晶片20的背面也可被樹脂40所覆蓋。
〈第2實施方式〉
第2實施方式中示出了在晶片墊的上表面等形成高密度的凹凸部的例子。需要說明的是,第2實施方式中存在著對與上述實施方式相同的構成部分的說明進行了省略的情況。
〔第2實施方式的半導體裝置的結構〕
首先,對第2實施方式的半導體裝置的結構進行說明。圖10是第2實施方式的半導體裝置的示例圖,圖10的(a)是平面圖,圖10的(b)是沿圖10的(a)的A-A線的截面圖,圖10的(c)是圖10的(b)的B的局部放大截面圖,圖10的(d)是圖10的(b)的B的局部放大平面圖。然,在圖10的(a)中,為了方便,對黏結材17、金屬線30及樹脂部40的圖示進行了省略,並實施了與圖10的(b)的截面圖相對應的陰影處理。又,在圖10的(d)中,為了方便,也對樹脂部40的圖示也進行了省略。
參照圖10,半導體裝置2與半導體裝置1(參照圖1)的不同點在於,晶片墊11、引線12及支撐條153的各上表面側都被進行了薄型化,並且晶片墊11、引線12及支撐條153的各上表面也都形成了高密度的凹凸部13。需要說明的是,設置了高密度的凹凸部13的區域在圖10的(a)中以類似梨皮的模樣被進行了表示,而在圖10的(b)中則以波浪線的形式被進行了表示。
這樣,藉由在晶片墊11、引線12及支撐條153的各上表面都設置高密度的凹凸部13,可增加晶片墊11、引線12及支撐條153的各上表面與樹脂部40相接觸的部分的表面積。為此,會產生固著效果,進而可提高引線架10和樹脂部40的密著性。其結果為,可防止引線架10和樹脂部40的界面剝離。
又,藉由在晶片墊11的上表面設置高密度的凹凸部13,黏結材17的固著效果會提高藉由黏結材17安裝在晶片
墊11的上表面的半導體晶片20的結合強度。又,就在段差面11d和12d上設置高密度的凹凸部13的效果而言,其與第1實施方式相同。
需要說明的是,與第1實施方式同樣地,為了提高引線鍵合性,也可在引線12的上表面形成銀(Ag)鍍膜等鍍膜18。銀鍍膜的厚度通常為2~6μm左右,又,即使在形成了銀鍍膜的情況下,由於高密度的凹凸部13也不會被平坦化,故可維持與形成銀鍍膜前大致相同的S比。為此,即使在引線12的上表面形成了鍍膜18的情況在,也可提高引線12和樹脂部的密著性。
然,由於與金屬線30的連接條件(引線鍵合的條件)的不同,有時不存在高密度的凹凸部13的情況也為優選。在此情況下,只要在引線12的上表面的與金屬線30連接的區域之外的部分形成高密度的凹凸部13即可。
〔第2實施方式的半導體裝置的製造方法〕
接下來,對第2實施方式的半導體裝置的製造方法進行說明。圖11~圖14是第2實施方式的半導體裝置的製造步驟的示例圖。
需要說明的是,圖11示出了圖4中的一個單片化區域C,圖11的(a)是平面圖,圖11的(b)是沿圖11的(a)的A-A線的截面圖,圖11的(c)是圖11的(b)的B的局部放大截面圖,圖11的(d)是圖11的(b)的B的局部放大平面圖。又,在圖11的(a)和圖11的(d)中,為了方便,實施了與圖11的(b)的截面圖相對應的陰影處理。又,設置了用於形成高密度的凹凸部13的開口部340y和350y的區域在圖11的(a)中以類似梨皮的模樣被進行了表示,而在圖11的(b)中則以波
浪線的形式被進行了表示。又,後述的圖12和圖13也同樣。
首先,在圖11所示的步驟中準備具有與圖4同樣的預定形狀的金屬製的板材10B,在板材10B的上表面形成感光性光阻340,並在板材10B的下表面也形成感光性光阻350。然後,對光阻340和350進行曝光和顯影,以在預定位置形成開口部340x和340y及開口部350x和350y。
開口部340x和350x是用於在板材10B上形成晶片墊11、複數個引線12及支撐條153的開口部,平面觀察時設置在互相重疊的位置。又,開口部340y是用於不僅形成高密度的凹凸部13還對板材10B的上表面側進行薄型化的開口部,其設置在成為晶片墊11、引線12及支撐條153的部分的上表面。又,開口部350y是用於不僅形成高密度的凹凸部13還對板材10B的下表面側進行薄型化的開口部,其設置在形成段差部11x和12x部分和形成支撐條153的部分。
開口部340y和350y例如是複數個圓形開口縱橫排列的開口部。圓形開口的直徑優選為0.020~0.060mm,較佳為0.020~0.040mm。圓形開口的間距優選為0.040~0.080mm。需要說明的是,開口部340y和350y也可為六邊形等多邊形,此時,該多邊形的外接圓的直徑優選為0.020mm以上且0.060mm以下,較佳為0.020~0.040mm。
這樣,就可形成覆蓋成為晶片墊11、引線12和支撐條153的部分的上表面及成為外框部151和阻隔條152的部分的上表面的光阻340。在光阻340的覆蓋成為晶片墊11、引線12及支撐條153的部分的上表面的區域可形成開口部340y。
又,還可形成覆蓋成為晶片墊11、引線12和支撐條153的部分的下表面及成為外框部151和阻隔條152的部分的下表面的光阻350。然,在光阻350的覆蓋成為段差部11x、段差部12x和支撐條153的部分的下表面的區域可形成開口部350y。
接下來,在圖12所示的步驟中以光阻340和350為蝕刻掩膜對板材10B進行蝕刻(例如,濕蝕刻)。藉由蝕刻,可在平面觀察時開口部340x和350x重疊形成的部分對板材10B進行貫通。
又,在形成了開口部340y的部分,不僅形成高密度的凹凸部13,還可使厚度變薄。即,形成了開口部340y的晶片墊11、引線12及支撐條153的各表面與沒有形成開口部的外框部151和阻隔條152的上表面相比較窪,這樣晶片墊11、引線12及支撐條153的部分就可被薄型化。
又,在形成了開口部350y的部分,不僅形成高密度的凹凸部13,還可使厚度變薄。即,形成了開口部350y的段差部11x、段差部12x及支撐條153的各下表面與沒有形成開口部的部分的下表面相比較窪,這樣不僅可形成段差部11x和12x,還可使支撐條153的部分薄型化。又,段差部11x的段差面11d、段差部12x的段差面12d及支撐條153的各下表面可形成高密度的凹凸部13。
藉由對開口部340y和開口部350y的開口的平面形狀或大小、間距進行改變,可形成具有各種各樣的形狀或深度的凹部的高密度的凹凸部13。又,藉由對開口部340y和開口部350y的開口的平面形狀或大小、間距進行改變,蝕刻量也會變化,這樣就可將晶片墊11、引線12、段差部11x、段差
部12x及支撐條153薄型化為任意厚度。
接下來,在圖13所示的步驟中對圖12所示的光阻340和350進行除去。據此,可製成圖14所示的引線架10T。在引線架10T中,外框部151的上表面和阻隔條152的上表面形成為同面。又,晶片墊11的上表面、引線12的上表面及支撐條153的上表面形成為同面。又,段差部11x的下表面、段差部12x的下表面及支撐條153的下表面形成為同面。又,外框部151的下表面、阻隔條152的下表面、晶片墊11的下表面及引線12的下表面也形成為同面。
又,從外框部151的上表面和阻隔條152的上表面至晶片墊11的上表面、引線12的上表面及支撐條153的上表面為止的間隔(深度)大於從外框部151的下表面、阻隔條152的下表面、晶片墊11的下表面及引線12的下表面至段差部11x的下表面、段差部12x的下表面及支撐條153的下表面為止的間隔(深度)。又,段差部11x、段差部12x及支撐條153的厚度薄於晶片墊11和引線12的厚度。
這樣,在第2實施方式的引線架10T中,最終被除去而不會成為製品(半導體裝置)的部分的厚度厚於最終成為製品(半導體裝置)的部分的厚度。為此,不僅可維持較高的剛性,還可使最終成為製品(半導體裝置)的部分薄型化。其結果為,可對作為最終製品的半導體裝置進行薄型化。
又,由於沒有採用為了維持剛性而使引線架本身具有複雜形狀或使用較硬材料的方法,故不會對所製成的半導體裝置的性能產生影響。
又,由於最終成為製品(半導體裝置)的部分的厚度可薄至任意厚度,故可製造出具有市場上的非一般厚度(即,具有特殊厚度)的引線架的半導體裝置。
需要說明的是,在本例中,最終被除去而不成為製品(半導體裝置)的部分為外框部151及阻隔條152。又,最終成為製品(半導體裝置)的部分為晶片墊11、引線12及支撐條153。
接下來,執行與圖9同樣的步驟,即,對所製作的結構體沿切割線進行切割,以將其單片化為每個單片化區域C,據此可獲得複數個半導體裝置2(參照圖10)。切割例如可藉由切割刀(slicer)等實行。
需要說明的是,作為上述步驟的變形例1,除了圖12和圖13所示的步驟之外,還可具有圖15和圖16的步驟。即,藉由對圖15所示的開口部340y的開口的平面形狀或大小、間距進行改變,如圖16所示,可在晶片墊11、引線12及支撐條153的上表面形成平坦的半蝕刻面。即,可不形成高密度的凹凸部13地實施半蝕刻。例如,藉由將開口部340y設計為圓形、多邊形、市松模樣(checkered pattern)等各種圖案中的任一圖案,並對該圖案的間距和尺寸進行適當選擇,可形成平面為平坦的半蝕刻面。
又,作為上述步驟的變形例2,除了圖12和圖13所示的步驟之外,還可具有圖17和圖18的步驟。即,如圖17所示,藉由使開口部340y的開口的間距擴大,如圖18所示,不僅可殘留一部分初始板厚,還可在晶片墊11、引線12及支撐條153的上表面形成高密度的凹凸部13。
〈實施例1〉
首先,製作圖19所示的試驗樣品。具體而言,在由銅構成的平坦的金屬板即引線架材100的上表面形成凹部的平面形狀為直徑0.020mm以上且0.060mm以下的圓形的凹凸部。然後,不對凹凸部的表面實施電鍍等被覆處理,僅在凹凸部上依據表1所示的製作條件形成樹脂杯140。需要說明的是,針對6個種類的S比分別製作了6個的試驗樣品,並進行了6次測定。這裡,S比=1表示沒有形成凹凸部的試驗樣品(比較例:以往的樣品)。又,求S比時的表面積的測定是通過使用3維測定激光顯微鏡(Olympus公式制LEXT OLS4100)進行的。
需要說明的是,如表1所示,作為熱歷史,在氮氣環境氣體中將試驗樣品置於175℃的溫度下一個小時,之後在大氣(空氣)中將其置於230℃的溫度下10分鐘,據此對該試驗樣品進行了加熱。該熱歷史是假設了從引線架至半導體裝置的製作步驟中的在由樹脂部對半導體晶片等進行密封前所進行的半導體晶片安裝步驟(晶片粘結步驟)和引線鍵合步驟中的加熱的熱歷史。
即,藉由這些步驟中的加熱,存在著不少引線架
氧化所導致的對樹脂部和引線架之間的密著力的影響。為此,在本試驗中,也是在對試驗樣品的引線架材100施加了相當於實際晶片粘結步驟和引線鍵合步驟的加熱的熱歷史之後,再形成樹脂杯140。據此,可獲得高可信度的試驗結果。
接下來,按照SEMI標準G69-0996所規定的步驟進行了杯剪切試驗。具體而言,將測量儀(gauge)(圖中未示)按在各試驗樣品的樹脂杯140上,以使其沿圖19的(b)的箭頭方向移動,由此對剪切強度進行了測定。試驗是在室溫(約25℃)下測量儀的高度為20μm、速度為200μm/秒的條件下進行的。
結果示於圖20。由圖20可知,比較例的試驗樣品(S比=1)的剪切強度平均值為13〔Kgf〕左右,而S比為1.8以上的試驗樣品的剪切強度平均值為17〔Kgf〕以上。即可知,S比為1.8以上時,與以往相比可大幅度地提高引線架和樹脂之間的密著性。需要說明的是,如果S比為2.5左右,則剪切強度的上升會達到飽和狀態,其原因在於,在發生引線框和樹脂的界面剝離之前,樹脂的一部分已經發生了剝離(即,發生了破壞)。
〈實施例2〉
在由銅構成的引線架材100的上表面形成與實施例1同樣的凹凸部,並在凹凸部的表面實施銀鍍,然後在實施了銀鍍的凹凸部上再形成樹脂杯140,除此之外均與實施例1相同,並進行了杯剪切試驗。需要說明的是,銀鍍膜的厚度約為6μm。
結果示於圖21。由圖21可知,比較例的試驗樣品(S比=1)的剪切強度平均值為13〔Kgf〕左右,而S比為
1.7以上的試驗樣品的剪切強度平均值為17〔Kgf〕以上。即可知,S比為1.7以上時,與以往相比可大幅度提高引線架上所形成的鍍銀膜和樹脂之間的密著性。
〈實施例3〉
在由銅構成引線架材100的上表面形成與實施例1同樣的凹凸部,並在凹凸部的表面實施鍍Ni/Pd/Au,然後在實施了鍍Ni/Pd/Au的凹凸部上再形成樹脂杯140,除此之外均與實施例1相同,並進行了杯剪切試驗。
需要說明的是,鍍Ni/Pd/Au是指在引線架材100的上表面依次層疊鍍鎳膜、鍍鈀膜和鍍金膜。在本實施例中,鍍鎳膜的厚度約為0.8μm,鍍鈀膜的厚度約為0.03μm,鍍金膜的厚度約為0.006μm。
結果示於圖22。由圖22可知,比較例的試驗樣品(S比=1)的剪切強度平均值為6〔Kgf〕左右,而S比為1.8以上的試驗樣品的剪切強度平均值為17〔Kgf〕以上。即可知,S比為1.8以上時,與以往相比可大幅度提高引線架上所形成的鍍Ni/Pd/Au膜和樹脂之間的密著性。
〈實施例的總結〉
通過在由銅構成的引線架的上表面形成凹部的平面形狀是直徑為0.020mm以上且0.060mm以下的圓並且S比為1.7以上的凹凸部即高密度的凹凸部,可增加與樹脂部相接觸的部分的表面積。由此會產生固著效果,進而可提高引線架和樹脂部之間的密著性。
又,高密度的凹凸部在實施了鍍銀或鍍Ni/Pd/Au
之後也可維持一定以上的S比,所以即使在實施了電鍍後的表面上形成了樹脂部的情況下,也可提高引線架和樹脂部之間的密著性。
又,S比為1.7~2.5左右是較佳的可使用範圍,從密著力的提高效果和/或密著力的提高會達到飽和的角度來看,S比的更好的範圍為1.8~2.0左右。
需要說明的是,在凹凸部的凹部的平面形狀是各頂點都與直徑為0.020mm以上且0.060mm以下的外接圓相交的多邊形的情況下,也確認到了同樣的效果。
以上對較佳實施方式等進行了詳細說明,但本發明並不限定於上述實施方式等,在權利要求書所記載的範圍內還可對上述實施方式等進行各種各樣的變形和置換。
例如,上述實施方式中盡管示出了在引線架上將複數個單片化區域配置為行列狀的例子,然,也可將複數個單片化區域配置為1列。又,引線架還可由1個單片化區域和從周邊側對該單片化區域進行支撐的外框部構成。
又,在上述實施方式中盡管以QFN型引線架為例進行了說明,然,本發明也可應用於其他類型的引線架。作為其他類型的例子可列舉出QFP(Quad Flat Package)型、LOC(Lead On Chip)型等。
又,上述實施方式中盡管示出了QFN型引線架具有晶片墊的例子,然,在QFN型引線架中也存在著不設置晶片墊的情況,本發明同樣也可應用於該情況。
基於上述,於本發明的一方面,提供一種半導體裝置,包括:引線架,包括第一表面和第二表面,該第二表面背
對該第一表面,該第二表面具有凹向該第一表面以形成臺階面的部分;半導體晶片,安裝在該引線架的該第一表面上;及密封樹脂,對該引線架和該半導體晶片進行密封。該臺階面包括形成有複數個凹部的非平坦表面部,並被該密封樹脂所覆蓋。
其中,該複數個凹部的每個凹部的平面形狀是圓形或多邊形,該圓形的直徑為0.020mm以上且0.060mm以下,該多邊形的外接圓具有0.020mm以上且0.060mm以下的直徑。在平面上形成該非平坦表面部的情況下,該非平坦表面部的表面積與該平面的表面積之比為1.7以上。
其中,該引線架包括作為外部連接端子的端子,該端子包括分別包括於該引線架的該第一表面和該第二表面的第一表面和第二表面。該端子的該第二表面的一部分凹向該端子的該第一表面以形成該臺階面。
其中,該密封樹脂包括側面和底面,在該端子的該第一表面和該第二表面之間延伸的該端子的側面從該密封樹脂的該側面露出,該端子的該第二表面的與凹向該端子的該第一表面的該部分不同的一部分從該密封樹脂的該底面露出。當沿垂直於該引線架的該第二表面的方向觀察時,該臺階面沿形成在述端子的該第二表面的露出了的該部分的周緣。
其中,該引線架包括安裝有該半導體晶片的晶片安裝部,該晶片安裝部包括分別包括於該引線架的該第一表面和該第二表面的第一表面和第二表面。該晶片安裝部的該第二表面的一部分凹向該晶片安裝部的該第一表面以形成該臺階面。
其中,該密封樹脂包括底面,該晶片安裝部的該
第二表面的與凹向該晶片安裝部的第一表面的該部分不同的一部分從該密封樹脂的該底面露出。當沿垂直於該引線架的該第二表面的方向觀察時,該臺階面形成在該晶片安裝部的該第二表面的露出了的該部分的周圍。
又,於本發明的另一方面,還提供一種引線架,包括:成為半導體裝置的單個區域,該單個區域包括第一表面和第二表面,該第一表面上安裝半導體晶片,該第二表面背對該第一表面,並具有凹向該第一表面以形成臺階面的部分,當密封樹脂對該單個區域和該半導體晶片進行密封時,該臺階面被該密封樹脂所覆蓋。該臺階面包括形成有複數個凹部的非平坦表面部。
其中,該複數個凹部的每個凹部的平面形狀是圓形或多邊形,該圓形的直徑為0.020mm以上且0.060mm以下,該多邊形的外接圓具有0.020mm以上且0.060mm以下的直徑。在平面上形成該非平坦表面部的情況下,該非平坦表面部的表面積與該平面的表面積之比為1.7以上。
該引線架還包括作為外部連接端子的端子,該端子包括於該單個區域,該端子包括分別包括於該單個區域的該第一表面和該第二表面的第一表面和第二表面。該端子的該第二表面的一部分凹向該端子的該第一表面以形成該臺階面。
其中,凹向該該端子的該第一表面的該部分形成在該端子的該第二表面的周緣部分。
該引線架還包括晶片安裝部,其上安裝該半導體晶片,該晶片安裝部包括於該單個區域,並包括分別包括於該
單個區域的該第一表面和該第二表面的第一表面和第二表面。該晶片安裝部的該第二表面的一部分凹向該晶片安裝部的該第一表面以形成該臺階面。
其中,凹向該晶片安裝部的該第一表面的該部分是該晶片安裝部的該第二表面的周緣部分。
該引線架還包括外框部,包圍該單個區域。該單個區域的厚度小於該外框部的厚度。
又,於本發明的另一方面,還提供一種引線架的製造方法,該引線架包括成為半導體裝置的單個區域,該單個區域包括第一表面和第二表面,該第一表面上安裝半導體晶片,該第二表面背對該第一表面。該製造方法包括:通過對金屬板進行蝕刻以形成該單個區域的步驟;及通過減少該單個區域的厚度使該單個區域的該第二表面的一部分凹向該該單個區域的第一表面以形成臺階面,並在該臺階面上形成包括複數個凹部的非平坦表面部的步驟,當密封樹脂對該單個區域和該半導體晶片進行密封時,該臺階面被該密封樹脂所覆蓋。
其中,該複數個凹部的每個凹部的平面形狀是圓形或多邊形,該圓形的直徑為0.020mm以上且0.060mm以下,該多邊形的外接圓具有0.020mm以上且0.060mm以下的直徑。在平面上形成該非平坦表面部的情況下,該非平坦表面部的表面積與該平面的表面積之比為1.7以上。
其中,在使用單一蝕刻掩膜的單一蝕刻過程中形成該單個區域和該非平坦表面部。
該引線架的製造方法還包括:形成包圍該單個區域
的外框部的步驟;及減少該單個區域的該第一表面側的該單個區域的厚度,以使該單個區域的厚度小於該外框部的厚度的步驟。
其中,在使用單一蝕刻掩膜的單一蝕刻過程中形成該單個區域和該外框部以及減少該單個區域的厚度。
1‧‧‧半導體裝置
10‧‧‧引線架
11‧‧‧晶片墊
11x‧‧‧段差部
11d‧‧‧段差面
12‧‧‧引線
12x‧‧‧段差部
12d‧‧‧段差面
13‧‧‧凹凸部
17‧‧‧接著材
18‧‧‧鍍膜
20‧‧‧半道體晶片
30‧‧‧金屬線
40‧‧‧樹脂部
153‧‧‧支撐條
A‧‧‧斷面線
B‧‧‧局部
Claims (18)
- 一種半導體裝置,包括:引線架,包括第一表面和第二表面,該第二表面位於該第一表面的相反側,該第二表面具有凹向該第一表面以形成臺階面的一部分;半導體晶片,安裝在該引線架的該第一表面上;及密封樹脂,對該引線架和該半導體晶片進行密封,其中,該臺階面包括形成有複數個凹部的非平坦表面部,並被該密封樹脂所覆蓋。
- 根據申請專利範圍第1項之半導體裝置,其中:該複數個凹部的每個凹部的平面形狀是圓形或多邊形,該圓形的直徑為0.020mm以上且0.060mm以下,該多邊形的外接圓具有0.020mm以上且0.060mm以下的直徑,及在平面上形成該非平坦表面部的情況下,該非平坦表面部的表面積與該平面的表面積之比為1.7以上。
- 根據申請專利範圍第1項之半導體裝置,其中:該引線架包括作為外部連接端子的端子,該端子包括分別包括在該引線架的該第一表面和該第二表面中的第一表面和第二表面,及該端子的該第二表面的一部分凹向該端子的該第一表面以形成該臺階面。
- 根據申請專利範圍第3項之半導體裝置,其中:該密封樹脂包括側面和底面,該第一表面和該第二表面之間延伸的該端子的側面從該密封樹脂的該側面露出,該端 子的該第二表面的與凹向該端子的該第一表面的該一部分不同的一部分從該密封樹脂的該底面露出,及當沿垂直於該引線架的該第二表面的方向觀察時,該臺階面形成在該端子的該第二表面的露出了的該一部分的周緣。
- 根據申請專利範圍第1項之半導體裝置,其中:該引線架包括安裝有該半導體晶片的晶片安裝部,該晶片安裝部包括分別包括於該引線架的該第一表面和該第二表面的第一表面和第二表面,及該晶片安裝部的該第二表面的一部分凹向該晶片安裝部的該第一表面以形成該臺階面。
- 根據申請專利範圍第5項之半導體裝置,其中:該密封樹脂包括底面,該晶片安裝部的該第二表面的與凹向該晶片安裝部的第一表面的該一部分不同的一部分從該密封樹脂的該底面露出,及當沿垂直於該引線架的該第二表面的方向觀察時,該臺階面形成在該晶片安裝部的該第二表面的露出了的該一部分的周圍。
- 一種引線架,包括:成為半導體裝置的單個區域,該單個區域包括第一表面和第二表面,該第一表面上安裝半導體晶片,該第二表面背對該第一表面,並具有凹向該第一表面以形成臺階面的一部分,當密封樹脂對該單個區域和該半導體晶片進行密封時,該臺階面被該密封樹脂覆蓋, 其中,該臺階面包括形成有複數個凹部的非平坦表面部。
- 根據申請專利範圍第7項之引線架,其中:該複數個凹部的每個凹部的平面形狀是圓形或多邊形,該圓形的直徑為0.020mm以上且0.060mm以下,該多邊形的外接圓具有0.020mm以上且0.060mm以下的直徑,及在平面上形成該非平坦表面部的情況下,該非平坦表面部的表面積與該平面的表面積之比為1.7以上。
- 根據申請專利範圍第7項之引線架,還包括:作為外部連接端子的端子,該端子包括在該單個區域中,該端子包括分別包括在該單個區域的該第一表面和該第二表面中的第一表面和第二表面,及該端子的該第二表面的一部分凹向該端子的該第一表面以形成該臺階面。
- 根據申請專利範圍第9項之引線架,其中:凹向該該端子的該第一表面的該一部分形成在該端子的該第二表面的周緣部分。
- 根據申請專利範圍第7項之引線架,還包括:晶片安裝部,其上安裝該半導體晶片,該晶片安裝部包括在該單個區域中,並包括分別包括在該單個區域的該第一表面和該第二表面中的第一表面和第二表面,其中,該晶片安裝部的該第二表面的一部分凹向該晶片安裝部的該第一表面以形成該臺階面。
- 根據申請專利範圍第11項之引線架,其中:凹向該晶片安裝部的該第一表面的該一部分是該晶片安裝 部的該第二表面的周緣部分。
- 根據申請專利範圍第7項之引線架,還包括:外框部,包圍該單個區域,其中,該單個區域的厚度小於該外框部的厚度。
- 一種引線架的製造方法,該引線架包括成為半導體裝置的單個區域,該單個區域包括第一表面和第二表面,該第一表面上安裝半導體晶片,該第二表面背對該第一表面,該製造方法包括:通過對金屬板進行蝕刻以形成該單個區域的步驟;及通過減少該單個區域的厚度使該單個區域的該第二表面的一部分凹向該該單個區域的第一表面以形成臺階面,並在該臺階面上形成包括複數個凹部的非平坦表面部的步驟,當密封樹脂對該單個區域和該半導體晶片進行密封時,該臺階面被該密封樹脂所覆蓋。
- 根據申請專利範圍第14項之引線架的製造方法,其中:該複數個凹部的每個凹部的平面形狀是圓形或多邊形,該圓形的直徑為0.020mm以上且0.060mm以下,該多邊形的外接圓具有0.020mm以上且0.060mm以下的直徑,及在平面上形成該非平坦表面部的情況下,該非平坦表面部的表面積與該平面的表面積之比為1.7以上。
- 根據申請專利範圍第14項之引線架的製造方法,其中:在使用單一蝕刻掩膜的單一蝕刻過程中形成該單個區域和該非平坦表面部。
- 根據申請專利範圍第14項之引線架的製造方法,還包括: 形成包圍該單個區域的外框部的步驟;及減少該單個區域的該第一表面側的該單個區域的厚度,以使該單個區域的厚度小於該外框部的厚度的步驟。
- 根據申請專利範圍第17項之引線架的製造方法,其中:在使用單一蝕刻掩膜的單一蝕刻過程中形成該單個區域和該外框部以及減少該單個區域的厚度。
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