CN106876359A - 引线架及其制造方法、半导体装置 - Google Patents
引线架及其制造方法、半导体装置 Download PDFInfo
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- CN106876359A CN106876359A CN201610949306.0A CN201610949306A CN106876359A CN 106876359 A CN106876359 A CN 106876359A CN 201610949306 A CN201610949306 A CN 201610949306A CN 106876359 A CN106876359 A CN 106876359A
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- Prior art keywords
- lead frame
- single region
- chip
- semiconductor device
- terminal
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Classifications
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Abstract
提供一种半导体装置,包括:引线架,包括第一表面和第二表面,所述第二表面背对所述第一表面,所述第二表面具有凹向所述第一表面以形成台阶面的一部分;半导体芯片,安装在所述引线架的所述第一表面上;及密封树脂,对所述引线架和所述半导体芯片进行密封。其中,所述台阶面包括形成有多个凹部的非平坦表面部,并被所述密封树脂覆盖。
Description
技术领域
本发明涉及一种引线架及其制造方法、半导体装置。
背景技术
已有一种在引线架上安装半导体芯片并藉由树脂进行密封的半导体装置。在这样的半导体装置中,工作时的发热会导致反复发生膨胀或收缩,故存在着引线架和树脂的界面会产生剥离的可能性。因此,藉由在芯片垫或引线的下表面侧设置段差部(高低部或台阶部),以使树脂流入段差部,可提高芯片垫或引线与树脂的密着性。
专利文献1:(日本)特开2014-044980号公报
发明内容
然而,在上述方法中,由于芯片垫或引线上所设置的段差部和树脂的接触部分的表面积不够大,故难以获得预期的密着性。
本发明是鉴于上述问题而提出的,其课题在于提供一种藉由使引线架上所设置的段差部和树脂的接触部分的表面积大于现有技术,可提高与树脂的密着性的半导体装置。
一种半导体装置,包括:引线架,包括第一表面和第二表面,所述第二表面背对所述第一表面,所述第二表面具有洼向所述第一表面以形成台阶面的部分;半导体芯片,安装在所述引线架的所述第一表面上;及密封树脂,对所述引线架和所述半导体芯片进行密封。其中,所述台阶面包括形成有多个凹部的非平坦表面部,并被所述密封树脂所覆盖。
根据所公开的技术,能够提供一种藉由使引线架上所设置的段差部和树脂的接触部分的表面积大于现有技术,可提高与树脂的密着性的半导体装置。
附图说明
图1A至图1D是第1实施方式的半导体装置的示例图。
图2是S比(S ratio)的说明图。
图3A至图3B是对在段差部的段差面上设置凹凸部的效果进行说明的图。
图4A至图4B是第1实施方式的半导体装置的制造步骤的示例图(其1)。
图5A至图5D是第1实施方式的半导体装置的制造步骤的示例图(其2)。
图6A至图6D是第1实施方式的半导体装置的制造步骤的示例图(其3)。
图7A至图7D是第1实施方式的半导体装置的制造步骤的示例图(其4)。
图8A至图8B是第1实施方式的半导体装置的制造步骤的示例图(其5)。
图9A至图9C是第1实施方式的半导体装置的制造步骤的示例图(其6)。
图10A至图10D是第2实施方式的半导体装置的示例图。
图11A至图11D是第2实施方式的半导体装置的制造步骤的示例图(其1)。
图12A至图12D是第2实施方式的半导体装置的制造步骤的示例图(其2)。
图13A至图13D是第2实施方式的半导体装置的制造步骤的示例图(其3)。
图14A至图14B是第2实施方式的半导体装置的制造步骤的示例图(其4)。
图15A至图15B是第2实施方式的变形例1的半导体装置的制造步骤的示例图(其1)。
图16A至图16B是第2实施方式的变形例1的半导体装置的制造步骤的示例图(其2)。
图17A至图17B是第2实施方式的变形例2的半导体装置的制造步骤的示例图(其1)。
图18A至图18B是第2实施方式的变形例2的半导体装置的制造步骤的示例图(其2)。
图19A至图19B是对杯剪切试验的试验样品等进行说明的图。
图20是实施例1的杯剪切试验结果的示例图。
图21是实施例2的杯剪切试验结果的示例图。
图22是实施例3的杯剪切试验结果的示例图。
图23是第1实施方式的另一半导体装置的截面图。
其中,附图标记说明如下:
1 半导体装置
10、10S、10T 引线架(lead frame)
11 芯片垫(die pad)
11d、12d 段差面(台阶面)
11x、12x 段差部(台阶部)
12 引线
13 凹凸部(非平坦表面部)
15 连接部
17 黏结材
18 镀膜
20 半导体芯片
30 金属线
40 树脂部
151 外框部
152 阻隔条(dam bar)
153 支撑条(support bar)
具体实施方式
下面参照附图对本发明的实施方式进行说明。需要说明的是,各图中存在着对相同的构成部分赋予了相同的符号并对其重复说明进行了省略的情况。
〈第1实施方式〉
(第1实施方式的半导体装置的结构)
首先对第1实施方式的半导体装置的结构进行说明。图1是第1实施方式的半导体装置的示例图,图1的(a)是仰视图,图1的(b)沿图1的(a)的A-A线的截面图,图1的(c)是图1的(b)的B的局部放大截面图,图1的(d)是图1的(b)的B的局部放大仰视图。然而,在图1的(a)中,为了方便,除了树脂部40之外还实施了与图1的(b)的截面图相对应的阴影处理。另外,在图1的(d)中,为了方便,对树脂部40的图示进行了省略。
参照图1,半导体装置1大致具有引线架10、半导体芯片20、金属线30(bondingwire)及树脂部40(密封树脂)。半导体装置1是所谓的QFN(Quad Flat Non-leadedpackage)型半导体装置。
需要说明的是,在本实施方式中,为了方便,将半导体装置1的半导体芯片20侧称为上侧或一侧,将引线架10侧称为下侧或另一侧。另外,将各部位的半导体芯片20侧的面称为一个面或上表面,将引线架10侧的面称为另一面或下表面。然而,半导体装置1也能以上下倒置的状态进行使用或者也能以任意角度进行配置。另外,平面观察是指从引线架10的一个面的法线方向观察对象物,平面形状是指从引线架10的一个面的法线方向观察对象物时的形状。
在半导体装置1中,引线架10具有用于安装半导体芯片20的芯片垫11(芯片安装部)、多个(plural)引线12(端子部)及支撑条153。作为引线架10的材料例如可使用铜(Cu)或铜合金、42合金(Fe和Ni的合金)等。
引线12与芯片垫11电气分离,平面观察时,在芯片垫11的周围按预定间距设置有多个引线。然而,引线12也不必设置在芯片垫11的周围的4个方向,例如也可仅设置在芯片垫11的两侧。引线12的宽度例如可为0.2mm左右。引线12的间距例如可为0.4mm左右。
引线12的上表面的与金属线30的连接的区域形成有镀膜18。作为镀膜18例如可使用Ag膜、Au膜、Ni/Au膜(对Ni膜和Au膜依次进行了层叠的金属膜)及Ni/Pd/Au膜(对Ni膜、Pd膜及Au膜依次进行了层叠的金属膜)等。藉由形成镀膜18,可提高与金属线30的连接性(wire bonding性)。然而,镀膜18只要根据需要形成即可。
引线架10上设置有引线架10的下表面侧被进行了薄型化的段差部。具体而言,在芯片垫11的下表面的外周设置有段差部11x。换言之,芯片垫11的下表面被形成为小于上表面的面积,段差部11x的段差面11d(下表面)在平面观察时设置在从芯片垫11的树脂部40的底面露出的露出面(芯片垫11的下表面)的周围。
另外,在除了从树脂部40的侧面露出的那一侧之外的引线12的下表面的外周设置有段差部12x。换言之,引线12的下表面被形成为小于上表面的面积,段差部12x的段差面12d(下表面)在平面观察时设置在除了从树脂部40的侧面露出的那一侧的从树脂部40的底面露出的露出面(引线12的下表面)的周围。段差部11x的段差面11d和段差部12x的段差面12d被树脂部40覆盖。藉由设置段差部11x和12x,由于段差部11x和12x内会流入构成树脂部40的树脂,故可防止芯片垫11和引线12从树脂部40脱落。
支撑条153是在对引线架10进行单片化(单个化)之前用于支撑芯片垫11的部件。需要说明的是,支撑条153的里面进行了半蚀刻,支撑条153的厚度与段差部11x和12x大致相同。因此,支撑条153的里面可被树脂部40完全覆盖,不会从树脂部40露出。
半导体芯片20以面朝上状态安装在芯片垫11上。半导体芯片20例如可藉由芯片黏结薄膜(die attach film)等黏结材17安装(die bonding)在芯片垫11上。作为黏结材17除了可使用芯片黏结薄膜等薄膜状的黏结材之外,还可使用糊状的黏结材。半导体芯片20的上表面侧所形成的各电极端子藉由金线或铜线等金属线30可与引线12的上表面所形成的镀膜18电气连接(wire bonding)。
树脂部40对引线架10、半导体芯片20及金属线30进行密封。然而,芯片垫11的下表面、引线12的下表面及引线12的半导体装置1的外周缘部侧的侧面从树脂部40露出。即,树脂部40能以使芯片垫11和引线12的一部分露出的方式对半导体芯片20等进行密封。引线12的从树脂部40露出的部分成为外部连接端子。
芯片垫11的下表面及引线12的下表面可与树脂部40的下表面大致同面。另外,引线12的半导体装置1的外周缘部侧的侧面可与树脂部40的侧面大致同面。作为树脂部40例如可采用使环氧树脂含有填料的所谓的模压树脂等。
段差部11x的段差面11d和段差部12x的段差面12d上设置有高密度的凹凸部13。另外,尽管没有图示,支撑条153的下表面也可设置有高密度的凹凸部13。需要说明的是,设置了高密度的凹凸部13的区域在图1的(a)中以类似梨皮的模样被进行了表示,在图1的(b)中则以波浪线的方式被进行了表示。
另外,高密度的凹凸部13并没有形成在芯片垫11的上表面和引线12的上表面。另外,高密度的凹凸部13也没有形成在芯片垫11和引线12的从树脂部40露出的部分。没有形成高密度的凹凸部13的面与形成了高密度的凹凸部13的面相比为平坦面(平面)。
然而,这也不是必须的,例如,也在从树脂部40露出的芯片垫11的下表面或引线12的下表面可形成高密度的凹凸部13。此时,由于芯片垫11的下表面或引线12的下表面上设置有焊料等结合材,故具有可提高芯片垫11或引线12与结合材的密着性的效果。
高密度的凹凸部13例如是平面形状为大致圆形的微小的凹部(dimple)高密度纵横排列的部分。高密度的凹凸部13例如可排列为面心格子等格子状。另外,也可对各凹部进行规则的排列。需要说明的是,在图1的(c)中,尽管高密度的凹凸部13的各凹部的截面被示为矩形形状,然而,实际上也可形成为凹部的上表面朝上方弯曲的曲面状的截面。
凹部的直径优选为0.020~0.060mm,较佳为0.020~0.040mm。凹部的间距优选为0.040~0.080mm。凹部的深度优选为引线架10的板厚的35~70%左右,例如可为0.010~0.050mm左右。
然而,在高密度的凹凸部13中,凹部的平面形状也可不为大致圆形,例如还可为六边形等多边形。此时,多边形的外接圆的直径优选为0.020~0.060mm,较佳为0.020~0.040mm。多边形的外接圆的间距优选为0.040~0.08mm。
需要说明的是,本申请中的高密度的凹凸部是指凹凸部的凹部的平面形状为直径0.02mm以上且0.060mm以下的圆形或者各顶点与直径为0.02mm以上且0.060mm以下的外接圆相交的多边形,且凹凸部的S比为1.7以上的凹凸部。这里,S比是指如图2所示在表面积为S0的平坦面上形成凹凸部且凹凸部的表面积为S的情况下的S0与S的比率。即,S比=S/S0。另外,在凹凸部的表面被进行了镀银等被覆处理的情况下,该镀面的面积为凹凸部的表面积。
在凹部的直径或多边形的外接圆的直径小于0.020mm或大于0.06mm的情况下,难以增加S比,不会提高与树脂部的密着性。
这样,藉由在段差部11x的段差面11d、段差部12x的段差面12d及支撑条153的下表面设置高密度的凹凸部13,可增加引线架10与树脂部40相接触的部分的表面积。由此可产生固着(anchor)效果,进而可提高引线架10和树脂部40的密着性。其结果为,可防止引线架10和树脂部40的界面剥离。需要说明的是,由于现有技术的凹凸部的S比为1~1.2左右,故难以确保具有充分的密着性。
另外,藉由在段差部11x的段差面11d和段差部12x的段差面12d上设置高密度的凹凸部13,可获得防止树脂部40从引线架10开始的剥离的传播的效果或防止水分进入半导体装置1内的效果。对此参照图3进行说明。
需要说明的是,水分一旦进入半导体装置的树脂部内(树脂部和引线架的界面),则在将半导体装置实装至实装基板时的回流(reflow)步骤等中,树脂部内的水分会急剧膨胀和气化,导致树脂部产生裂纹(crack)等问题(所谓的爆米花(popcorn)现象)。一旦发生爆米花现象,半导体装置就会被破坏。而在半导体装置1中,藉由在段差部11x的段差面11d和段差部12x的段差面12d上设置高密度的凹凸部13,可防止出现爆米花现象。其结果为,可防止半导体装置1被破坏。
图3的(a)是比较例的半导体装置的示例图,其示出了段差部11x的段差面11d上没有设置高密度的凹凸部13的半导体装置。需要说明的是,尽管没有图示,然而,段差部12x的段差面12d上也没有设置高密度的凹凸部13。在图3的(a)所示的半导体装置200中,a所示的芯片垫11和树脂部40的界面发生剥离后,剥离会按b、c、d、e的顺序传播并扩大。另外,在水分从a所示的芯片垫11和树脂部40的界面进入后,水分会按b、c、d、e的顺序进入内部。
相对于此,在图3的(b)所示的半导体装置1中,段差部11x的段差面11d上设置了高密度的凹凸部13。为此,即使a所示的芯片垫11和树脂部40的界面发生了剥离,也仅会传播至b,由于设置了高密度的凹凸部13的部分的芯片垫11和树脂部40的密着力较大,故可防止剥离沿c、d、e传播并扩大。同样,即使水分从a所示的芯片垫11和树脂部40的界面进入,也仅会进入至b,由于设置了高密度的凹凸部13的部分的芯片垫11和树脂部40的密着力较大,故可防止水分沿c、d、e进入内部。
以上对段差部11x进行了说明,然而,就段差部12x而言也具有同样的效果。另外,在段差部11x或12x以外的部分也设置了高密度的凹凸部13的情况下,由于该部分的与树脂部40的密着力较大,故也可与段差部11x或12x的情况同样地获得防止剥离的传播的效果或防止水分的进入的效果。
(第1实施方式的半导体装置的制造方法)
接下来,对第1实施方式的半导体装置的制造方法进行说明。图4~图9是第1实施方式的半导体装置的制造步骤的示例图。
首先,在图4所示的步骤中准备具有预定形状的金属制的板材10B。板材10B是最终可沿虚线所示的切割线被切割以被单片化为每个单片化区域(单个区域)C进而成为多个引线架10(参照图1)的部件。作为板材10B的材料例如可使用铜(Cu)或铜合金、42合金等。板材10B的厚度例如可为100~200μm左右。需要说明的是,图4的(a)是平面图,图4的(b)是沿图4的(a)的A-A线的截面图。在图4的(a)的平面图中,为了方便,还实施了与图4的(b)的截面图相对应的阴影处理。
接下来,在图5所示的步骤中,在板材10B的上表面形成感光性光阻300,并在板材10B的下表面也形成感光性光阻310。然后,对光阻300和310进行曝光和显影,以在预定位置形成开口部300x及开口部310x和310y。
开口部300x和310x是用于在板材10B上形成芯片垫11、引线12及支撑条153的开口部,平面观察时,设置在互相重叠的位置。另外,开口部310y是用于形成高密度的凹凸部13并对板材10B的下表面侧进行薄型化的开口部,其设置在形成段差部11x和12x的部分和形成支撑条153的部分。开口部310y例如是多个圆形开口纵横排列的开口部。圆形开口的直径优选为0.020~0.060mm,较佳为0.020~0.040mm。圆形开口的间距优选为0.040~0.080mm。
需要说明的是,图5示出了图4中的一个单片化区域C,图5的(a)是仰视图,图5的(b)是沿图5的(a)的A-A线的截面图,图5的(c)是图5的(b)的B的局部放大截面图,图5的(d)是图5的(b)的B的局部放大仰视图。另外,在图5的(a)和图5的(d)中,为了方便,也实施了与图5的(b)的截面图相对应的阴影处理。另外,设置了用于形成高密度的凹凸部13的开口部310y的区域在图5的(a)中以类似梨皮的模样被进行了表示,而在图5的(b)中则以波浪线的形式被进行了表示。另外,后述的图6和图7也同样。
接下来,在图6所示的步骤中以光阻300和310为蚀刻掩膜对板材10B进行蚀刻(例如,湿蚀刻)。藉由蚀刻,可在平面观察时开口部300x和310x重叠形成的部分对板材10B进行贯通。
另外,在形成了开口部310y的部分,由于蚀刻初期蚀刻液被限制进入各圆形开口的周围(形成了光阻310的部分),故板材10B不会被进行部分蚀刻。之后,从蚀刻中期开始至蚀刻末期蚀刻液会从周围进入,并对开口部310y的整个面进行腐食。其结果为,各圆形开口的周围与各圆形开口的内部相比蚀刻深度较浅,故各圆形开口的内部与各圆形开口的周围相比较洼,成为平面形状为圆形的凹部,这样,不仅可形成高密度的凹凸部13,还可使整体厚度变薄。
即,形成了开口部310y的段差部11x、段差部12x及支撑条153的各部分的下表面与没有形成开口部的部分的下表面相比较洼,这样,不仅可形成段差部11x和12x,还可对支撑条153的部分进行薄型化。另外,段差部11x、段差部12x及支撑条153的各下表面都形成了高密度的凹凸部13。需要说明的是,段差部11x的段差面11d(下表面)、段差部12x的段差面12d(下表面)及支撑条153的下表面为由树脂部40覆盖的区域。
另外,藉由对开口部310y的开口的平面形状或大小、间距进行改变,可形成具有各种各样形状或深度的凹部的高密度的凹凸部13。另外,藉由对开口部310y的开口的平面形状或大小、间距进行改变,由于蚀刻量也会发生变化,故可将段差部11x、段差部12x及支撑条153薄型化为任意厚度。
接下来,在图7所示的步骤中对图6所示的光阻300和310进行除去。据此,成为图8所示的平面形状的引线架10S。需要说明的是,图8的(a)是仰视图,图8的(b)是沿图8的(a)的A-A线的截面图。图8所示的引线架10S是成为引线架10的多个单片化区域C经由连接部15被连接了的结构。连接部15具有在引线架10S的外缘部形成为框架状的外框部151、在外框部151的内侧于各单片化区域C之间被配置为格子状的阻隔条152、及在各单片化区域C内被斜着配置的支撑条153。支撑条153的一端与外框部151或阻隔条152连接,另一端与芯片垫11的四角连接,以对芯片垫11进行支撑。另外,在外框部151或阻隔条152的各单片化区域C侧,以包围芯片垫11的方式设置了多个引线12。由QFN封装型半导体装置可知,阻隔条152也被称为“连接条”(connecting bar或sawing bar)。
图7和图8的步骤之后,也可在引线架10S的所要部分藉由电镀等被覆手段形成Ag膜、Au膜、Ni/Au膜(对Ni膜和Au膜依次进行了层叠的金属膜)、Ni/Pd/Au膜(对Ni膜、Pd膜及Au膜依次进行了层叠的金属膜)等。这里,作为一例,为了提高引线键合(wire bonding)性,可在引线12的上表面上藉由镀银等形成镀膜18。
继续对半导体装置1的制作步骤进行说明。首先,在图9的(a)所示的步骤中,以面朝上的状态将半导体芯片20安装在各单片化区域C的芯片垫11上。半导体芯片20例如可藉由芯片黏结薄膜等黏结材17被安装在芯片垫11上。在此情况下,可加热至预定温度以使芯片黏结薄膜硬化。作为黏结材17除了可使用芯片黏结薄膜等薄膜状的黏结材之外,还可使用糊状的黏结材。
接下来,在图9的(b)所示的步骤中,将半导体芯片20的上表面侧所形成的电极端子经由金属线30与引线12的上表面所形成的镀膜18电气连接。金属线30例如可采用引线键合的方式与半导体芯片20的电极端子和镀膜18连接。
接下来,在图9的(c)所示的步骤中形成对引线架10S、半导体芯片20及金属线30进行密封的树脂部40。作为树脂部40例如可使用使环氧树脂含有填料的所谓的模压树脂等。树脂部40例如可通过传递模压(transfer mold)法或直接模压(compression mold)法等形成。
需要说明的是,在形成树脂部40时,为了不使树脂流入引线架10S的下表面,可在引线架10S的下表面贴上保护胶带等。由于引线架10S的下表面没有形成高密度的凹凸部13,故可在引线架10S的下面无间隙地贴上保护胶带等,进而可确实地防止树脂流入。
然而,由于只要可确实地贴上保护胶带等即可,例如也可仅使芯片垫11的下表面的外周部为平坦面,而在其内侧形成高密度的凹凸部13。在此情况下,在完成了半导体装置1的制作后进行实装时,具有可提高芯片垫11的下表面和芯片垫11的下表面所设置的焊料等结合材之间的密着性的效果。
之后,沿切割线对图9的(c)所示的结构体进行切割,使其单片化为各单片化区域C,据此可完成多个半导体装置(参照图1)的制作。切割例如可通过切割机(slicer)等来进行。
需要说明的是,半导体装置1可作为一个制品出货,另外,图8所示的单片化前的引线架10S也可作为一个制品出货。在此情况下,作为制品获得了单片化前的引线架10S时,可藉由执行图9所示的各步骤制作多个半导体装置1。
这样,在引线架10S的制造步骤中就可在藉由蚀刻板材形成芯片垫11或引线12、支撑条153时所使用的蚀刻掩膜上制作用于形成高密度的凹凸部13的预定图案。据此,藉由在与形成芯片垫11或引线12、支撑条153的步骤相同的步骤中不仅形成段差部11x和12x还对支撑条153进行薄型化,可在段差部11x、段差部12x及支撑条153的下表面形成高密度的凹凸部13。为此,可提高制造步骤的效率,还可降低制造成本。
另外,由于可采用一个蚀刻掩膜同时形成芯片垫11、引线12、支撑条153、段差部11x、段差部12x及高密度的凹凸部13,故它们的位置理论上不会发生偏差。因此,可在段差部11x、段差部12x及支撑条153的预期位置形成高密度的凹凸部13。
需要说明的是,在现有技术的方法中,由于形成芯片垫11或引线12、支撑条153的蚀刻与对表面进行粗化的处理(氧化处理、粗化电镀处理、粗化蚀刻处理等)为不同的步骤,故制造步骤复杂,成本也高。另外,在进行部分粗化的情况下,尽管采用掩膜(masking)等可对粗化区域进行限定,然而,由于难以避免蚀刻所形成的引线架和粗化处理用的掩膜的位置偏差,故位置精度较差。
第一实施方式的另一半导体装置的示例如下。图23是该另一半导体装置的截面图。图23中的半导体装置1a包括引线12但不包括芯片垫或支撑条。半导体芯片20以面朝下的方式(flip chip bonding)安装在引线架10上,以使半导体芯片20的电极端子藉由连接端子50(连接部件)与引线12的上表面12a连接,该连接端子50例如可为焊料隆起(solderbump)、金隆起(gold bump)、或铜隆起(copper bump)等金属隆起。镀膜18设置在引线12的上表面12a,其中设置了连接端子50。此时,半导体芯片20的背面(图23中的上表面)可暴露于树脂40的上表面,据此,可降低半导体装置1a的厚度,并可提高半导体芯片20的散热性。然而,半导体芯片20的背面也可被树脂40所覆盖。
〈第2实施方式〉
第2实施方式中示出了在芯片垫的上表面等形成高密度的凹凸部的例子。需要说明的是,第2实施方式中存在着对与上述实施方式相同的构成部分的说明进行了省略的情况。
(第2实施方式的半导体装置的结构)
首先,对第2实施方式的半导体装置的结构进行说明。图10是第2实施方式的半导体装置的示例图,图10的(a)是平面图,图10的(b)是沿图10的(a)的A-A线的截面图,图10的(c)是图10的(b)的B的局部放大截面图,图10的(d)是图10的(b)的B的局部放大平面图。然而,在图10的(a)中,为了方便,对黏结材17、金属线30及树脂部40的图示进行了省略,并实施了与图10的(b)的截面图相对应的阴影处理。另外,在图10的(d)中,为了方便,也对树脂部40的图示也进行了省略。
参照图10,半导体装置2与半导体装置1(参照图1)的不同点在于,芯片垫11、引线12及支撑条153的各上表面侧都被进行了薄型化,并且芯片垫11、引线12及支撑条153的各上表面也都形成了高密度的凹凸部13。需要说明的是,设置了高密度的凹凸部13的区域在图10的(a)中以类似梨皮的模样被进行了表示,而在图10的(b)中则以波浪线的形式被进行了表示。
这样,藉由在芯片垫11、引线12及支撑条153的各上表面都设置高密度的凹凸部13,可增加芯片垫11、引线12及支撑条153的各上表面与树脂部40相接触的部分的表面积。为此,会产生固着效果,进而可提高引线架10和树脂部40的密着性。其结果为,可防止引线架10和树脂部40的界面剥离。
另外,藉由在芯片垫11的上表面设置高密度的凹凸部13,黏结材17的固着效果会提高藉由黏结材17安装在芯片垫11的上表面的半导体芯片20的结合强度。另外,就在段差面11d和12d上设置高密度的凹凸部13的效果而言,其与第1实施方式相同。
需要说明的是,与第1实施方式同样地,为了提高引线键合性,也可在引线12的上表面形成银(Ag)镀膜等镀膜18。银镀膜的厚度通常为2~6μm左右,另外,即使在形成了银镀膜的情况下,由于高密度的凹凸部13也不会被平坦化,故可维持与形成银镀膜前大致相同的S比。为此,即使在引线12的上表面形成了镀膜18的情况在,也可提高引线12和树脂部的密着性。
然而,由于与金属线30的连接条件(引线键合的条件)的不同,有时不存在高密度的凹凸部13的情况也为优选。在此情况下,只要在引线12的上表面的与金属线30连接的区域之外的部分形成高密度的凹凸部13即可。
(第2实施方式的半导体装置的制造方法)
接下来,对第2实施方式的半导体装置的制造方法进行说明。图11~图14是第2实施方式的半导体装置的制造步骤的示例图。
需要说明的是,图11示出了图4中的一个单片化区域C,图11的(a)是平面图,图11的(b)是沿图11的(a)的A-A线的截面图,图11的(c)是图11的(b)的B的局部放大截面图,图11的(d)是图11的(b)的B的局部放大平面图。另外,在图11的(a)和图11的(d)中,为了方便,实施了与图11的(b)的截面图相对应的阴影处理。另外,设置了用于形成高密度的凹凸部13的开口部340y和350y的区域在图11的(a)中以类似梨皮的模样被进行了表示,而在图11的(b)中则以波浪线的形式被进行了表示。另外,后述的图12和图13也同样。
首先,在图11所示的步骤中准备具有与图4同样的预定形状的金属制的板材10B,在板材10B的上表面形成感光性光阻340,并在板材10B的下表面也形成感光性光阻350。然后,对光阻340和350进行曝光和显影,以在预定位置形成开口部340x和340y及开口部350x和350y。
开口部340x和350x是用于在板材10B上形成芯片垫11、多个引线12及支撑条153的开口部,平面观察时设置在互相重叠的位置。另外,开口部340y是用于不仅形成高密度的凹凸部13还对板材10B的上表面侧进行薄型化的开口部,其设置在成为芯片垫11、引线12及支撑条153的部分的上表面。另外,开口部350y是用于不仅形成高密度的凹凸部13还对板材10B的下表面侧进行薄型化的开口部,其设置在形成段差部11x和12x部分和形成支撑条153的部分。
开口部340y和350y例如是多个圆形开口纵横排列的开口部。圆形开口的直径优选为0.020~0.060mm,较佳为0.020~0.040mm。圆形开口的间距优选为0.040~0.080mm。需要说明的是,开口部340y和350y也可为六边形等多边形,此时,该多边形的外接圆的直径优选为0.020mm以上且0.060mm以下,较佳为0.020~0.040mm。
这样,就可形成覆盖成为芯片垫11、引线12和支撑条153的部分的上表面及成为外框部151和阻隔条152的部分的上表面的光阻340。在光阻340的覆盖成为芯片垫11、引线12及支撑条153的部分的上表面的区域可形成开口部340y。
另外,还可形成覆盖成为芯片垫11、引线12和支撑条153的部分的下表面及成为外框部151和阻隔条152的部分的下表面的光阻350。然而,在光阻350的覆盖成为段差部11x、段差部12x和支撑条153的部分的下表面的区域可形成开口部350y。
接下来,在图12所示的步骤中以光阻340和350为蚀刻掩膜对板材10B进行蚀刻(例如,湿蚀刻)。藉由蚀刻,可在平面观察时开口部340x和350x重叠形成的部分对板材10B进行贯通。
另外,在形成了开口部340y的部分,不仅形成高密度的凹凸部13,还可使厚度变薄。即,形成了开口部340y的芯片垫11、引线12及支撑条153的各表面与没有形成开口部的外框部151和阻隔条152的上表面相比较洼,这样芯片垫11、引线12及支撑条153的部分就可被薄型化。
另外,在形成了开口部350y的部分,不仅形成高密度的凹凸部13,还可使厚度变薄。即,形成了开口部350y的段差部11x、段差部12x及支撑条153的各下表面与没有形成开口部的部分的下表面相比较洼,这样不仅可形成段差部11x和12x,还可使支撑条153的部分薄型化。另外,段差部11x的段差面11d、段差部12x的段差面12d及支撑条153的各下表面可形成高密度的凹凸部13。
藉由对开口部340y和开口部350y的开口的平面形状或大小、间距进行改变,可形成具有各种各样的形状或深度的凹部的高密度的凹凸部13。另外,藉由对开口部340y和开口部350y的开口的平面形状或大小、间距进行改变,蚀刻量也会变化,这样就可将芯片垫11、引线12、段差部11x、段差部12x及支撑条153薄型化为任意厚度。
接下来,在图13所示的步骤中对图12所示的光阻340和350进行除去。据此,可制成图14所示的引线架10T。在引线架10T中,外框部151的上表面和阻隔条152的上表面形成为同面。另外,芯片垫11的上表面、引线12的上表面及支撑条153的上表面形成为同面。另外,段差部11x的下表面、段差部12x的下表面及支撑条153的下表面形成为同面。另外,外框部151的下表面、阻隔条152的下表面、芯片垫11的下表面及引线12的下表面也形成为同面。
另外,从外框部151的上表面和阻隔条152的上表面至芯片垫11的上表面、引线12的上表面及支撑条153的上表面为止的间隔(深度)大于从外框部151的下表面、阻隔条152的下表面、芯片垫11的下表面及引线12的下表面至段差部11x的下表面、段差部12x的下表面及支撑条153的下表面为止的间隔(深度)。另外,段差部11x、段差部12x及支撑条153的厚度薄于芯片垫11和引线12的厚度。
这样,在第2实施方式的引线架10T中,最终被除去而不会成为制品(半导体装置)的部分的厚度厚于最终成为制品(半导体装置)的部分的厚度。为此,不仅可维持较高的刚性,还可使最终成为制品(半导体装置)的部分薄型化。其结果为,可对作为最终制品的半导体装置进行薄型化。
另外,由于没有采用为了维持刚性而使引线架本身具有复杂形状或使用较硬材料的方法,故不会对所制成的半导体装置的性能产生影响。
另外,由于最终成为制品(半导体装置)的部分的厚度可薄至任意厚度,故可制造出具有市场上的非一般厚度(即,具有特殊厚度)的引线架的半导体装置。
需要说明的是,在本例中,最终被除去而不成为制品(半导体装置)的部分为外框部151及阻隔条152。另外,最终成为制品(半导体装置)的部分为芯片垫11、引线12及支撑条153。
接下来,执行与图9同样的步骤,即,对所制作的结构体沿切割线进行切割,以将其单片化为每个单片化区域C,据此可获得多个半导体装置2(参照图10)。切割例如可藉由切割刀(slicer)等实行。
需要说明的是,作为上述步骤的变形例1,除了图12和图13所示的步骤之外,还可具有图15和图16的步骤。即,藉由对图15所示的开口部340y的开口的平面形状或大小、间距进行改变,如图16所示,可在芯片垫11、引线12及支撑条153的上表面形成平坦的半蚀刻面。即,可不形成高密度的凹凸部13地实施半蚀刻。例如,藉由将开口部340y设计为圆形、多边形、市松模样(checkered pattern)等各种图案中的任一图案,并对该图案的间距和尺寸进行适当选择,可形成平面为平坦的半蚀刻面。
另外,作为上述步骤的变形例2,除了图12和图13所示的步骤之外,还可具有图17和图18的步骤。即,如图17所示,藉由使开口部340y的开口的间距扩大,如图18所示,不仅可残留一部分初始板厚,还可在芯片垫11、引线12及支撑条153的上表面形成高密度的凹凸部13。
〈实施例1〉
首先,制作图19所示的试验样品。具体而言,在由铜构成的平坦的金属板即引线架材100的上表面形成凹部的平面形状为直径0.020mm以上且0.060mm以下的圆形的凹凸部。然后,不对凹凸部的表面实施电镀等被覆处理,仅在凹凸部上依据表1所示的制作条件形成树脂杯140。需要说明的是,针对6个种类的S比分别制作了6个的试验样品,并进行了6次测定。这里,S比=1表示没有形成凹凸部的试验样品(比较例:以往的样品)。另外,求S比时的表面积的测定是通过使用3维测定激光显微镜(Olympus公式制LEXT OLS4100)进行的。
(表1)
树脂的种类 | 环氧类树脂 |
高度h | 3mm |
3.568mm | |
3mm | |
表面积 | |
热历史 | |
树脂的硬化条件 | 175℃×6h(空气) |
需要说明的是,如表1所示,作为热历史,在氮气环境气体中将试验样品置于175℃的温度下一个小时,之后在大气(空气)中将其置于230℃的温度下10分钟,据此对该试验样品进行了加热。该热历史是假设了从引线架至半导体装置的制作步骤中的在由树脂部对半导体芯片等进行密封前所进行的半导体芯片安装步骤(芯片粘结步骤)和引线键合步骤中的加热的热历史。
即,藉由这些步骤中的加热,存在着不少引线架氧化所导致的对树脂部和引线架之间的密着力的影响。为此,在本试验中,也是在对试验样品的引线架材100施加了相当于实际芯片粘结步骤和引线键合步骤的加热的热历史之后,再形成树脂杯140。据此,可获得高可信度的试验结果。
接下来,按照SEMI标准G69-0996所规定的步骤进行了杯剪切试验。具体而言,将测量仪(gauge)(图中未示)按在各试验样品的树脂杯140上,以使其沿图19的(b)的箭头方向移动,由此对剪切强度进行了测定。试验是在室温(约25℃)下测量仪的高度为20μm、速度为200μm/秒的条件下进行的。
结果示于图20。由图20可知,比较例的试验样品(S比=1)的剪切强度平均值为13(Kgf)左右,而S比为1.8以上的试验样品的剪切强度平均值为17(Kgf)以上。即可知,S比为1.8以上时,与以往相比可大幅度地提高引线架和树脂之间的密着性。需要说明的是,如果S比为2.5左右,则剪切强度的上升会达到饱和状态,其原因在于,在发生引线框和树脂的界面剥离之前,树脂的一部分已经发生了剥离(即,发生了破坏)。
〈实施例2〉
在由铜构成的引线架材100的上表面形成与实施例1同样的凹凸部,并在凹凸部的表面实施银镀,然后在实施了银镀的凹凸部上再形成树脂杯140,除此之外均与实施例1相同,并进行了杯剪切试验。需要说明的是,银镀膜的厚度约为6μm。
结果示于图21。由图21可知,比较例的试验样品(S比=1)的剪切强度平均值为13(Kgf)左右,而S比为1.7以上的试验样品的剪切强度平均值为17(Kgf)以上。即可知,S比为1.7以上时,与以往相比可大幅度提高引线架上所形成的镀银膜和树脂之间的密着性。
〈实施例3〉
在由铜构成引线架材100的上表面形成与实施例1同样的凹凸部,并在凹凸部的表面实施镀Ni/Pd/Au,然后在实施了镀Ni/Pd/Au的凹凸部上再形成树脂杯140,除此之外均与实施例1相同,并进行了杯剪切试验。
需要说明的是,镀Ni/Pd/Au是指在引线架材100的上表面依次层叠镀镍膜、镀钯膜和镀金膜。在本实施例中,镀镍膜的厚度约为0.8μm,镀钯膜的厚度约为0.03μm,镀金膜的厚度约为0.006μm。
结果示于图22。由图22可知,比较例的试验样品(S比=1)的剪切强度平均值为6(Kgf)左右,而S比为1.8以上的试验样品的剪切强度平均值为17(Kgf)以上。即可知,S比为1.8以上时,与以往相比可大幅度提高引线架上所形成的镀Ni/Pd/Au膜和树脂之间的密着性。
〈实施例的总结〉
通过在由铜构成的引线架的上表面形成凹部的平面形状是直径为0.020mm以上且0.060mm以下的圆并且S比为1.7以上的凹凸部即高密度的凹凸部,可增加与树脂部相接触的部分的表面积。由此会产生固着效果,进而可提高引线架和树脂部之间的密着性。
另外,高密度的凹凸部在实施了镀银或镀Ni/Pd/Au之后也可维持一定以上的S比,所以即使在实施了电镀后的表面上形成了树脂部的情况下,也可提高引线架和树脂部之间的密着性。
另外,S比为1.7~2.5左右是较佳的可使用范围,从密着力的提高效果和/或密着力的提高会达到饱和的角度来看,S比的更好的范围为1.8~2.0左右。
需要说明的是,在凹凸部的凹部的平面形状是各顶点都与直径为0.020mm以上且0.060mm以下的外接圆相交的多边形的情况下,也确认到了同样的效果。
以上对较佳实施方式等进行了详细说明,但本发明并不限定于上述实施方式等,在权利要求书所记载的范围内还可对上述实施方式等进行各种各样的变形和置换。
例如,上述实施方式中尽管示出了在引线架上将多个单片化区域配置为行列状的例子,然而,也可将多个单片化区域配置为1列。另外,引线架还可由1个单片化区域和从周边侧对该单片化区域进行支撑的外框部构成。
另外,在上述实施方式中尽管以QFN型引线架为例进行了说明,然而,本发明也可应用于其他类型的引线架。作为其他类型的例子可列举出QFP(Quad Flat Package)型、LOC(Lead On Chip)型等。
另外,上述实施方式中尽管示出了QFN型引线架具有芯片垫的例子,然而,在QFN型引线架中也存在着不设置芯片垫的情况,本发明同样也可应用于该情况。
基于上述,于本发明的一方面,提供一种半导体装置,包括:引线架,包括第一表面和第二表面,所述第二表面背对所述第一表面,所述第二表面具有洼向所述第一表面以形成台阶面的部分;半导体芯片,安装在所述引线架的所述第一表面上;及密封树脂,对所述引线架和所述半导体芯片进行密封。所述台阶面包括形成有多个凹部的非平坦表面部,并被所述密封树脂所覆盖。
其中,所述多个凹部的每个凹部的平面形状是圆形或多边形,所述圆形的直径为0.020mm以上且0.060mm以下,所述多边形的外接圆具有0.020mm以上且0.060mm以下的直径。在平面上形成所述非平坦表面部的情况下,所述非平坦表面部的表面积与所述平面的表面积之比为1.7以上。
其中,所述引线架包括作为外部连接端子的端子,所述端子包括分别包括于所述引线架的所述第一表面和所述第二表面的第一表面和第二表面。所述端子的所述第二表面的一部分洼向所述端子的所述第一表面以形成所述台阶面。
其中,所述密封树脂包括侧面和底面,在所述端子的所述第一表面和所述第二表面之间延伸的所述端子的侧面从所述密封树脂的所述侧面露出,所述端子的所述第二表面的与洼向所述端子的所述第一表面的所述部分不同的一部分从所述密封树脂的所述底面露出。当沿垂直于所述引线架的所述第二表面的方向观察时,所述台阶面沿形成在述端子的所述第二表面的露出了的所述部分的周缘。
其中,所述引线架包括安装有所述半导体芯片的芯片安装部,所述芯片安装部包括分别包括于所述引线架的所述第一表面和所述第二表面的第一表面和第二表面。所述芯片安装部的所述第二表面的一部分洼向所述芯片安装部的所述第一表面以形成所述台阶面。
其中,所述密封树脂包括底面,所述芯片安装部的所述第二表面的与洼向所述芯片安装部的第一表面的所述部分不同的一部分从所述密封树脂的所述底面露出。当沿垂直于所述引线架的所述第二表面的方向观察时,所述台阶面形成在所述芯片安装部的所述第二表面的露出了的所述部分的周围。
另外,于本发明的另一方面,还提供一种引线架,包括:成为半导体装置的单个区域,所述单个区域包括第一表面和第二表面,所述第一表面上安装半导体芯片,所述第二表面背对所述第一表面,并具有洼向所述第一表面以形成台阶面的部分,当密封树脂对所述单个区域和所述半导体芯片进行密封时,所述台阶面被所述密封树脂所覆盖。所述台阶面包括形成有多个凹部的非平坦表面部。
其中,所述多个凹部的每个凹部的平面形状是圆形或多边形,所述圆形的直径为0.020mm以上且0.060mm以下,所述多边形的外接圆具有0.020mm以上且0.060mm以下的直径。在平面上形成所述非平坦表面部的情况下,所述非平坦表面部的表面积与所述平面的表面积之比为1.7以上。
所述引线架还包括作为外部连接端子的端子,所述端子包括于所述单个区域,所述端子包括分别包括于所述单个区域的所述第一表面和所述第二表面的第一表面和第二表面。所述端子的所述第二表面的一部分洼向所述端子的所述第一表面以形成所述台阶面。
其中,洼向所述所述端子的所述第一表面的所述部分形成在所述端子的所述第二表面的周缘部分。
所述引线架还包括芯片安装部,其上安装所述半导体芯片,所述芯片安装部包括于所述单个区域,并包括分别包括于所述单个区域的所述第一表面和所述第二表面的第一表面和第二表面。所述芯片安装部的所述第二表面的一部分洼向所述芯片安装部的所述第一表面以形成所述台阶面。
其中,洼向所述芯片安装部的所述第一表面的所述部分是所述芯片安装部的所述第二表面的周缘部分。
所述引线架还包括外框部,包围所述单个区域。所述单个区域的厚度小于所述外框部的厚度。
另外,于本发明的另一方面,还提供一种引线架的制造方法,所述引线架包括成为半导体装置的单个区域,所述单个区域包括第一表面和第二表面,所述第一表面上安装半导体芯片,所述第二表面背对所述第一表面。所述制造方法包括:通过对金属板进行蚀刻以形成所述单个区域的步骤;及通过减少所述单个区域的厚度使所述单个区域的所述第二表面的一部分洼向所述所述单个区域的第一表面以形成台阶面,并在所述台阶面上形成包括多个凹部的非平坦表面部的步骤,当密封树脂对所述单个区域和所述半导体芯片进行密封时,所述台阶面被所述密封树脂所覆盖。
其中,所述多个凹部的每个凹部的平面形状是圆形或多边形,所述圆形的直径为0.020mm以上且0.060mm以下,所述多边形的外接圆具有0.020mm以上且0.060mm以下的直径。在平面上形成所述非平坦表面部的情况下,所述非平坦表面部的表面积与所述平面的表面积之比为1.7以上。
其中,在使用单一蚀刻掩膜的单一蚀刻过程中形成所述单个区域和所述非平坦表面部。
所述引线架的制造方法还包括:形成包围所述单个区域的外框部的步骤;及减少所述单个区域的所述第一表面侧的所述单个区域的厚度,以使所述单个区域的厚度小于所述外框部的厚度的步骤。
其中,在使用单一蚀刻掩膜的单一蚀刻过程中形成所述单个区域和所述外框部以及减少所述单个区域的厚度。
Claims (18)
1.一种半导体装置,包括:
引线架,包括第一表面和第二表面,所述第二表面位于所述第一表面的相反侧,所述第二表面具有凹向所述第一表面以形成台阶面的一部分;
半导体芯片,安装在所述引线架的所述第一表面上;及
密封树脂,对所述引线架和所述半导体芯片进行密封,
其中,所述台阶面包括形成有多个凹部的非平坦表面部,并被所述密封树脂所覆盖。
2.如权利要求1所述的半导体装置,其中:
所述多个凹部的每个凹部的平面形状是圆形或多边形,所述圆形的直径为0.020mm以上且0.060mm以下,所述多边形的外接圆具有0.020mm以上且0.060mm以下的直径,及
在平面上形成所述非平坦表面部的情况下,所述非平坦表面部的表面积与所述平面的表面积之比为1.7以上。
3.如权利要求1所述的半导体装置,其中:
所述引线架包括作为外部连接端子的端子,所述端子包括分别包括在所述引线架的所述第一表面和所述第二表面中的第一表面和第二表面,及
所述端子的所述第二表面的一部分凹向所述端子的所述第一表面以形成所述台阶面。
4.如权利要求3所述的半导体装置,其中:
所述密封树脂包括侧面和底面,所述第一表面和所述第二表面之间延伸的所述端子的侧面从所述密封树脂的所述侧面露出,所述端子的所述第二表面的与凹向所述端子的所述第一表面的所述一部分不同的一部分从所述密封树脂的所述底面露出,及
当沿垂直于所述引线架的所述第二表面的方向观察时,所述台阶面形成在所述端子的所述第二表面的露出了的所述一部分的周缘。
5.如权利要求1所述的半导体装置,其中:
所述引线架包括安装有所述半导体芯片的芯片安装部,所述芯片安装部包括分别包括于所述引线架的所述第一表面和所述第二表面的第一表面和第二表面,及
所述芯片安装部的所述第二表面的一部分凹向所述芯片安装部的所述第一表面以形成所述台阶面。
6.如权利要求5所述的半导体装置,其中:
所述密封树脂包括底面,所述芯片安装部的所述第二表面的与凹向所述芯片安装部的第一表面的所述一部分不同的一部分从所述密封树脂的所述底面露出,及
当沿垂直于所述引线架的所述第二表面的方向观察时,所述台阶面形成在所述芯片安装部的所述第二表面的露出了的所述一部分的周围。
7.一种引线架,包括:
成为半导体装置的单个区域,所述单个区域包括第一表面和第二表面,所述第一表面上安装半导体芯片,所述第二表面背对所述第一表面,并具有凹向所述第一表面以形成台阶面的一部分,当密封树脂对所述单个区域和所述半导体芯片进行密封时,所述台阶面被所述密封树脂覆盖,
其中,所述台阶面包括形成有多个凹部的非平坦表面部。
8.如权利要求7所述的引线架,其中:
所述多个凹部的每个凹部的平面形状是圆形或多边形,所述圆形的直径为0.020mm以上且0.060mm以下,所述多边形的外接圆具有0.020mm以上且0.060mm以下的直径,及
在平面上形成所述非平坦表面部的情况下,所述非平坦表面部的表面积与所述平面的表面积之比为1.7以上。
9.如权利要求7所述的引线架,还包括:
作为外部连接端子的端子,所述端子包括在所述单个区域中,所述端子包括分别包括在所述单个区域的所述第一表面和所述第二表面中的第一表面和第二表面,及
所述端子的所述第二表面的一部分凹向所述端子的所述第一表面以形成所述台阶面。
10.如权利要求9所述的引线架,其中:
凹向所述所述端子的所述第一表面的所述一部分形成在所述端子的所述第二表面的周缘部分。
11.如权利要求7所述的引线架,还包括:
芯片安装部,其上安装所述半导体芯片,所述芯片安装部包括在所述单个区域中,并包括分别包括在所述单个区域的所述第一表面和所述第二表面中的第一表面和第二表面,
其中,所述芯片安装部的所述第二表面的一部分凹向所述芯片安装部的所述第一表面以形成所述台阶面。
12.如权利要求11所述的引线架,其中:
凹向所述芯片安装部的所述第一表面的所述一部分是所述芯片安装部的所述第二表面的周缘部分。
13.如权利要求7所述的引线架,还包括:
外框部,包围所述单个区域,
其中,所述单个区域的厚度小于所述外框部的厚度。
14.一种引线架的制造方法,所述引线架包括成为半导体装置的单个区域,所述单个区域包括第一表面和第二表面,所述第一表面上安装半导体芯片,所述第二表面背对所述第一表面,所述制造方法包括:
通过对金属板进行蚀刻以形成所述单个区域的步骤;及
通过减少所述单个区域的厚度使所述单个区域的所述第二表面的一部分凹向所述所述单个区域的第一表面以形成台阶面,并在所述台阶面上形成包括多个凹部的非平坦表面部的步骤,当密封树脂对所述单个区域和所述半导体芯片进行密封时,所述台阶面被所述密封树脂所覆盖。
15.如权利要求14所述的引线架的制造方法,其中:
所述多个凹部的每个凹部的平面形状是圆形或多边形,所述圆形的直径为0.020mm以上且0.060mm以下,所述多边形的外接圆具有0.020mm以上且0.060mm以下的直径,及
在平面上形成所述非平坦表面部的情况下,所述非平坦表面部的表面积与所述平面的表面积之比为1.7以上。
16.如权利要求14所述的引线架的制造方法,其中:
在使用单一蚀刻掩膜的单一蚀刻过程中形成所述单个区域和所述非平坦表面部。
17.如权利要求14所述的引线架的制造方法,还包括:
形成包围所述单个区域的外框部的步骤;及
减少所述单个区域的所述第一表面侧的所述单个区域的厚度,以使所述单个区域的厚度小于所述外框部的厚度的步骤。
18.如权利要求17所述的引线架的制造方法,其中:
在使用单一蚀刻掩膜的单一蚀刻过程中形成所述单个区域和所述外框部以及减少所述单个区域的厚度。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112133640A (zh) * | 2020-11-24 | 2020-12-25 | 宁波康强电子股份有限公司 | 一种具有粗糙侧壁的引线框架的制备方法 |
US11842951B2 (en) * | 2019-06-21 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device for improving heat dissipation and mounting structure thereof |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7149907B2 (ja) * | 2019-09-04 | 2022-10-07 | 三菱電機株式会社 | 半導体装置および半導体素子 |
KR102249465B1 (ko) * | 2019-10-31 | 2021-05-07 | 주식회사 코스텍시스 | 고방열 플라스틱 패키지 |
US11715678B2 (en) * | 2020-12-31 | 2023-08-01 | Texas Instruments Incorporated | Roughened conductive components |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH079961B2 (ja) * | 1988-05-25 | 1995-02-01 | 三菱電機株式会社 | 樹脂封止形半導体装置 |
CN1355668A (zh) * | 2000-10-31 | 2002-06-26 | W.C.贺利氏股份有限两合公司 | 制造金属支承框架的方法,金属支承框架及其应用 |
US7205180B1 (en) * | 2003-07-19 | 2007-04-17 | Ns Electronics Bangkok (1993) Ltd. | Process of fabricating semiconductor packages using leadframes roughened with chemical etchant |
JP2014044980A (ja) * | 2012-08-24 | 2014-03-13 | Dainippon Printing Co Ltd | 半導体装置製造用リードフレーム及び半導体装置の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7112474B1 (en) * | 1998-06-24 | 2006-09-26 | Amkor Technology, Inc. | Method of making an integrated circuit package |
JP2000208693A (ja) * | 1999-01-11 | 2000-07-28 | Dainippon Printing Co Ltd | リ―ドフレ―ム部材とその製造方法および樹脂封止型半導体装置 |
JP4857594B2 (ja) * | 2005-04-26 | 2012-01-18 | 大日本印刷株式会社 | 回路部材、及び回路部材の製造方法 |
JPWO2007061112A1 (ja) * | 2005-11-28 | 2009-05-07 | 大日本印刷株式会社 | 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置 |
US9305859B2 (en) * | 2006-05-02 | 2016-04-05 | Advanced Analogic Technologies Incorporated | Integrated circuit die with low thermal resistance |
US8174096B2 (en) * | 2006-08-25 | 2012-05-08 | Asm Assembly Materials Ltd. | Stamped leadframe and method of manufacture thereof |
TW201021119A (en) * | 2008-09-25 | 2010-06-01 | Lg Innotek Co Ltd | Structure and manufacture method for multi-row lead frame and semiconductor package |
JP2010087129A (ja) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
US20100171201A1 (en) * | 2009-01-06 | 2010-07-08 | Wyant M Todd | Chip on lead with small power pad design |
US7858443B2 (en) * | 2009-03-09 | 2010-12-28 | Utac Hong Kong Limited | Leadless integrated circuit package having standoff contacts and die attach pad |
-
2015
- 2015-11-05 JP JP2015217896A patent/JP6576796B2/ja active Active
-
2016
- 2016-10-11 US US15/290,102 patent/US9984958B2/en active Active
- 2016-10-25 TW TW105134397A patent/TWI716477B/zh active
- 2016-10-26 CN CN201610949306.0A patent/CN106876359A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH079961B2 (ja) * | 1988-05-25 | 1995-02-01 | 三菱電機株式会社 | 樹脂封止形半導体装置 |
CN1355668A (zh) * | 2000-10-31 | 2002-06-26 | W.C.贺利氏股份有限两合公司 | 制造金属支承框架的方法,金属支承框架及其应用 |
US7205180B1 (en) * | 2003-07-19 | 2007-04-17 | Ns Electronics Bangkok (1993) Ltd. | Process of fabricating semiconductor packages using leadframes roughened with chemical etchant |
JP2014044980A (ja) * | 2012-08-24 | 2014-03-13 | Dainippon Printing Co Ltd | 半導体装置製造用リードフレーム及び半導体装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11842951B2 (en) * | 2019-06-21 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device for improving heat dissipation and mounting structure thereof |
CN112133640A (zh) * | 2020-11-24 | 2020-12-25 | 宁波康强电子股份有限公司 | 一种具有粗糙侧壁的引线框架的制备方法 |
Also Published As
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US9984958B2 (en) | 2018-05-29 |
JP2017092153A (ja) | 2017-05-25 |
TW201727847A (zh) | 2017-08-01 |
US20170133300A1 (en) | 2017-05-11 |
JP6576796B2 (ja) | 2019-09-18 |
TWI716477B (zh) | 2021-01-21 |
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