JP6603169B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP6603169B2 JP6603169B2 JP2016086431A JP2016086431A JP6603169B2 JP 6603169 B2 JP6603169 B2 JP 6603169B2 JP 2016086431 A JP2016086431 A JP 2016086431A JP 2016086431 A JP2016086431 A JP 2016086431A JP 6603169 B2 JP6603169 B2 JP 6603169B2
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Description
本発明の一実施の形態の半導体装置を図面を参照して説明する。
図1は、本発明の一実施の形態である半導体装置PKGの上面図であり、図2は、半導体装置PKGの下面図(裏面図)であり、図3〜図5は、半導体装置PKGの平面透視図であり、図6〜図8は、半導体装置PKGの断面図であり、図9は、半導体装置PKGの側面図であり、図10は、図9の一部を拡大した部分拡大側面図である。また、図11も、半導体装置PKGの平面透視図である。
次に、本実施の形態の半導体装置PKGの製造工程について、図12〜図33を参照して説明する。図12は、本実施の形態の半導体装置PKGの製造工程を示すプロセスフロー図である。図13〜図33は、本実施の形態の半導体装置PKGの製造工程を示す平面図または断面図である。図13〜図33のうち、図13、図17、図20、図23、図28および図31は、平面図(上面図)であり、図14〜図16、図18、図19、図21、図22、図24〜図27、図29、図30、図32および図33は、断面図である。また、図14、図18、図21、図24、図26、図29および図32は、図13のD−D線に相当する位置での断面図(上記図6に対応する断面図)に対応し、図15、図19、図22、図25、図27、図30および図33は、図13のE−E線に相当する位置での断面図(上記図7に対応する断面図)に対応し、図16は、図13のF−F線に相当する位置での断面図に対応している。
図34は、本発明者が検討した検討例の半導体装置PKG101の下面図であり、図35は、検討例の半導体装置PKG101の平面透視図であり、図36および図37は、検討例の半導体装置PKG101の断面図であり、図38は、検討例の半導体装置PKG101の側面図であり、それぞれ、上記図2、図3、図6、図7および図9に相当するものである。なお、図35のA1−A1線の位置での半導体装置PKG101の断面が、図36に対応し、図35のB1−B1線の位置での半導体装置PKG101の断面が、図37に対応している。
本実施の形態の主要な特徴のうちの一つは、リードLD1とその隣のリードLD2とにおいて、封止部MRの下面MRbを基準として、リードLD1の端面TM1の下辺KH1の高さ位置が、リードLD2の端面TM2の上辺JH2の高さ位置よりも高いことである。これを別の表現で言うと、側面視において、封止部MRの厚さ方向におけるリードLD1の端面TM1の下辺KH1と封止部MRの上面MRaとの間の距離(L2)は、封止部MRの厚さ方向におけるリードLD2の端面TM2の上辺JH2と封止部MRの上面MRaとの間の距離(L3)よりも小さい(L2<L3)。これにより、リードLD1,LD2の切断面であるリードLD1,LD2の端面TM1,TM2に金属バリ(リードの金属バリ)が生じても、互いに隣り合う2つのリードLD1,LD2間が金属バリを介して短絡してしまうのを的確に防止することができる。その理由について、以下に説明する。
次に、本実施の形態の半導体装置PKGの第1変形例について説明する。なお、以下では、第1変形例の半導体装置PKGを、符号PKG1を付して半導体装置PKG1と称することとする。また、上記図1〜図11の半導体装置PKGを、以下では、上記半導体装置PKGと称することとする。
次に、本実施の形態の半導体装置PKGの第2変形例について説明する。なお、以下では、第2変形例の半導体装置PKGを、符号PKG2を付して半導体装置PKG2と称することとする。また、上記図1〜図11の半導体装置PKGを、以下では、上記半導体装置PKGと称することとする。
次に、本実施の形態の半導体装置PKGの第3変形例について説明する。なお、以下では、第3変形例の半導体装置PKGを、符号PKG3を付して半導体装置PKG3と称することとする。また、上記図1〜図11の半導体装置PKGを、以下では、上記半導体装置PKGと称することとする。
次に、本実施の形態の半導体装置PKGの第4変形例について説明する。なお、以下では、第4変形例の半導体装置PKGを、符号PKG4を付して半導体装置PKG4と称することとする。また、上記図1〜図11の半導体装置PKGを、以下では、上記半導体装置PKGと称することとする。
次に、本実施の形態の半導体装置PKGの第5変形例について説明する。なお、以下では、第5変形例の半導体装置PKGを、符号PKG5を付して半導体装置PKG5と称することとする。また、上記図1〜図11の半導体装置PKGを、以下では、上記半導体装置PKGと称することとする。
BW ワイヤ
CP 半導体チップ
DB ダムバー
DP ダイパッド
JH1,JH2,JH102 上辺
KH1,KH2,KH101 下辺
LD1,LD2,LD101,LD102 リード
LD1a,LD2a,LD101a 厚肉部
LD1b,LD2b 薄肉部
LF リードフレーム
MB 金属バリ
MR,MR1,MR101 封止部
MRa,MR1a 上面
MRb,MR1b 下面
MRc1,MRc2,MRc3,MRc4 側面
PD パッド電極
PKG,PKG1〜PKG5、PKG101 半導体装置
PL めっき層
H1,H2 寸法
TL 吊りリード
TM,TM1,TM2,TM101,TM102 端面
T1a,T1b,T2a,T2b,T3,T4a,T4b,T4c,T4d 厚さ
W1a,W1b,W2a,W2b 幅
Claims (18)
- (a)チップ搭載部と複数のリードとを有するリードフレームを準備する工程、
(b)複数のパッド電極を有する半導体チップを、前記チップ搭載部上に搭載する工程、
(c)前記(b)工程後、前記半導体チップの前記複数のパッド電極と前記複数のリードとを、複数のワイヤを介してそれぞれ電気的に接続する工程、
(d)前記(c)工程後、前記半導体チップ、前記複数のワイヤ、前記チップ搭載部および前記複数のリードを封止する樹脂封止部を形成する工程、
(e)前記(d)工程後、前記樹脂封止部および前記複数のリードを、回転刃を用いて切断する工程、
を有し、
前記(d)工程で形成された前記樹脂封止部は、互いに反対側に位置する第1上面および第1下面を有し、
前記(d)工程では、前記複数のリードのそれぞれの少なくとも一部は、前記樹脂封止部の前記第1下面から露出され、
前記(e)工程により、前記回転刃による前記複数のリードのそれぞれの切断面は、前記回転刃による前記樹脂封止部の切断面から露出され、
前記複数のリードは、第1リードと前記第1リードの隣に位置する第2リードとを有し、
前記回転刃による前記第1リードの切断面である第1端面は、前記第1上面に近い側の第1上辺と、前記第1上面から遠い側の第1下辺とを有し、
前記回転刃による前記第2リードの切断面である第2端面は、前記第1上面に近い側の第2上辺と、前記第1上面から遠い側の第2下辺とを有し、
前記樹脂封止部の厚さ方向における前記第1下辺と前記第1上面との間の距離は、前記樹脂封止部の前記厚さ方向における前記第2上辺と前記第1上面との間の距離よりも小さく、
前記第1下面に平行な方向における前記第1端面の寸法は、前記第1下面に平行な方向における前記第2端面の寸法よりも小さい、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程では、超音波を印加しながら、前記複数のワイヤを前記複数のリードにそれぞれ接続する、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記複数のワイヤのそれぞれは、銅ワイヤである、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記樹脂封止部の厚さ方向における前記第1端面の寸法は、前記樹脂封止部の厚さ方向における前記第2端面の寸法よりも大きい、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程では、前記リードフレームは、エッチング加工により作製される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記複数のリードは、前記チップ搭載部を囲むように配置され、
前記複数のリードは、複数の前記第1リードと複数の前記第2リードとを有し、
前記第1リードと前記第2リードとが交互に配置されている、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1リードは、前記第1リードの延在方向に隣り合う第1厚肉部と前記第1厚肉部よりも薄い第1薄肉部とを一体的に有し、
前記第1厚肉部および前記第1薄肉部のうち、前記第1厚肉部が前記チップ搭載部に近い側に位置し、
前記(d)工程では、前記第1厚肉部の第2下面は、前記樹脂封止部の前記第1下面から露出され、前記第1薄肉部の第3下面は前記樹脂封止部で覆われ、
前記第1端面は、前記回転刃による前記第1薄肉部の切断面であり、
前記第2リードは、前記第2リードの延在方向に隣り合う第2厚肉部と前記第2厚肉部よりも薄い第2薄肉部とを一体的に有し、
前記第2厚肉部および前記第2薄肉部のうち、前記第2厚肉部が前記チップ搭載部に近い側に位置し、
前記第2端面は、前記回転刃による前記第2薄肉部の切断面である、半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記第1薄肉部の幅は、前記第1厚肉部の幅よりも小さい、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記第2薄肉部の幅は、前記第2厚肉部の幅よりも小さい、半導体装置の製造方法。 - (a)第1デバイス形成領域と、ダムバーを介して前記第1デバイス形成領域の隣に位置する第2デバイス形成領域と、を有するリードフレームを準備する工程、
ここで、
前記第1デバイス形成領域および前記第2デバイス形成領域のそれぞれは、
チップ搭載部と、
前記チップ搭載部を支持する複数の吊りリードと、
複数のリードと、
を有し、
(b)前記第1デバイス形成領域の前記チップ搭載部上に第1半導体チップを搭載し、前記第2デバイス形成領域の前記チップ搭載部上に第2半導体チップを搭載する工程、
ここで、前記第1半導体チップおよび前記第2半導体チップのそれぞれは、複数のパッド電極を有し、
(c)前記(b)工程後、前記第1半導体チップの前記複数のパッド電極と前記第1デバイス形成領域の前記複数のリードとを、複数の第1ワイヤを介してそれぞれ電気的に接続し、前記第2半導体チップの前記複数のパッド電極と前記第2デバイス形成領域の前記複数のリードとを、複数の第2ワイヤを介してそれぞれ電気的に接続する工程、
(d)前記(c)工程後、前記リードフレームの前記第1デバイス形成領域および前記第2デバイス形成領域を覆うように、樹脂封止部を形成する工程、
ここで、
前記樹脂封止部により、前記第1デバイス形成領域の前記第1半導体チップ、前記複数の第1ワイヤ、前記チップ搭載部および前記複数のリードと、前記第2デバイス形成領域の前記第2半導体チップ、前記複数の第2ワイヤ、前記チップ搭載部および前記複数のリードとが封止され、
前記樹脂封止部は、互いに反対側に位置する第1上面および第1下面を有し、
前記第1および第2デバイス形成領域の前記複数のリードのそれぞれの少なくとも一部は、前記樹脂封止部の前記第1下面から露出され、
(e)前記(d)工程後、前記第1デバイス形成領域と前記第2デバイス形成領域との間において、前記樹脂封止部、前記複数のリード、前記複数の吊りリードおよび前記ダムバーを、回転刃を用いて切断する工程、
を有し、
前記(e)工程により、前記回転刃による前記複数のリードの切断面は、前記回転刃による前記樹脂封止部の切断面から露出され、
前記複数のリードは、第1リードと前記第1リードの隣に位置する第2リードとを有し、
前記回転刃による前記第1リードの切断面である第1端面は、前記第1上面に近い側の第1上辺と、前記第1上面から遠い側の第1下辺とを有し、
前記回転刃による前記第2リードの切断面である第2端面は、前記第1上面に近い側の第2上辺と、前記第1上面から遠い側の第2下辺とを有し、
前記樹脂封止部の厚さ方向における前記第1下辺と前記第1上面との間の距離は、前記樹脂封止部の前記厚さ方向における前記第2上辺と前記第1上面との間の距離よりも小さく、
前記第1下面に平行な方向における前記第1端面の寸法は、前記第1下面に平行な方向における前記第2端面の寸法よりも小さい、半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第1リードは、前記第1リードの延在方向に隣り合う第1厚肉部と前記第1厚肉部よりも薄い第1薄肉部とを一体的に有し、
前記第1厚肉部および前記第1薄肉部のうち、前記第1厚肉部が前記チップ搭載部に近い側に位置し、前記第1薄肉部が前記ダムバーに接続され、
前記第2リードは、前記第2リードの延在方向に隣り合う第2厚肉部と前記第2厚肉部よりも薄い第2薄肉部とを一体的に有し、
前記第2厚肉部および前記第2薄肉部のうち、前記第2厚肉部が前記チップ搭載部に近い側に位置し、前記第2薄肉部が前記ダムバーに接続され、
前記第1端面は、前記回転刃による前記第1薄肉部の切断面であり、
前記第2端面は、前記回転刃による前記第2薄肉部の切断面であり、
前記ダムバーのうちの前記第1リードの前記第1薄肉部と接続する第1部分は、前記第1リードの前記第1薄肉部と同じ厚さを有し、
前記ダムバーのうちの前記第2リードの第2薄肉部と接続する第2部分は、前記第2リードの前記第2薄肉部と同じ厚さを有する、半導体装置の製造方法。 - チップ搭載部と、
前記チップ搭載部上に搭載され、複数のパッド電極を有する半導体チップと、
複数のリードと、
前記半導体チップの前記複数のパッド電極と前記複数のリードとをそれぞれ電気的に接続する複数のワイヤと、
前記チップ搭載部、前記半導体チップ、前記複数のワイヤおよび前記複数のリードを封止する樹脂封止部と、
を有する半導体装置であって、
前記樹脂封止部は、互いに反対側に位置する第1上面、第1下面、および前記第1上面と前記第1下面との間に位置する複数の側面を有し、
前記複数のリードのそれぞれの少なくとも一部は、前記樹脂封止部の第1下面から露出され、
前記複数のリードは、第1リードと前記第1リードの隣に位置する第2リードとを有し、
前記第1リードの第1端面と前記第2リードの第2端面とは、前記樹脂封止部の前記複数の側面のうちの第1側面から露出され、
前記第1リードの前記第1端面は、前記第1上面に近い側の第1上辺と、前記第1上面から遠い側の第1下辺とを有し、
前記第2リードの前記第2端面は、前記第1上面に近い側の第2上辺と、前記第1上面から遠い側の第2下辺とを有し、
前記第1リードの前記第1端面および前記第2リードの前記第2端面では、前記第1下面および前記第1側面のそれぞれに平行な方向に金属バリが生じており、
前記樹脂封止部の厚さ方向における前記第1下辺と前記第1上面との間の距離は、前記樹脂封止部の前記厚さ方向における前記第2上辺と前記第1上面との間の距離よりも小さく、
前記第1下面に平行な方向における前記第1端面の寸法は、前記第1下面に平行な方向における前記第2端面の寸法よりも小さい、半導体装置。 - 請求項12記載の半導体装置において、
前記樹脂封止部の厚さ方向における前記第1端面の寸法は、前記樹脂封止部の厚さ方向における前記第2端面の寸法よりも大きい、半導体装置。 - 請求項12記載の半導体装置において、
前記複数のリードは、前記チップ搭載部を囲むように配置され、
前記複数のリードは、複数の前記第1リードと複数の前記第2リードとを有し、
前記第1リードと前記第2リードとが交互に配置されている、半導体装置。 - 請求項12記載の半導体装置において、
前記第1リードは、前記第1リードの延在方向に隣り合う第1厚肉部と前記第1厚肉部よりも薄い第1薄肉部とを一体的に有し、
前記第1厚肉部および前記第1薄肉部のうち、前記第1厚肉部が前記チップ搭載部に近い側に位置し、
前記第1厚肉部の第2下面は、前記樹脂封止部の第1下面から露出され、前記第1薄肉部の第3下面は前記樹脂封止部で覆われ、
前記第1端面は、前記第1薄肉部により形成され、
前記第2リードは、前記第2リードの延在方向に隣り合う第2厚肉部と前記第2厚肉部よりも薄い第2薄肉部とを一体的に有し、
前記第2厚肉部および前記第2薄肉部のうち、前記第2厚肉部が前記チップ搭載部に近い側に位置し、
前記第2端面は、前記第2薄肉部により形成されている、半導体装置。 - 請求項15記載の半導体装置において、
前記第2厚肉部の第4下面および前記第2薄肉部の第5下面は、前記樹脂封止部の前記第1下面から露出されている、半導体装置。 - 請求項15記載の半導体装置において、
前記第1薄肉部の幅は、前記第1厚肉部の幅よりも小さい、半導体装置。 - 請求項17記載の半導体装置において、
前記第2薄肉部の幅は、前記第2厚肉部の幅よりも小さい、半導体装置。
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