TWI489610B - 具電磁遮蔽之封裝結構之製法 - Google Patents

具電磁遮蔽之封裝結構之製法 Download PDF

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TWI489610B
TWI489610B TW099101178A TW99101178A TWI489610B TW I489610 B TWI489610 B TW I489610B TW 099101178 A TW099101178 A TW 099101178A TW 99101178 A TW99101178 A TW 99101178A TW I489610 B TWI489610 B TW I489610B
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encapsulant
substrate
package structure
metal
masking film
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TW201126687A (en
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姚進財
黃建屏
柯俊吉
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矽品精密工業股份有限公司
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Priority to US12/769,053 priority patent/US8963298B2/en
Publication of TW201126687A publication Critical patent/TW201126687A/zh
Priority to US14/622,255 priority patent/US9425152B2/en
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Description

具電磁遮蔽之封裝結構之製法
本發明係有關於一種封裝結構及其製法，尤指一種具電磁遮蔽之封裝結構及其製法。
半導體封裝件(Semiconductor Package)係為一種將半導體晶片(chip)電性連接在一導線架或基板之承載件上，再以係如環氧樹脂之封裝膠體包覆在該半導體晶片及承載件上，以藉由該封裝膠體保護該半導體晶片及承載件，而能避免外界之水氣或污染物之侵害。
而習知之半導體封裝件於運作時，多少會受外界之電磁(EMI)等雜訊干擾，導致該半導體封裝件之電性運作功能不正常，因此影響整體之電性功能。
有鑑於習知半導體封裝件易受電磁干擾之問題，而有如美國專利第5,166,772號揭露於封裝膠體中嵌埋金屬罩之結構。
請參閱第1圖，其為美國專利第5,166,772號之封裝結構立體剖視示意圖；如圖所示，係於基板(substrate)10上接置晶片11，且該晶片11以複數銲線12電性連接至該基板10，並於該晶片11外罩設一網狀之金屬罩(metal shield)13，且該基板10上具有至少一接地端14，令該金屬罩13電性連接至該接地端14，此外，於該金屬罩13、晶片11、銲線12、及部份基板10上形成封裝膠體15，以將該金屬罩13嵌埋於該封裝膠體15中，並且藉由該網狀之金屬罩13遮蔽外界電磁干擾該晶片11之運作，俾能避免電性運作功能不正常，而影響整體之電性功能。其他類似具電磁遮蔽設計之封裝結構包括美國專利第4,218,578、4,838,475、4,953,002及5,030,935號所揭露者。
惟，上述之習知構造，必須先另行製作網狀之金屬罩13，因而增加製程之複雜度；之後，再將該金屬罩13罩設於該晶片11上，並且將該金屬罩13固定於該基板10上，如此則增加組裝之困難度。此外，該網狀之金屬罩13罩設於該基板10上後，於該金屬罩13、晶片11、銲線12及部份基板10上形成封裝膠體15時，該封裝膠體15必須通過網狀的金屬罩13方能覆蓋於該晶片11上，由於該金屬罩13係為網狀，當該封裝膠體15通過該金屬罩13之細密的網目時容易產生紊流，導致氣泡產生，因此易於該封裝膠體15中產生氣泡，而於後續熱製程中產生爆米花效應。
另請參閱第2圖，其為美國專利第5,557,142號之封裝結構立體剖視示意圖，係於基板20上接置晶片21，且該晶片21以複數銲線22電性連接至該基板20，又於該晶片21、銲線22及部份基板20上形成封裝膠體23，以藉由該封裝膠體23保護該晶片21、銲線22及基板20，且於該封裝膠體23之外露表面以塗佈或濺鍍形成金屬層24，俾以藉由該金屬層24遮蔽外界電磁干擾。其他類似具電磁遮蔽設計之封裝結構包括美國專利第5,220,489、5,311,059及7,342,303號所揭露者。
惟，上述之習知構造，雖能免除複雜之製程，但必須在該基板20上完成接置晶片21及封裝膠體23，且進行切單(singular)成為單一封裝結構後，方能於該封裝膠體23之外露表面塗佈或濺鍍形成金屬層24，而該單一封裝結構於製程中不易排放取件，因而不利於大量生產。再者，濺鍍之方式亦無法應用於封裝膠體與基板側邊齊平之封裝結構。
另外，如美國專利第7,030,469號所揭露之一種封裝結構，其係於封裝膠體上形成外露出銲線之溝槽，且該溝槽及封裝膠體上形成有與該銲線連接之導線層，以達成電磁遮蔽之效果，惟，該導線層須為非鐵金屬材料，而僅能以沉積或濺鍍方式覆蓋於溝槽及封裝膠體上，無法應用於封裝膠體與基板側邊齊平之封裝結構。再者，該導線層與該銲線為點接觸，易有接觸不良的問題。
因此，鑒於上述之問題，如何避免習知具電磁遮蔽之封裝結構及其製法之製作複雜度、組裝困難、易於熱製程中產生爆米花效應及不利於大量生產，實已成為目前亟欲解決之課題。
鑑於上述習知技術之種種缺失，本發明提供一種具電磁遮蔽之封裝結構，係包括：基板單元，係具有相對之第一表面及第二表面，且該第一表面具有置晶區；金屬柱，係設於該第一表面上；晶片，係接置並電性連接於該置晶區上；封裝膠體，係包覆該晶片及第一表面，並外露出該部分金屬柱；以及遮蔽膜，係包覆該封裝膠體並電性連接該金屬柱。
為得到前述之封裝結構，本發明復揭露一種具電磁遮蔽之封裝結構之製法，係包括：準備一基板，該基板上定義有複數縱橫分佈之切割線以圍設出複數基板單元，且各該基板單元具相對之第一表面及第二表面，於各該第一表面具有置晶區；於各該基板單元邊緣之至少一切割線上形成金屬柱；於各該基板單元之置晶區上接置並電性連接晶片；於該基板、晶片及金屬柱上形成封裝膠體，以包覆該些晶片及金屬柱；沿著各該切割線第一次裁切該封裝膠體及金屬柱，以於該封裝膠體中形成複數露出各該金屬柱之溝槽；於該封裝膠體表面及溝槽中形成遮蔽膜，以令該遮蔽膜電性連接該些金屬柱；以及沿著各該切割線進行第二次裁切，以切割該溝槽中之遮蔽膜及基板，俾令該遮蔽膜包覆該封裝膠體側面，並與該基板側邊齊平。
依上述之具電磁遮蔽之封裝結構之製法，該金屬柱可設於該橫向分佈之切割線或縱向分佈之切割線上，或者，該金屬柱可設於該橫向分佈切割線及縱向分佈切割線之交點上，甚至部分金屬柱係設於單一切割線上，部分金屬柱係設於切割線之交點上。
在本發明之一實施態樣中，形成該金屬柱之材料係為銅、錫或金。該晶片具有相對應之作用面與非作用面，且於該作用面上具有複數信號銲墊、電源銲墊及接地銲墊，而該些信號銲墊、電源銲墊及接地銲墊係以打線電性連接或覆晶電性連接該基板單元。
又於本發明之製法中，該第一次裁切之深度係大於、等於、或小於該封裝膠體之厚度，且該第二次裁切之寬度係小於該溝槽之寬度，以令該遮蔽膜形成於該封裝膠體之側表面。
在實施上，形成該遮蔽膜可為碳質(carbon-based)材料或含金屬粉體材料，而該遮蔽膜亦可藉由網版印刷形成於該封裝膠體之外露表面及該些溝槽中，然後固化該遮蔽膜。或者，先於該些溝槽中滴入液態之碳質材料或含金屬粉體材料，以形成第一遮蔽膜，再於該封裝膠體之外露表面及該些溝槽中之第一遮蔽膜上形成第二遮蔽膜，之後固化該第一遮蔽膜及第二遮蔽膜。
另外，所述之該基板單元之第二表面復可包括形成複數銲球。
由上可知，本發明具電磁遮蔽之封裝結構及其製法，係於該基板之各個基板單元上形成金屬柱及於該置晶區中接置晶片，接著於該基板、晶片及金屬柱上形成封裝膠體，然後第一次裁切該封裝膠體，以於該封裝膠體中形成複數縱橫分割之溝槽，並分割各該金屬柱以露出其側表面，但未切割分離該些基板單元，再於該封裝膠體之外露表面及該些溝槽中形成遮蔽膜，之後再沿著各該溝槽進行第二次裁切，以切割該溝槽中之遮蔽膜及基板，以令該遮蔽膜形成於該封裝膠體之側面，本發明之方法可於切單前巧妙地透過溝槽的形成，而於其中填入電磁遮蔽材料，俾與金屬柱作面接觸，免除如美國專利第7,030,469號所揭露之點接觸可能產生的接地不良問題，更能免除習知結構及其製法之製作複雜度、組裝困難、易於熱製程中產生爆米花效應及不利於大量生產等缺失。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
請參閱第3A至3F-3圖，係為本發明所揭露之具電磁遮蔽之封裝結構之製法。
如第3A及3A’圖所示，該第3A圖係為第3A’圖之上視圖；如圖所示，首先，準備一基板30，該基板30上定義有複數縱橫分佈之切割線301以圍設出複數基板單元31，如圖所示，該切割線301包括複數橫向分佈切割線301a及縱向分佈切割線301b，且各該基板單元31具相對之第一表面31a及第二表面31b，於各該第一表面31a具有置晶區311。
依上所述，復於各該基板單元31邊緣之至少一切割線301上形成係為銅、錫或金之金屬柱32，以連接該基板單元31上之接地端或接地層(未圖示)，而該金屬柱32係可設於該橫向分佈切割線301a、縱向分佈切割線301b上，或者，該金屬柱32可設於該橫向分佈切割線301a及縱向分佈切割線301b之交點上，甚至如第3A”圖所示，部分金屬柱32係設於單一切割線上，部分金屬柱32係設於切割線之交點上。
如第3B圖所示，於各該基板單元31之置晶區311上接置並電性連接晶片33，該晶片33具有相對應之作用面與非作用面，於該作用面上具有複數信號銲墊、電源銲墊及接地銲墊，該些信號銲墊、電源銲墊及接地銲墊係以打線(wire bonding)或覆晶(flip chip)方式電性連接該基板單元31；於本實施例中，係以打線電性連接作說明，但不以此為限。
接著，復於該基板30、晶片33及金屬柱32上形成封裝膠體34，以包覆該些晶片33及金屬柱32。
如第3C圖所示，沿著各該切割線301第一次裁切該封裝膠體34及金屬柱32，以於該封裝膠體34中形成複數露出各該金屬柱32之溝槽340，且該第一次裁切之深度d係可大於、等於、或小於該封裝膠體34之厚度t。
如第3D圖所示，於該封裝膠體34表面及溝槽340中以網版印刷形成材質為碳質材料或含金屬粉體材料之遮蔽膜35，且令該遮蔽膜35電性連接該些金屬柱32之側表面320，並於網版印刷後進行固化，如此即能藉由該遮蔽膜35之遮蔽，防止該晶片33受電磁干擾，俾以提供正常之運作。
另請參閱第3D-1及3D-2圖，其係為形成該遮蔽膜35之另一實施例，與前述實施例之不同處在於先在該些溝槽340中先滴入液態之碳質材料或含金屬粉體材料，以形成第一遮蔽膜351，如第3D-1圖所示；接著，於該封裝膠體34之外露表面及該些溝槽340中之第一遮蔽膜351上形成第二遮蔽膜352，如第3D-2圖所示；最後固化該第一遮蔽膜351及第二遮蔽膜352。
如第3E圖所示，沿著各該溝槽340之切割線301進行第二次裁切，以切割該溝槽340中之遮蔽膜35及基板30，且該第二次裁切之寬度w2小於該第一次裁切或溝槽340之寬度w1，俾令該遮蔽膜35包覆該封裝膠體34側面341，並與該基板30側邊齊平。
如第3F圖所示，復包括該基板單元31之第二表面31b形成複數銲球36，以供電性連接至其它電子裝置。
依上述之製法，本發明復提供一種具電磁遮蔽之封裝結構3，係包括：基板單元31、金屬柱32、晶片33、封裝膠體34及遮蔽膜35。
所述之基板單元31，係具有相對之第一表面31a及第二表面31b，於該第一表面31a具有置晶區311。
所述之金屬柱32，係設於該第一表面31a上，且形成該金屬柱32之材料係可為銅、錫或金。
所述之晶片33具有相對應之作用面與非作用面，且於該作用面上具有複數信號銲墊、電源銲墊及接地銲墊，該些信號銲墊、電源銲墊及接地銲墊係以打線或覆晶方式電性連接該基板單元31。
所述之封裝膠體34，係包覆該晶片33及基板單元31之第一表面31a，並外露出該部分金屬柱32。
所述之遮蔽膜35係可為碳質材料或含金屬粉體材料，係包覆該封裝膠體34並電性連接該金屬柱32。如圖所示，在本實施例中，第一次裁切該封裝膠體34及金屬柱32時，該第一次裁切之深度d係等於該封裝膠體34之厚度t，因此，該遮蔽膜35包覆該金屬柱32，且該遮蔽膜35係與該基板30側邊齊平。
又依上述之具電磁遮蔽之封裝結構，復可包括複數銲球36，係設於該基板單元31之第二表面31b，以供電性連接至其它電子裝置。
請參閱第3F-1圖，其係具電磁遮蔽之封裝結構3’的另一實施例，與前述實施例之不同處在於第3C圖所示中沿著各該切割線301第一次裁切該封裝膠體34及金屬柱32時，該第一次裁切之深度d係大於該封裝膠體34之厚度t。因此，該遮蔽膜35包覆該金屬柱32及部分基板30，且該遮蔽膜35係與該基板30側邊齊平。
請參閱第3F-2圖，其係具電磁遮蔽之封裝結構3”的又一實施例，與前述實施例之不同處在於第3C圖所示中沿著各該切割線301第一次裁切該封裝膠體34及金屬柱32時，該第一次裁切之深度d係小於該封裝膠體34之厚度t。因此，該遮蔽膜35僅包覆該部分金屬柱32，故該遮蔽膜35與該金屬柱32及基板30側邊齊平。
請參閱第3F-3圖，其係具電磁遮蔽之封裝結構的再一實施例，與前述實施例之不同處在於該封裝結構之基板單元31為一導線架，而該導線架具有晶片座312和複數個接腳313，本實施例之封裝結構3’’’復包括該金屬柱32，係設於各該接腳313上，晶片33，係接置於晶片座312上，並以銲線37電性連接該接腳313，封裝膠體34，係包覆該晶片33及導線架，並外露出該部分金屬柱32；以及遮蔽膜35，係包覆該封裝膠體34並電性連接該金屬柱32。
本發明具電磁遮蔽之封裝結構及其製法，係於該基板之切割線位置上形成金屬柱，並於該基板單元第一表面之置晶區中接置晶片，接著於該基板、晶片及金屬柱上形成封裝膠體，以包覆該些晶片及金屬柱，然後沿著各該切割線第一次裁切該封裝膠體，但未穿透該基板，以於該封裝膠體中形成複數縱橫分割之溝槽，並分割各該金屬柱以露出其側表面，再於該封裝膠體之外露表面及該些溝槽中形成遮蔽膜，之後再沿著各該溝槽之切割線進行第二次裁切，以切割該遮蔽膜及基板，且令該遮蔽膜形成於該封裝膠體之側面，並分割成複數封裝單元；由於先分割該封裝膠體以形成溝槽，但未切割分離該些基板單元，再於已分割之封裝膠體表面及溝槽中形成遮蔽膜，之後再完全分割該封裝膠體及該些基板單元，本發明之方法可於切單前巧妙地透過溝槽的形成，而於其中填入電磁遮蔽材料，俾與金屬柱作面接觸提升接地品質，更能免除習知結構及其製法之製作複雜度、組裝困難、易於熱製程中產生爆米花效應、及不利於大量生產等缺失。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．基板
11．．．晶片
12、37．．．銲線
13．．．金屬罩
14．．．接地端
15．．．封裝膠體
20．．．基板
21．．．晶片
22、37．．．銲線
23．．．封裝膠體
24．．．金屬層
3、3’、3”、3’’’．．．封裝結構
30．．．基板
301．．．切割線
301a．．．橫向分佈切割線
301b．．．縱向分佈切割線
31．．．基板單元
31a．．．第一表面
31b．．．第二表面
311．．．置晶區
32．．．金屬柱
320．．．側表面
33．．．晶片
34．．．封裝膠體
340．．．溝槽
341．．．側面
35．．．遮蔽膜
351．．．第一遮蔽膜
352．．．第二遮蔽膜
36．．．銲球
d．．．深度
t．．．厚度
312．．．晶片座
313．．．接腳
第1圖係為美國專利第5,166,772號之封裝結構立體剖視示意圖；
第2圖係為美國專利第5,557,142號之封裝結構立體剖視示意圖；以及
第3A至3F-3圖係為本發明具電磁遮蔽之封裝結構之製法的剖視示意圖；其中，第3A’圖係第3A圖之剖視圖，
第3A”圖為第3A圖之另一實施例，該第3D-1及3D-2圖係為第3D圖之另一實施例，第3F-1至3F-3圖係本發明具電磁遮蔽之封裝結構的其他實施態樣。
3．．．封裝結構
301．．．切割線
31．．．基板單元
32．．．金屬柱
320．．．側表面
33．．．晶片
34．．．封裝膠體
340．．．溝槽
341．．．側面
35．．．遮蔽膜

Claims (14)

  1. 一種具電磁遮蔽之封裝結構之製法，係包括：準備一基板，該基板上定義有複數縱橫分佈之切割線以圍設出複數基板單元，且各該基板單元具相對之第一表面及第二表面，於各該第一表面具有置晶區；於各該基板單元邊緣之至少一切割線上形成金屬柱；於各該基板單元之置晶區上接置並電性連接晶片；於該基板、晶片及金屬柱上形成封裝膠體，以包覆該些晶片及金屬柱；沿著各該切割線第一次裁切該封裝膠體及金屬柱，以於該封裝膠體中形成複數露出各該金屬柱之溝槽；於該些溝槽中滴入液態之碳質材料或含金屬粉體材料，以形成第一遮蔽膜；於該封裝膠體之外露表面及該些溝槽中之第一遮蔽膜上以網版印刷形成第二遮蔽膜；固化該第一遮蔽膜及第二遮蔽膜，以於該封裝膠體表面及溝槽中形成遮蔽膜，以令該遮蔽膜電性連接該些金屬柱；以及沿著各該切割線進行第二次裁切，以切割該溝槽中之遮蔽膜及該基板，俾令該遮蔽膜包覆該封裝膠體側面、該金屬柱側面與該基板單元之各側面之部分表面，該遮蔽膜之側面外表面並與該基板單元側邊齊平。
  2. 如申請專利範圍第1項所述之具電磁遮蔽之封裝結構之製法，其中，該金屬柱係設於該橫向分佈之切割線或縱向分佈之切割線上。
  3. 如申請專利範圍第1項所述之具電磁遮蔽之封裝結構之製法，其中，該金屬柱係設於該橫向分佈切割線及縱向分佈切割線之交點上。
  4. 如申請專利範圍第1項所述之具電磁遮蔽之封裝結構之製法，其中，形成該金屬柱之材料係為銅、錫或金。
  5. 如申請專利範圍第1項所述之具電磁遮蔽之封裝結構之製法，其中，該晶片係以打線或覆晶方式電性連接該基板單元。
  6. 如申請專利範圍第1項所述之具電磁遮蔽之封裝結構之製法，其中，該第一次裁切之深度係大於該封裝膠體之厚度。
  7. 如申請專利範圍第1項所述之具電磁遮蔽之封裝結構之製法，其中，該第二次裁切之寬度小於該溝槽之寬度。
  8. 一種具電磁遮蔽之封裝結構之製法，係包括：準備一基板，該基板上定義有複數縱橫分佈之切割線以圍設出複數基板單元，且各該基板單元具相對之第一表面及第二表面，於各該第一表面具有置晶區；於各該基板單元邊緣之至少一切割線上形成金屬柱；於各該基板單元之置晶區上接置並電性連接晶片；於該基板、晶片及金屬柱上形成封裝膠體，以包覆 該些晶片及金屬柱；沿著各該切割線第一次裁切該封裝膠體及金屬柱，以於該封裝膠體中形成複數露出各該金屬柱之溝槽；於該些溝槽中滴入液態之碳質材料或含金屬粉體材料，以形成第一遮蔽膜；於該封裝膠體之外露表面及該些溝槽中之第一遮蔽膜上以網版印刷形成第二遮蔽膜；固化該第一遮蔽膜及第二遮蔽膜，以於該封裝膠體表面及溝槽中形成遮蔽膜，以令該遮蔽膜電性連接該些金屬柱；以及沿著各該切割線進行第二次裁切，以切割該溝槽中之遮蔽膜及該基板，俾令該遮蔽膜包覆該封裝膠體側面與該金屬柱部分側面，該遮蔽膜之側面外表面並與該基板單元側邊齊平。
  9. 如申請專利範圍第8項所述之具電磁遮蔽之封裝結構之製法，其中，該金屬柱係設於該橫向分佈之切割線或縱向分佈之切割線上。
  10. 如申請專利範圍第8項所述之具電磁遮蔽之封裝結構之製法，其中，該金屬柱係設於該橫向分佈切割線及縱向分佈切割線之交點上。
  11. 如申請專利範圍第8項所述之具電磁遮蔽之封裝結構之製法，其中，形成該金屬柱之材料係為銅、錫或金。
  12. 如申請專利範圍第8項所述之具電磁遮蔽之封裝結構 之製法，其中，該晶片係以打線或覆晶方式電性連接該基板單元。
  13. 如申請專利範圍第8項所述之具電磁遮蔽之封裝結構之製法，其中，該第一次裁切之深度係小於該封裝膠體之厚度。
  14. 如申請專利範圍第8項所述之具電磁遮蔽之封裝結構之製法，其中，該第二次裁切之寬度小於該溝槽之寬度。
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