TW201301452A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TW201301452A
TW201301452A TW100121958A TW100121958A TW201301452A TW 201301452 A TW201301452 A TW 201301452A TW 100121958 A TW100121958 A TW 100121958A TW 100121958 A TW100121958 A TW 100121958A TW 201301452 A TW201301452 A TW 201301452A
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layer
dielectric layer
extension
semiconductor package
pad
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TW100121958A
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TWI453872B (zh
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洪良易
白裕呈
孫銘成
林俊賢
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矽品精密工業股份有限公司
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Priority to TW100121958A priority Critical patent/TWI453872B/zh
Priority to CN201110193715.XA priority patent/CN102842546B/zh
Priority to US13/242,462 priority patent/US8471383B2/en
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Abstract

一種半導體封裝件，係包括：具有相對之第一與第二表面及側面的介電層；銅材之線路層，係形成於該介電層之第一表面上，該線路層具有延伸墊；表面處理層，係形成於該線路層上；半導體晶片，係設於該線路層上並電性連接該表面處理層；以及形成於該介電層之第一表面上之封裝膠體，係包覆該半導體晶片、線路層及表面處理層，且外露該介電層之第二表面，又該介電層之側面與該封裝膠體之間具有通孔，使該延伸墊位於該通孔中。藉由外露於通孔之延伸墊結合銲球，因銅材與銲錫材料之間的電性連接較佳，故可提升電性連接之品質。本發明復提供該半導體封裝件之製法。

Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種無承載件之半導體封裝件。
傳統以導線架作為晶片承載件之半導體封件之型態及種類繁多，就四邊扁平無導腳(Quad Flat Non-leaded,QFN)半導體封裝件而言，其特徵在於未設置有外導腳，即未形成有如習知四邊形平面(Quad Flat package,QFP)半導體封裝件中用以與外界電性連接之外導腳，如此，將得以縮小半導體封裝件之尺寸。
然而伴隨半導體產品輕薄短小之發展趨勢，傳統導線架之QFN封裝件往往因其封裝膠體厚度之限制，而無法進一步縮小封裝件之整體高度，因此，業界便發展出一種無承載件(carrierless)之半導體封裝件，冀藉由減低習用之導線架厚度，以令其整體厚度得以較傳統導線架式封裝件更為輕薄。
請參閱第1圖，係為第5,830,800號美國專利所揭示之無承載件之半導體封裝件，該半導體封裝件1主要先於一銅板(未圖示)上形成多數電鍍銲墊14；再於該銅板上設置半導體晶片16並透過銲線17電性連接半導體晶片16及銲墊14，復進行封裝模壓製程以形成封裝膠體18，再移除該銅板而外露該銲墊14，接著以拒銲層11定義出該銲墊14位置，俾供植設銲球19於該銲墊14上，藉以完成該半導體封裝件1。相關之技術內容亦可參閱美國專利第6,770,959、6,989,294、6,933,594及6,872,661等。
前述銲墊之設置數目係大致因應佈設於晶片之作用表面上的電極墊數目，以使各晶片電極墊藉銲線電性連接至對應之銲墊。然而，當欲使用高度積集化(Highly Integrated)之晶片時，即該晶片具有數量較多或密度較高之電極墊，相對地需佈設較多銲墊，而使銲墊與晶片間之距離及銲線之弧長增加；過長之銲線不僅使銲線(Wire Bonding)作業之困難度提昇，且於形成封裝膠體之模壓(Molding)作業進行時，過長之銲線易受樹脂模流之衝擊而產生偏移(Sweep)或移位(Shift)現象，偏移或移位之銲線則可能彼此觸碰而導致短路(Short)問題，影響電性連接品質；再者，若銲墊與晶片間相距過遠，則可能使銲線作業難以進行，而造成無法藉銲線方式電性連接晶片至銲墊之情況。又，過長之銲線將增加材料成本。
鑒此，美國專利第7,638,879號遂揭示一種利用線路重佈置層(Redistribution layer,RDL)技術以使銲墊可延伸至鄰近晶片周圍，而減少銲線長度或交錯情況，且降低銲線之材料成本。如第2圖所示，該半導體封裝件2先將一介電層21藉由結合層200形成於一銅材之承載板20上，並於該介電層21上開設複數開孔210，且以電鍍方式形成鎳/金材25於各該開孔210中；再以電鍍方式形成銅材之線路層24於該介電層21與鎳/金材25上，且該線路層24之端部係為銲墊241；再設置半導體晶片26於該介電層21上，並藉銲線27電性連接該半導體晶片26與該銲墊241，且形成封裝膠體28以包覆該半導體晶片26及銲線27；最後移除該承載板20與結合層200，而使該介電層21及該鎳/金材25外露。
然，習知半導體封裝件2中，需以該鎳/金材25結合銲錫材料(圖未示)以接置於一電路板(圖未示)上，但該鎳/金材25與銲錫材料之間的電性及散熱效果不佳，導致電性連接之品質不佳。
再者，該承載板20係為銅材，其材料價格高，導致材料成本提高。
又，該半導體封裝件2接置於電路板上時，係先於該電路板之電性連接墊上形成0.1mm的銲錫膏，再將該鎳/金材25結合至該銲錫膏上。惟，若該半導體封裝件2發生翹曲(warpage)時，因該銲錫膏太薄，使該鎳/金材25無法接置於該銲錫膏上，因而導致電性連接不良。
因此，如何解決上述問題而能提供一種無承載件之半導體封裝件及其製法，以提升封裝件電性品質並降低成本，實為目前業界亟待解決之課題。
為克服習知技術之問題，本發明提供一種半導體封裝件，係包括：介電層，係具有相對之第一表面與第二表面、及相鄰該第一表面與第二表面之側面；銅材之線路層，係形成於該介電層之第一表面上；表面處理層，係形成於該線路層上；半導體晶片，係設於該線路層上並電性連接該表面處理層；以及封裝膠體，係形成於該介電層之第一表面上以包覆該半導體晶片、線路層及表面處理層，且外露該介電層之第二表面，又該介電層之側面與該封裝膠體之間具有通孔，使部分該表面處理層位於該通孔中。
前述之封裝件中，該線路層可具有延伸線路，該延伸線路之一端具有設於該介電層之第一表面上之第一接觸墊，該延伸線路之另一端係為形成於該表面處理層上以外露於該通孔之延伸墊。
前述之封裝件中，該銅材之線路層復可具有第二接觸墊，係形成於該介電層之第一表面上，且該半導體晶片係設於該第二接觸墊上，又該介電層之第二表面上具有複數連通該介電層之第一表面之開孔，以外露出該線路層之部分表面。
本發明復提供一種半導體封裝件之製法，係包括：提供一由鐵合金或銅合金所製之承載板，於該承載板之表面上定義承載區與鄰接該承載區外之延伸區；形成介電層於該承載板之承載區上，且該介電層係具有外露之第一表面、結合至該承載板上之第二表面、及相鄰該第一與第二表面之側面；形成銅材之線路層於該介電層之第一表面與該承載板延伸區之部分表面上，該線路層具有延伸線路，該延伸線路之兩端具有第一接觸墊與延伸墊，該第一接觸墊係形成於該介電層之第一表面上，而該延伸墊係形成於該承載板延伸區上；形成表面處理層於該線路層上；將半導體晶片設於該介電層之第一表面上且電性連接該表面處理層；於該承載板與該介電層之第一表面上形成封裝膠體，以包覆該半導體晶片與線路層，使該延伸墊位於該介電層側面與該延伸區上的封裝膠體之間；移除該承載板，以外露出該介電層之第二表面，且令該延伸墊外露於該介電層之第二表面與封裝膠體表面；以及移除部份該延伸墊，以於該介電層側面與該封裝膠體之間形成通孔。
前述之製法中，形成該線路層與表面處理層之製程，係包括：形成阻層於該介電層之第一表面與該承載板上，且於該阻層上形成複數第一開口，以外露出該承載板之延伸區及連通該延伸區之介電層部分第一表面；形成該線路層於該第一開口中；形成該表面處理層於該線路層上；以及移除該阻層，以外露該承載板延伸區之部分表面。
依上述製法，該阻層復形成有第二開口，以外露出該介電層之另一部分第一表面，且該線路層復形成於該第二開口中，故復包括於形成該阻層之前，於該介電層上形成複數開孔，以外露出該承載板之承載區表面，且該阻層之第二開口連通該開孔，而該線路層復形成於該第二開口及開孔中，當移除該承載板後，亦包括移除該開孔中之銅材，俾外露出線路層之部份表面，以作為第二接觸墊。再者，於移除部份該延伸墊時，同時移除部份該第二接觸墊，以形成銲球於該開孔中。又，前述之製法中，可包括移除該延伸墊之剩餘部份，以外露該表面處理層於該通孔中。
另外，前述之封裝件及其製法中，可形成銲球於該通孔中，且該表面處理層之結構係為形成於該線路層上之金層、形成於該金層上之鎳層、及形成於該鎳層上之金、鉛或銀材。
由上可知，本發明半導體封裝件及其製法，係藉由銅材之線路層之延伸墊外露於通孔，以結合銲球，因銅材與銲錫材料之間的電性連接較佳，且具有更好的導熱效果，故可提升電性連接之品質。
再者，本發明之製法中，該承載板係由鐵合金或銅合金所製，故成本相較於習知技術之純銅低，因而可降低材料成本。
又，本發明半導體封裝件接置於電路板上時，係可先形成銲球於該通孔中之延伸墊上，再將該銲球結合至0.1mm的銲錫膏上。若本發明半導體封裝件發生翹曲(warpage)時，可藉由銲球準確接置於該銲錫膏上，故不易發生電性連接不良之問題。
另外，依前述之本發明半導體封裝件及其製法，本發明復提供更具體技術，詳如後述。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“底”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第3A至3I圖，其係為本發明半導體封裝件之製法之剖面示意圖。
如第3A圖所示，提供一鐵合金或銅合金所製之承載板30，於該承載板30之表面上定義出承載區S與鄰接該承載區S外圍之延伸區E。
接著，形成一介電層31於該承載板30之全部承載區S上，且利用圖案化製程，於該介電層31上形成複數開孔310(本圖中以一個開孔310說明)，以外露出該承載板30承載區S之部分表面。於本實施例中，該介電層31具有外露之第一表面(如圖所示之上表面)31a、結合至該承載板30上之第二表面(如圖所示之下表面)31b、及相鄰該第一表面31a與第二表面31b之側面31c。
如第3B圖所示，形成導電層32於該介電層31之第一表面31a、側面31c、開孔310與該承載板30延伸區E表面上。
如第3C圖所示，再於該導電層32上形成阻層33，且於該阻層33上形成複數第一開口330，以外露出該承載板30部分延伸區E上之導電層32、及連通該延伸區E之介電層31側面31c與部分第一表面31a上之導電層32。
於本實施例中，該阻層33復形成有第二開口330’，以外露出該介電層31之另一部分第一表面31a，且該第二開口330’係連通該開孔310，以外露出該開孔310上之導電層32。
如第3D圖所示，藉由電鍍銅材之方式，形成線路層34於該第一及第二開口330,330’中之導電層32上與該開孔310中之導電層32上，該線路層34具有延伸線路340，該延伸線路340之兩端分別具有第一接觸墊341與延伸墊342，該第一接觸墊341係形成於該介電層31之第一表面31a上，而該延伸墊342係形成於該承載板30延伸區E上。
接著，形成表面處理層35於該線路層34上。於本實施例中，如第3D(a)圖所示，該表面處理層35之結構係為形成於該線路層34上之金層35a、形成於該金層35a上之鎳層35b、及形成該鎳層35b上之金、鉛或銀材35c。
如第3E圖所示，移除該阻層33及其覆蓋之導電層32，以外露出該承載板30延伸區E之部分表面。
如第3F圖所示，將半導體晶片36設於該承載區S之線路層34上，且以銲線37電性連接該表面處理層35與半導體晶片36。於其他實施例中，該半導體晶片亦可以覆晶方式電性連接該表面處理層。
接著，於該承載板30延伸區E之外露表面與該介電層31之第一表面31a上形成封裝膠體38，以包覆該半導體晶片36、銲線37與線路層34，使該延伸墊342位於該介電層31側面31c與該延伸區E上的封裝膠體38之間。
如第3G圖所示，移除該承載板30，以外露出該介電層31之第二表面31b與封裝膠體38底面，令該延伸墊342外露於該介電層31之第二表面31b與封裝膠體38底面，部分之線路層34亦外露於該開孔310，俾供作為第二接觸墊343。
如第3H圖所示，移除該延伸墊342之部分材質及其上之導電層32，以於該介電層31之側面31c與該封裝膠體38之間形成通孔380，且移除該開孔310中之銅材，俾外露出該第二接觸墊343。
於另一實施例中，移除該延伸墊342之剩餘部分與該第二接觸墊343，以外露該表面處理層35於該通孔380’及該開孔310’中，如第3H’圖所示。
再者，可進行切單製程，如第3G圖所示之切割線L，以取得單一半導體封裝件3,3’。
如第3I圖所示，形成銲球39於該通孔380中之延伸墊342上與該開孔310中之第二接觸墊343上。
再者，該半導體晶片36未電性連接該第二接觸墊343時，該第二接觸墊343可作散熱之用；該半導體晶片36電性連接該第二接觸墊343時，該第二接觸墊343可作電性傳導與散熱之用。
如第3I’圖所示，將該銲球39形成於該通孔380或該開孔310中之表面處理層35(金層35a)上，令該銲球39結合至該線路層34之側面34a，以提高電性及散熱效果。
本發明復提供一種半導體封裝件3,3’，係包括：介電層31，係具有相對之第一表面31a與第二表面31b、及相鄰該第一表面31a與第二表面31b之側面31c；銅材之線路層34，係形成於該介電層31之第一表面31a上；表面處理層35，係形成於該線路層34上；半導體晶片36，係設於該線路層34上方並電性連接該線路層34與表面處理層35；以及封裝膠體38，係形成於該介電層31之第一表面31a上以包覆該半導體晶片36、線路層34及表面處理層35，且外露該介電層31之第二表面31b，又該介電層31之側面31c與該封裝膠體38之間具有通孔380,380’，以於該通孔380,380’中形成銲球39。
於一實施態樣中，部分該表面處理層35位於該通孔380中，且該線路層34具有延伸線路340，該延伸線路340之一端具有設於該介電層31之第一表面31a上之第一接觸墊341，該延伸線路340之另一端係為形成於該表面處理層35上而外露於該通孔380之延伸墊342。
於另一實施態樣中，係部分該表面處理層35外露於該通孔380’中。
於該半導體封裝件3,3’中，該線路層34具有第二接觸墊343，係形成於該介電層31之第一表面31a上，令該半導體晶片36設於該第二接觸墊343上方。再者，該介電層31之第二表面31b上具有複數連通該介電層31之第一表面31a之開孔310,310’，以外露出該線路層34之部分表面(如第二接觸墊343)或該表面處理層35。又包括形成於該開孔310,310’中之銲球39，以電性連接該線路層34。
另外，該表面處理層35之結構係為形成於該線路層34上之金層35a、形成於該金層35a上之鎳層35b、及形成於該鎳層35b上之金、鉛或銀材35c。
綜上所述，本發明半導體封裝件3及其製法，係藉由銅材之延伸墊342外露於該介電層31之側面31c與該封裝膠體38之間的通孔380、或第二接觸墊343外露於該開孔310，以結合銲球39；相較於習知技術，本發明半導體封裝件3因銅材(延伸墊342)與銲錫材料(銲球39)之間的電性連接較佳，故有效提升電性連接之品質，且具有更好的導熱效果。
再者，本發明半導體封裝件3之製法中，該承載板30係由鐵合金或銅合金所製，故成本相較於習知技術之純銅低，因而可降低材料成本。
又，如第4圖所示，將本發明半導體封裝件3接置於一電路板4上時，係用形成於該延伸墊342上之銲球39結合至該電路板4上之厚度d約為0.1mm之銲錫膏40上。因該銲球39之凸出高度h約為0.3mm，故可提供較高之接合凸塊(stand-off)，若本發明半導體封裝件3發生翹曲(warpage)時，仍可藉由銲球39有效接置於該銲錫膏40上，因而不會發生電性連接不良之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,3,3’．．．半導體封裝件
11．．．拒銲層
14,241．．．銲墊
16,26,36．．．半導體晶片
17,27,37．．．銲線
18,28,38．．．封裝膠體
19,39．．．銲球
20,30．．．承載板
200．．．結合層
21,31．．．介電層
210,310,310’．．．開孔
24,34．．．線路層
25．．．鎳/金材
31a．．．第一表面
31b．．．第二表面
31c,34a．．．側面
32．．．導電層
33．．．阻層
330．．．第一開口
330’．．．第二開口
340．．．延伸線路
341．．．第一接觸墊
342．．．延伸墊
343．．．第二接觸墊
35．．．表面處理層
35a．．．金層
35b．．．鎳層
35c．．．金、鉛或銀材
380,380’．．．通孔
4．．．電路板
40．．．銲錫膏
L．．．切割線
E．．．延伸區
S．．．承載區
d．．．厚度
h．．．凸出高度
第1圖係顯示美國專利第5,830,800號之無承載件之半導體封裝件之剖面示意圖；
第2圖係顯示美國專利第7,638,879號之無承載件之半導體封裝件之剖面示意圖；
第3A至3I圖係為本發明半導體封裝件之製法之剖面示意圖；其中，第3D(a)圖係為第3D圖之局部放大圖，第3H’及3I’圖係為第3H及3I圖之另一種實施態樣；以及
第4圖係為本發明半導體封裝件接置電路板之剖面示意圖。
3．．．半導體封裝件
31．．．介電層
31a．．．第一表面
31b．．．第二表面
31c．．．側面
310．．．開孔
34．．．線路層
340．．．延伸線路
341．．．第一接觸墊
342．．．延伸墊
343．．．第二接觸墊
35．．．表面處理層
36．．．半導體晶片
37．．．銲線
38．．．封裝膠體
380．．．通孔

Claims (16)

  1. 一種半導體封裝件，係包括：介電層，係具有相對之第一表面與第二表面、及相鄰該第一表面與第二表面之側面；銅材之線路層，係形成於該介電層之第一表面上；表面處理層，係形成於該線路層上；半導體晶片，係設於該線路層上方並電性連接該線路層與表面處理層；以及封裝膠體，係形成於該介電層之第一表面上以包覆該半導體晶片、線路層及表面處理層，且外露該介電層之第二表面，又該介電層之側面與該封裝膠體之間具有通孔，使部分該表面處理層位於該通孔中。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路層具有延伸線路，該延伸線路之一端具有設於該介電層之第一表面上之第一接觸墊，該延伸線路之另一端係為形成於該表面處理層上而外露於該通孔之延伸墊。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路層具有第二接觸墊，係形成於該介電層之第一表面上，令該半導體晶片設於該第二接觸墊上方。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該介電層之第二表面上具有複數連通該介電層之第一表面之開孔，以外露出該線路層之部分表面。
  5. 如申請專利範圍第4項所述之半導體封裝件，復包括形成於該開孔中之銲球，以電性連接該線路層。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該表面處理層之結構係為形成於該線路層上之金層、形成於該金層上之鎳層、及形成於該鎳層上之金、鉛或銀材。
  7. 如申請專利範圍第1項所述之半導體封裝件，復包括形成於該通孔中之銲球。
  8. 一種半導體封裝件之製法，係包括：提供一承載板，於該承載板之表面上定義承載區與鄰接該承載區外之延伸區；形成介電層於該承載板之承載區上，且該介電層係具有外露之第一表面、結合至該承載板上之第二表面、及相鄰該第一與第二表面之側面；形成銅材之線路層於該介電層之第一表面與該承載板延伸區之部分表面上，該線路層具有延伸線路，該延伸線路之兩端具有第一接觸墊與延伸墊，該第一接觸墊係形成於該介電層之第一表面上，而該延伸墊係形成於該承載板延伸區上；形成表面處理層於該線路層上；將半導體晶片設於該介電層之第一表面上且電性連接該表面處理層；於該承載板與該介電層之第一表面上形成封裝膠體，以包覆該半導體晶片與線路層，使該延伸墊位於該介電層側面與該延伸區上的封裝膠體之間；移除該承載板，以外露出該介電層之第二表面，且令該延伸墊外露於該介電層之第二表面與封裝膠體表面；以及移除部份該延伸墊，以於該介電層側面與該封裝膠體之間形成通孔。
  9. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，形成該承載板之材質係為鐵合金或銅合金。
  10. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，形成該線路層與表面處理層之製程，係包括：形成阻層於該介電層之第一表面與該承載板上，且於該阻層上形成複數第一開口，以外露出該承載板之延伸區及連通該延伸區之介電層部分第一表面；形成該線路層於該第一開口中；形成該表面處理層於該線路層上；以及移除該阻層，以外露該承載板延伸區之部分表面。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該阻層復形成有第二開口，以外露出該介電層之另一部分第一表面，且該線路層復形成於該第二開口中。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括於形成該阻層之前，於該介電層上形成複數開孔，以外露出該承載板之承載區表面，且該阻層之第二開口連通該開孔，而該線路層復形成於該第二開口及開孔中，當移除該承載板後，復包括移除該開孔中之銅材，俾外露出線路層之部份表面，以作為第二接觸墊。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，復包括於移除部份該延伸墊時，同時移除部份該第二接觸墊，以形成銲球於該開孔中。
  14. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，該表面處理層之結構係為形成於該線路層上之金層、形成於該金層上之鎳層、及形成該鎳層上之金、鉛或銀材。
  15. 如申請專利範圍第8項所述之半導體封裝件之製法，復包括移除該延伸墊之剩餘部份，以外露該表面處理層於該通孔中。
  16. 如申請專利範圍第8項所述之半導體封裝件之製法，復包括形成銲球於該通孔中。
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